Intel® 3200/3210 Chipset Memory Controller Hub (MCH) Specification Update December 2007 Document Number: 318464-002
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Contents 1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Summary Tables of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Identification Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® 3200/3210 Chipset Memory Controller Hub (MCH) Specification Update
Revision History 1 Revision History Revision Description Date -001 • Initial Release November 2007 -002 • Added Errata 2 December 2007 Intel® 3200/3210 Chipset Memory Controller Hub (MCH) Specification Update 5
Preface 2 Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.
Summary Tables of Changes 3 Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the MCH product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations: 3.1 Codes Used in Summary Tables 3.1.
Summary Tables of Changes 3.2 Number Steppings Status ERRATA X No Fix PCIe 1.1 cards in PCIe slots off the MCH lead to boot failures. X No Fix IERR due to DMI/PCIe Link Not Trained A0 A1 1 X 2 X 3.3 No. - 3.4 No. - 3.5 No. - 8 Errata Specification Changes SPECIFICATION CHANGES There are no Specification Changes in this Specification Update revision. Specification Clarifications SPECIFICATION CLARIFICATIONS There are no Specification Changes in this Specification Update revision.
Identification Information 4 Identification Information 4.1 Component Marking Information The Intel® 3200/3210 Chipset MCH stepping can be identified by the following component markings: Stepping Top Marking Notes A1 NU3210MC SLALH Intel® 3210 Chipset MCH - Production A1 NU3200MC SLALG Intel® 3200 Chipset MCH - Production In future samples releases, Intel® 3210 Chipset MCH and Intel® 3200 Chipset MCH can be identified by the presence or absence of Bus 0, Device 6.
Errata 5 Errata 1. PCIe 1.1 cards in PCIe slots off the MCH lead to boot failures. Problem: The Intel® X38 Express Chipset sets the TS1 Ordered Set - Symbol 4 Bit[6] to 1b when a PCIe 1.1 card is plugged in. This is a reserved bit which is used in PCIe 2.0 to broadcast support for selectable de-emphasis. PCIe 1.1 Specification states that Bit[6] should be set to 0b. With some 2.5 GT/s PCIe 1.
Specification Changes 6 Specification Changes There are no Specification Changes in this Specification Update revision. 7 Specification Clarifications There are no Specification Clarifications in this Specification Update revision. 8 Documentation Changes There are no Documentation Changes in this Specification Update revision.
Documentation Changes 12 Intel® 3200/3210 Chipset Memory Controller Hub (MCH) Specification Update
