Intel® Xeon® Processor 7000 Series Specification Update March 2010 Notice: The Intel® Xeon® Processor 7000 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
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Contents Contents Revision History ........................................................................................................ 5 Preface ...................................................................................................................... 6 Identification Information ......................................................................................... 8 Summary Tables of Changes.................................................................................... 11 Errata .
Contents 4 Intel® Xeon® Processor 7000 Series Specification Update, March 2010
Revision History Version Description -001 Initial release of the Dual-Core Specification Update. -002 Added erratum A57. Intel® Xeon® Date Processor 7000 Series November 2005 December 2005 -003 Updated erratum A17; added errata A58-A79. January 2006 -004 In Documentation changes, updated reference to IA-32 Intel® Architecture Software Developer’s Manual to reflect volumes 3A and 3B. Added Errata A80-A84. April 2006 -005 Added AE and AF to the Codes Used in Summary Table. Added erratum A85.
Preface This document is an update to the specifications contained in the Affected Documents and Related Documents tables below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.
Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification. Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification. Documentation Changes include typos, errors, or omissions from the current published specifications.
Identification Information The Intel® Xeon® Processor 7000 Series can be identified by the following register contents: Extended Family1 Extended Model2 Type3 Family4 Model5 00000000b 0000b 00b 1111b 0100b NOTES: 1. 2. 3. 4. 5. The Extended Family corresponds to bits [27:20] of the EDX register after RESET, bits [27:20] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.
Package Markings Figure 1 shows the production topside markings and Figure 2 shows thebottom-side markings on the processor. These diagrams are to aid in the identification of the Intel® Xeon® Processor 7000 Series . Please note that the figures in this section are not to scale. Intel® Xeon® Processor 7000 Sequence Package Markings Figure 1.
Intel® Xeon® Processor 7000 Series Specifiication Update, March 2010
Summary Tables of Changes The following table indicates the Errata, Specification Changes, Specification Clarifications, or Documentation Changes which apply to the Intel® Xeon® Processor 7000 Series . Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations: Codes Used in Summary Table Stepping X: Errata exists in the stepping indicated.
M= Mobile Intel® Celeron® processor N= Intel® Pentium® 4 processor O= Intel® Xeon® processor MP P= Intel® Xeon® processor Q= Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology on 90-nm process technology R= Intel® Pentium® 4 processor on 90 nm process S= 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) T= Mobile Intel® Pentium® 4 processor-M U= 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache V= Mobile Intel® Celeron® process
AS = Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series AT = Intel® Celeron® Processor 200 Series AV = Intel® Core™2 Extreme processor QX9000Δ series and Intel® Core™2 Quad processor Q9000Δ series AW = Intel® Core™ 2 Duo processor E8000 series AX = Quad-Core Intel® Xeon® processor 5400 series AY = Dual-Core Intel® Xeon® processor 5200 series AZ = Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Process AAA = Quad-Core Intel® Xeon® pr
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Errata A1. Transaction is not retired after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, the transaction will not be retried. Implication: When this erratum occurs, locked transactions will not be retried. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. A2.
Unlocks having different memory types) does not however introduce any functional failures such as system hangs or memory corruption. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. A5. Machine check architecture error reporting and recovery may not work as expected Problem: When the processor detects errors it should attempt to report and/or recover from the error.
• If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction become corrupted, the processor will signal a Machine Check Exception (MCE). If the instruction is directed at a device that is powered down, the processor may also receive an assertion of SMI#. Since MCEs have higher priority, the processor will call the MCE handler, and the SMI# assertion will remain pending.
Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. A6. Debug mechanisms may not function as expected Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, the transaction will not be Certain debug mechanisms may not function as expected on the processor.
Status: For the steppings affected, see the Summary Table of Changes. A9. System bus interrupt messages without data and which receive a hard-failure response may hang the processor Problem: When a System Bus agent (processor or chipset) issues an interrupt transaction without data onto the System Bus, and the transaction receives a hard-failure response, a potential processor hang can occur.
A13. When the processor is in the system management mode (SMM), debug registers may be fully writeable Problem: When in system management mode (SMM), the processor executes code and stores data in the SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the processor should block writes to the reserved bit locations. Due to this erratum, the processor may not block these writes. This may result in invalid data in the reserved bit locations.
A17. A write to an APIC register sometimes may appear to have not occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memorybased APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g. CLI, is executed soon after an uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the actual priority has been lowered.
A21. xAPIC may not report some illegal vector error Problem: The local xAPIC has an Error Status Register, which records all errors it detects. Bit 6 of this register, the Receive Illegal Vector bit, is set when the local xAPIC detects an illegal vector in a message that it receives. When an illegal vector error is received on the same internal clock that the error status register is being written due to a previous error, bit 6 does not get set and illegal vector errors are not flagged.
A25. Using STPCLK# and executing code from very slow memory could lead to a system hang Problem: The system may hang when the following conditions are met: 1. Periodic STPCLK# mechanism is enabled via the chipset 2. Hyper-Threading Technology is enabled 3. One logical processor is waiting for an event (i.e. hardware interrupt) 4. The other logical processor executes code from very slow memory such that every code fetch is deferred long enough for the STPCLK# to be re-asserted.
reported by CPUID instruction 0x8000008. This erratum applies whenever PAE is enabled. Implication: Software that sets the upper address bits on a MOV CR3 instruction and expects a fault may fail. This erratum has not been observed with commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. A30.
An FXRSTOR instruction executed with 64-bit operand size may signal a General Protection Fault (#GP) if the FDP or FP instruction pointer (FIP) is in non-canonical form. Implication: When this erratum occurs, Intel EM64T enabled systems may encounter an unintended #GP fault. Workaround: Software should avoid using non-canonical effective addressing in Intel EM64T enabled processors. BIOS can contain a workaround for this erratum removing the unintended #GP fault on FXRSTOR.
A38. With trap flag (TF) asserted, FP instruction that triggers an unmasked FP exception may take single step trap before retirement of instruction Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for external events to occur, including a transition to a lower power state. When resuming from the lower power state, it may be possible to take the single step trap before the execution of the original FP instruction completes.
b. Update the associated cache line state information to shared state on the originating bus (rather than invalid state) in reaction to a BWIL or BLW. Status: For the steppings affected, see the Summary Table of Changes. A41.
A45. Data access which spans both canonical and non-canonical address space may hang system Problem: If a data access causes a page split across the canonical to non-canonical address space, the processor may livelock which in turn would cause a system hang. Implication: When this erratum occurs, the processor may livelock, resulting in a system hang. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
A49. At core-to-bus ratios of 16:1 and above defer reply transactions with non-zero REQb Values; may cause a front side bus stall Problem: Certain processors are likely to hang the front side bus (FSB) if the following conditions are met: 1. A Defer Reply transaction has a REQb[2:0] value of either 010b, 011b, 100b, 110b, or 111b, and 2. The operating bus ratio is 16:1 or higher.
system may be susceptible to a variety of failing symptoms including; system hangs and MCERR# or IERR# assertions. Implication: POC can not be used to enter single logical processor mode. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. A54.
can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte boundary before pushing the stack frame. Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment checks are disabled at the start of the IRET.
A62. VM exit on Load Machine Status Word (LMSW) may not show expected exit information in the Virtual-Machine Control Structure (VMCS) Problem: In systems supporting Intel Virtualization Technology, a VM exit on an LMSW instruction, which references memory, may not return expected exit information concerning data breakpoints in the VMCS.
A67. The processor may incorrectly respond to machine checks during VM entry/exit transitions Problem: In systems supporting Intel Virtualization Technology, when machine checks are encountered during VM entry/exit transitions, the processor is expected to respond with a VM exit (if a machine check occurs during VM entry) or abort (if a machine check occurs during VM exit).
Status: For the steppings affected, see the Summary Table of Changes. A71. VM exit due to TPR shadow below threshold may improperly set and cause “Blocking by STI” actions Problem: In a system supporting Intel Virtualization Technology and Intel EM64T, the “blocking by STI” bit of the interruptibility-state field may be saved as 1 rather than 0.
Implication: This erratum may cause a load to an unexpected memory address. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes. A76.
Workaround: Software should ensure that “host address-space size” VM exit control has the same value as IA32_EFER.LMA at the time of VMLAUNCH/VMRESUME. Status: For the steppings affected, see the Summary Table of Changes. A80.
A83. Processor may hang during entry into No-Fill Mode or No-Eviction Mode Problem: Only one logical processor per core can be active when processor is put in No-Fill Mode or No-Eviction Mode. If the other logical processor is active or there is an internal or external event pending to wake that logical processor, the processor may hang when writing to MSR IA32_BIOS_CACHE_AS_RAM (80H). Implication: A processor may hang due to this erratum.
A87. VMEntry from 64-bit Host to 32-bit Guest may Cause IERR# with Hyper-Threading Enabled Problem: When transitioning from a 64-bit host environment to a 32-bit guest environment via a VMEntry, internal conditions in a processor with Hyper-Threading enabled may cause a page-table walk to be prematurely terminated, resulting in a processor hang and the assertion of IERR#. Implication: An IERR# may occur on VMEntry from a 64-bit to a 32-bit environment with HyperThreading enabled.
Specification Changes There are no new Specification Changes for this revision. The Specification Changes listed in this section apply to the following documents: 1. Intel® Xeon® Processor 7000 Series Datasheet (Order Number 309626-003) All Specification Clarifications will be incorporated into a future version of the appropriate Intel® Xeon® Processor 7000 Series documentation.
Specification Clarifications There are no new Specification Clarifications for this revision. The Specification Clarifications listed in this section apply to the following documents: 1. Intel® Xeon® Processor 7000 Series Datasheet (Order Number 309626-003) All Specification Clarifications will be incorporated into a future version of the appropriate Intel® Xeon® Processor 7000 Series documentation.
Documentation Changes There are no new Documentation Changes for this revision. The Documentation Changes listed in this section apply to the following documents: 1. Intel® Xeon® Processor 7000 Series Datasheet (Order Number 309626-003) All Documentation Changes will be incorporated into a future version of the appropriate Intel® Xeon® Processor 7000 Series documentation.
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