Intel® E7505 Chipset Memory Controller Hub (MCH) Datasheet December 2002 Document Number: 251932-002
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Contents 1 Introduction ................................................................................................................15 1.1 1.2 1.3 2 Signal Description ...................................................................................................21 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 Terminology.........................................................................................................15 Reference Documents............................................................
3.5.16 3.5.17 3.5.18 3.5.19 3.5.20 3.5.21 3.6 4 PAM[0:6]—Programmable Attribute Map Registers (D0:F0).................. 56 DRB—DRAM Row Boundary Register (D0:F0) ..................................... 58 DRA—DRAM Row Attribute Register (D0:F0) ....................................... 60 DRT—DRAM Timing Register (D0:F0) .................................................. 61 DRC—DRAM Controller Mode Register (D0:F0) ...................................
3.6.24 3.6.25 3.6.26 3.6.27 3.6.28 3.6.29 3.7 3.8 DRAM_FERR—DRAM First Error Register (D0:F1) ..............................94 DRAM_NERR—DRAM Next Error Register (D0:F1) .............................94 SCICMD_DRAM —SCI Command Register (D0:F1) .............................95 SMICMD_DRAM—SMI Command Register (D0:F1) .............................95 SERRCMD_DRAM—SEER Command Register (D0:F1) ......................96 DRAM_CELOG_ADD—DRAM First Correctable Memory Error Address Register (D0:F1)96 3.6.
3.9 4 System Address Map............................................................................................ 145 4.1 4.2 4.3 6 3.8.7 BCC2—Base Class Code Register (D2:F0)......................................... 126 3.8.8 MLT2—Master Latency Timer (Scratch Pad) Register (D2:F0) ........... 127 3.8.9 HDR2—Header Type Register (D2:F0)................................................ 127 3.8.10 PBUSN2—Primary Bus Number Register (D2:F0) .............................. 127 3.8.
4.4 5 Functional Description.........................................................................................155 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6 Memory Re-claim Background ..........................................................................154 4.4.1 Memory Re-mapping............................................................................154 System Bus Overview .......................................................................................155 5.1.
7 Ballout and Package Information .................................................................... 183 7.1 7.2 7.3 8 Testability .................................................................................................................. 215 8.1 8 Ballout Assignment ........................................................................................... 183 Package Specifications .....................................................................................
Figures 1-1 2-1 3-1 3-2 4-1 4-2 4-3 7-1 7-2 7-3 7-4 7-5 8-1 Dual-Processor System Block Diagram ..............................................................19 MCH Interface Signals ........................................................................................22 PAM Registers ....................................................................................................57 Memory Socket Rows Description ......................................................................
6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 10 Signal Groups System Bus Interface ................................................................ 175 Signal Groups DDR Interface............................................................................ 175 Signal Groups AGP Interface............................................................................ 176 Signal Groups Hub Interface 2.0 (HI_B) ...............................
Revision History Revision -001 -002 Description Date Initial Release November 2002 Addidtion of 1.3V MCH Core Voltage data December 2002 Update ICC requirments for 1.2 V and 1.
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Intel® E7505 Chipset MCH Features ■ Processor/Host Bus Support — Symmetric Multiprocessing Protocol (SMP) for up to two processors — 533 MHz or 400 MHz (2x address, 4x data) — System Bus Dynamic Bus Inversion (DBI) — 36-bit host bus addressing — 12-deep in-order queue — 2-deep defer queue (only one per HI) — AGTL+ bus driver technology with on-die termination resistors — Parity protection on host bus Data, Address/ Request, and Response signals ■ Memory System — Dual Channel (144-bits wide) DDR memory inte
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Introduction 1 Introduction The Intel® E7505 chipset is a high-performance chipset designed as the next generation workstation. The main components of the chipset are the Memory Controller Hub (MCH) host bridge and the Intel® 82801BA I/O Controller Hub 4 (ICH4) for the I/O subsystem. A supporting component for the platform is the Intel® 82870P2 PCI-64 Hub 2 (P64H2) for I/O expansion.
Introduction Term Description MCH The Memory Controller Hub component contains the processor interface and system memory interface. The MCH communicates with the I/O Controller Hub 4 (ICH4) and other controller hubs over a proprietary interconnect called the Hub Interface. Intel® The PCI-64 Hub 2 component adds PCI-X functionality to the chipset.The P64H2 connects to the MCH over a proprietary interconnect called the Hub Interface 2.0.
Introduction NOTES: 1. Contact your local Intel representative for the latest revision and document number for this document. 2. Refer to the Intel® Xeon™ Processor and Intel® E7505 Chipset Platform Design Guide for an expanded set of reference documents.
Introduction 1.3 Intel® E7505 Chipset System Architecture The Intel® E7505 chipset is optimized for the Intel® Xeon™ processor with 512 KB L2 cache. The architecture of the chipset provides the performance and feature-set required for dual-processor based workstations in the volume and performance market segments. The MCH supports AGP 8x with backwards compatibility to AGP 4x. The AGP interface is fully compliant with the AGP Specification 3.0.
Introduction Figure 1-1. Dual-Processor System Block Diagram Processor Processor 133/100 MHz DDR Channel A AGP Device Intel® E7505 Memory Controller Hub (MCH) 8x AGP HI_A USB 2.0 (6 ports) 8-Bit HI 1.5 ATA-100 (4 drives) SMBus 2.0 GPIOs HI_B Main Memory (16 GB Max) 200/266 MHz DDR Interface DDR Channel B 16-Bit HI 2.
Introduction 20 Intel® E7505 Chipset MCH Datasheet
Signal Description Signal Description 2 This chapter provides a detailed description of MCH signals. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present after the signal name, the signal is asserted when at a high voltage level.
Signal Description Figure 2-1.
Signal Description 2.1 Host Interface Signals Table 2-1. Host Interface Signals (Sheet 1 of 3) Signal Name ADS# Type I/O AGTL+ Description Address Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. Address Parity: The AP[1:0]# lines are driven by the request initiator and provide parity protection for the Request Phase signals. AP[1:0]# are common clock signals and are driven one common clock after the Request Phase.
Signal Description Table 2-1. Host Interface Signals (Sheet 2 of 3) Signal Name DRDY# Type I/O AGTL+ I/O HA[35:3]# GTL+ 2x I/O HADSTB[1:0]# AGTL+ 2x I/O HD[63:0]# AGTL+ 4x Description Data Ready: This signal is asserted for each cycle that data is transferred. Host Address Bus: HA[35:3]# connect to the system address bus. During processor cycles, HA[35:3]# are inputs. The MCH drives HA[35:3]# during snoop cycles on behalf of HI initiators. HA[35:3] are transferred at 2x rate.
Signal Description Table 2-1. Host Interface Signals (Sheet 3 of 3) Signal Name Type HXRCOMP, I/O HYRCOMP GTL+ HXSWNG, I HYSWNG Analog HDVREF[3:0] HAVREF[1:0] CCVREF I Analog I Analog I Analog Intel® E7505 Chipset MCH Datasheet Description Host RCOMP: These signals are used to calibrate the Host GTL+ I/O buffers. Since the Host GTL+ IO buffers cover two sides of the die, HXRCOMP is for the signals on one side of the die, and HYRCOMP handles signals on the other side of the die.
Signal Description 2.2 DDR Channel A Signals Table 2-2. DDR Channel A Signals (Sheet 1 of 3) Signal Name CB_A[7:0] DQ_A[63:0] DQS_A[17:0] Type I/O SSTL-2 I/O SSTL-2 I/O SSTL-2 Description ECC Data bits: These signals are the 8-bit ECC data, running at 2x data rate. The data is source synchronous using the DQS strobes. Data: These signals are the 64-bit data bus, running at 2x data rate. The data is source synchronous using the DQS strobes.
Signal Description Table 2-2. DDR Channel A Signals (Sheet 2 of 3) Signal Name Type Description Chip Select: The chip select inputs determine which row a command is targeting. There is one per row (2 per DIMM). Multiplexed Chip Selects and clocks: These signals are chip select outputs on a three-DIMM motherboard supporting registered DIMMs only, and clock outputs on a two DIMM motherboard which supports unbuffered or registered DIMMs. A configuration bit determines their function.
Signal Description Table 2-2. DDR Channel A Signals (Sheet 3 of 3) Signal Name Type Description Clock Enable: CKE_x high activates, and CKE_x low deactivates the internal clock signals, and device input buffers and output drivers. Driving CKE_x low provides precharge powerdown and self refresh operation (all banks idle), or Active Powerdown (row active in any bank). CKE_x is synchronous for powerdown entry and exit, and for self refresh entry.
Signal Description 2.3 DDR Channel B Signals Table 2-3. DDR Channel B Signals (Sheet 1 of 3) Signal Name CB_B[7:0] DQ_B[63:0] DQS_B[17:0] Type I/O SSTL-2 I/O SSTL-2 I/O SSTL-2 Description ECC Data bits: These signals are the 8-bit ECC data, running at 2x data rate. The data is source synchronous using the DQS strobes. Data: These signals are the 64-bit data bus, running at 2x data rate. The data is source synchronous using the DQS_x strobes.
Signal Description Table 2-3. DDR Channel B Signals (Sheet 2 of 3) Signal Name Type Description Differential Clock: Output to DIMMs. Commands are referenced to the rising edge of CMDCLK_x and the falling edge of CMDCLK_x#. One per DIMM for registered DIMMs, three per DIMM for unbuffered DIMMs.
Signal Description Table 2-3. DDR Channel B Signals (Sheet 3 of 3) Signal Name CAS_B# WE_B# Type O SSTL-2 O SSTL-2 Description Column Address Strobe: This signal is used to indicate a read or write command to the open page in the bank specified by the BA_x signals. CAS_B# is also used to enter register set mode or start an auto refresh or enter self refresh. Write Enable: This signal is used to differentiate a read from a write command when CAS_B# is active and RAS_B# is inactive.
Signal Description 2.4 Hub Interface_A Signals Table 2-4. Hub Interface_A Signals Signal Name Type HI_A[11:0] (as/t/s) I/O HI2 PRCOMP_A PREF_A I/O HI2 I Analog I/O PSTRBF_0 (as/t/s) HI2 I/O PSTRBS_0 (as/t/s) HI2 PSWNG_A 2.5 I Analog Description HI_A Signals: These signals are used for the hub interface between the Intel® ICH4 and the MCH. Compensation for HI: This signal is used to calibrate the HI_A I/O Buffers. HI_A Reference: This signal is the reference voltage input for HI_A.
Signal Description 2.6 AGP Interface Signals 2.6.1 AGP Arbitration Signals Table 2-6. AGP Arbitration Signals Signal Name Type Description GREQ# (2.0) GREQ (3.0) I Request: This signal is the output of the AGP device used to request access to the bus to initiate a PCI (GFRAME(#)) or AGP (PIPE#) request. This signal is not required to initiate an AGP request via SBA. GGNT# (2.0) GGNT (3.
Signal Description 2.6.2 AGP Address / Data Signals Table 2-7. AGP Address/ Data Signals Signal Name GDEVSEL# (2.0), GDEVSEL (3.0) GAD[31:0] Type I/O s/t/s AGP I/O AGP GC/BE[3:0]# (2.0), I/O GC#/BE[3:0] (3.0) AGP GPAR I/O AGP Description Device Select: During GFRAME(#) based accesses, GDEVSEL(#) is driven active by the target to indicate that it is responding to the access.
Signal Description 2.6.3 AGP Command/Control Signals Table 2-8. AGP Command/ Control Signals (Sheet 1 of 2) Signal Name Type Description Pipelined Read: This signal is asserted by the current master to indicate a full width address is to be enqueued by the target. The master enqueues one request each rising clock edge while PIPE# is asserted. When PIPE# is deasserted, no new requests are re-queued across the AD bus. PIPE# may be used in AGP 2.0 signaling modes, but is not permitted by the AGP 3.
Signal Description Table 2-8. AGP Command/ Control Signals (Sheet 2 of 2) Signal Name GTRDY# (2.0), GTRDY (3.0) GSTOP# (2.0), GSTOP (3.0) RBF# (2.0), RBF (3.0) Type I/O s/t/s AGP I/O s/t/s AGP I/O s/t/s AGP WBF# (2.0), I WBF (3.0 AGP Description Target Ready: This signal is used for both GFRAME(#) based and AGP transactions.
Signal Description 2.7 Clocks, Reset, and Miscellaneous Signals Table 2-9. Clocks, Reset, and Miscellaneous Signals Signal Name Type Description HCLKINP I HCLKINN DiffCLK Differential Host Clock In: These pins receive a differential host clock from the external clock synthesizer. This clock is used by all the Intel® E7505 chipset MCH logic in the host clock domain. GCLKIN PWRGD I CMOS I CMOS 66 MHz Clock In: This pin receives a 66 MHz clock from the clock synthesizer.
Signal Description 2.8 Strap Signals Pin DDR_STRAP HA7# Strap Name I CMOS CPU Bus InOrder Queue Depth Description DDR Strap Input. This pin is used to indicate to the BIOS the memory type. This pin should be grounded on a motherboard implementing registered DDR DIMMs. It should be pulled up to 2.5 V on a motherboard implementing unbuffered DDR DIMMs. The value on HA7# is sampled by all processor bus agents, including the MCH, on the rising edge of CPURST#.
Register Description 3 Register Description This chapter describes the MCH PCI configuration registers. A detailed register bit description is provided.
Register Description Term 3.2 Description Reserved Registers In addition to reserved bits within a register, the MCH contains address locations in the configuration space of the Host-hub interface Bridge/DRAM Controller and the internal graphics device entities that are marked either “Reserved” or Intel Reserved.” When a “Reserved” register location is read, a random value can be returned. (“Reserved” registers can be 8, 16, or 32 bits in size).
Register Description A disabled or non-existent device’s configuration register space is hidden, returning all 1s for reads and dropping writes just as if the cycle terminated with a Master Abort on PCI. The MCH automatically detects if devices are connected to HI_B by sampling the corresponding REQI signal on the rising edge of RSTIN#.
Register Description 3.3.1 Logical PCI Bus #0 Configuration Mechanism The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONFIG_ADDRESS register. When the Bus Number field of CONFIG_ADDRESS is 0, the configuration cycle is targeting a PCI Bus #0 device. • The Host-HI_A Bridge entity within the MCH is hardwired as Device 0 on PCI Bus #0 • The AGP Bridge entity within the MCH is hardwired as Device 1 on PCI Bus #0.
Register Description 3.3.4 AGP Bus Configuration Mechanism From the chipset configuration perspective, AGP is seen as a PCI bus interface residing on a Secondary Bus side of the virtual PCI-to-PCI bridges referred to as the MCH Host-to-AGP bridge. On the Primary bus side, the virtual PCI-to-PCI bridge is attached to PCI Bus #0. Therefore, the Primary Bus Number register is hardwired to 0.
Register Description 3.4.1 CONFIG_ADDRESS—Configuration Address Register Address Offset: Default Value: Attribute: Size: 0CF8h 0000 0000h R/W 32 bits CONFIG_ADDRESS is a 32-bit register that can be accessed only as a Dword. A “byte” or “word” reference will pass through the Configuration Address register and HI_A onto the PCI_A bus as an I/O cycle.
Register Description 3.5 Chipset Host Controller Registers (Device 0, Function 0) The Chipset Host Controller registers are in Device 0 (D0), Function 0 (F0). Table 3-2 provides the register address map for this device, function. Warning: Address locations that are not listed the table are considered reserved register locations. Writes to “Reserved” registers may cause system failure. Reads to “Reserved” registers may return a nonzero value. Table 3-2.
Register Description Table 3-2. Chipset Host Controller Register Address Map (D0:F0) 3.5.
Register Description 3.5.3 PCICMD—PCI Command Register (D0:F0) Address Offset: Default Value: Attribute: Size: 04–05h 0006h RO, R/W 16 bits Since MCH Device 0 does not physically reside on PCI_A many of the bits are not implemented. Bits Default, Access 15:10 9 Description Reserved 0b RO Fast Back-to-Back Enable (FB2B). Hardwired to 0. This bit controls whether or not the master can do fast back-to-back write. Since device 0 is strictly a target, this bit is not implemented. SERR Enable (SERRE).
Register Description 3.5.4 PCISTS—PCI Status Register (D0:F0) Address Offset: Default Value: Attribute: Size: 06–07h 0090h RO, R/WC 16 bits PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI interface. Bit 14 is read/write clear. All other bits are Read Only. Since MCH Device 0 does not physically reside on PCI_A many of the bits are not implemented. Note: Software must write a 1 to clear bits that are set.
Register Description 3.5.5 RID—Revision Identification Register (D0:F0) Address Offset: Default Value: Attribute: Size: 08h see table below RO 8 bits This register contains the revision number of the MCH Device 0. Bits 7:0 3.5.6 Default, Access Description 00h, Revision Identification Number (RID). This is an 8-bit value that indicates the revision identification number for the MCH Device 0.
Register Description 3.5.8 MLT—Master Latency Timer Register (D0:F0) Address Offset: Default Value: Attribute: Size: 0Dh 00h RO 8 bits Device 0 in the MCH is not a PCI master; therefore, this register is not implemented. Bits Default, Access 7:0 3.5.9 Reserved HDR—Header Type Register (D0:F0) Address Offset: Default Value: Attribute: Size: Bits 7:0 Default, Access 00h or 80, RO 50 Description 0Eh 00h or 80h RO 8 bits Description PCI Header (HDR).
Register Description 3.5.10 APBASE—Aperture Base Configuration Register (D0:F0) Address Offset: Default Value: Attribute: Size: 10–13h 0000 0008h RO, RW 32 bits The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics Aperture. The standard PCI Configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to 0 or behave as hardwired to 0).
Register Description 3.5.11 SVID—Subsystem Vendor Identification Register (D0:F0) Address Offset: Default Value: Attribute: Size: 2C–2Dh 0000h R/WO 16 bits This value is used to identify the vendor of the subsystem. Bits 15:0 3.5.12 Default, Access 0000h R/WO Description Subsystem Vendor ID (SUBVID). This field should be programmed during boot-up to indicate the vendor of the system board. After it has been written once, it becomes read only.
Register Description 3.5.14 CAPID—Product Specific Capability Identifier Register (D0:F0) Address Offset: Default Value: Attribute: Size: 40–43h 0104 A009h RO 32 bits The fields in this register contain product specific capabilities. The CAPPTR register provides the offset that points to this register. Set by BIOS. Bits Default, Access 31:28 27:24 23:16 15:8 7:0 Description Reserved 0001b RO 04h RO A0h RO 09h RO CAPID Version.
Register Description 3.5.15 MCHCFG—MCH Configuration Register (D0:F0) Address Offset: Default Value: Attribute: Size: Bits Default, Access 15 14:13 50–51h 0004h RO, R/W 16 bits Description Reserved 00b Number of Stop Grant Cycles (NSG). This field contains the number of Stop Grant transactions expected on the SB bus before a Stop Grant Acknowledge packet is sent to the Intel® ICH4.
Register Description Bits Default, Access Description Throttled-Write Occurred. 4 0b R/W 0 = This bit is cleared by writing a 0 to it. 1 = This bit is set when a write is throttled. This bit is set when the maximum allowed number of writes has been reached during a time-slice and there is at least one more write to be done. Throttled-Read Occurred. 3 0b R/W 1b RO 2 loaded from HA7# on RESET# 1:0 Intel® E7505 Chipset MCH Datasheet 0 = This bit is cleared by writing a 0 to it.
Register Description 3.5.16 PAM[0:6]—Programmable Attribute Map Registers (D0:F0) Address Offset: Default Value: Access: Size: 59–5Fh (PAM0–PAM6) 00h R/W 8 bits each The MCH allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers support these features. However, not all seven of these registers are identical.
Register Description Figure 3-1.
Register Description 3.5.17 DRB—DRAM Row Boundary Register (D0:F0) Address Offset: Default Value: Attribute: Size: 60–67h (DRB[0:7]) 00h RO 8 bits x 8 registers The DRAM Row Boundary registers defines the upper boundary address of each DRAM row with a granularity of 64 MB. Each row has its own single-byte DRB register. For example, a value of 1 in DRB0 indicates that 64 MB of DRAM has been populated in the first row. In this mode a row spans across both DIMMs.
Register Description DRB0 = Total memory in row0 (in 64-MB increments) DRB1 = Total memory in row0 + row1 (in 64-MB increments) ... DRB7 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 + row6 + row7 (in 64-MB increments) The row referred to by this register is defined by the DIMM chip select used. Double-sided DIMMs use both Row0 and Row1 (for CS0# and CS1#, even though there is one physical slot for the row.
Register Description 3.5.18 DRA—DRAM Row Attribute Register (D0:F0) Address Offset: Default Value: Attribute: Size: 70–73h 00h RO, R/W 8 bits x 4 registers The DRAM Row Attribute register defines the page sizes to be used for each row of memory. Each nibble of information in the DRA registers describes the page size of a row. For this register, a row is defined by the chip select used by the DIMM; thus, a double-sided DIMM has both an even and an odd entry.
Register Description 3.5.19 DRT—DRAM Timing Register (D0:F0) Address Offset: Default Value: Attribute: Size: 78–7Bh 0000 0010h RO, R/W 32 bits This register controls the timing of the DRAM Controller. Bits Default, Access 31:30 29 Description Reserved 0b R/W Back To Back Write-Read Turn Around. This field determines the minimum number of CMDCLK (command clocks, at 100 MHz) between Write-Read commands. It applies to WR-RD pairs to different rows.
Register Description Bits Default, Access Description Read Delay (tRD). This tRD value represents the time elapsed from the internal DCLK rising (for which command is sent) until HCLK rising for which initial SB data is driven (and the data can be read from the DDR receive FIFO).
Register Description Bits Default, Access Description CAS# Latency (tCL). The number of clocks between the rising edge used by DRAM to sample the Read Command and the rising edge that is used by the DRAM to drive read data. 5:4 01b 00 = 2.5 R/W 01 = 2 10 = Reserved 11 = Reserved 3 0b R/W Write RAS# to CAS# Delay (tRCD). This bit controls the number of clocks inserted between a row activate command and a write command to that row. 0 = 3 DRAM Clocks 1 = 2 DRAM Clocks READ RAS# to CAS# Delay (tRCD).
Register Description 3.5.20 DRC—DRAM Controller Mode Register (D0:F0) Address Offset: Default Value: Attribute: Size: Bits 31:30 29 7C–7Fh 0044_0009h RO, R/W 32 bits Default, Access 00b Description RO Revision Number (REV). This field reflects the revision number of the format used for SDR/DDR register definition. 0b Initialization Complete (IC). This bit is used for communication of software state between the memory controller and the BIOS.
Register Description Bits Default, Access Description Mode Select (SMS). These bits select the special operational mode of the DRAM interface. The special modes are intended for initialization at power up. When this field is first set to a non-zero value, the DRBs must be set to properly indicate which ranks are populated, since this information is latched shortly after a non-zero value is first written. DRBs can be changed later to adjust the rank addresses.
Register Description 3.5.21 REROTC—Receive Enable Reference Output Timing Control Register (D0:F0) Address Offset: Default Value: Attribute: Size: Bits 15 80–81h 0000h R/W 16 bits Default, Access 0b R/W Description Increase Read/Write Turnaround Margin. Total turnaround margin is controlled by this field in addition to the back-to-back read write turnaround control (bit 28) of the DRAM Timing Register. It is expected that extra margin will be required for 266 MHz DDR operation with CAS Latency of 2.
Register Description 3.5.23 DDR_CNTL—DDR Memory Control Register (D0:F0) Address Offset: Default Value: Attribute: Size: Bits 7 8Eh 00xx 0000b RO, R/W 8 bits Default, Access 0b R/W Description DDR Refresh Frequency. This bit is set by the BIOS to the DDR refresh frequency. It is used by the refresh timer to set the refresh period properly according to the number of clocks per microsecond. This is an indicator bit to the DDR logic only. It does not change the DDR frequency.
Register Description 3.5.24 SMRAM—System Management RAM Control Register (D0:F0) Address Offset: Default Value: Attribute: Size: 9Dh 02h RO, R/W 8 bits The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the Lock bit is set. Bits Default, Access 7 6 5 Description Reserved 0b R/W 0b R/W SMM Space Open (D_OPEN).
Register Description 3.5.25 ESMRAMC—Extended System Management RAM Control Register (D0:F0) Address Offset: Default Value: Attribute: Size: 9Eh 38h RO, R/W/L, R/WC 8 bits The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MB. Bits Default, Access Description Enable High SMRAM (H_SMRAME). This bit controls the SMM memory space location (i.e.
Register Description 3.5.26 ACAPID—AGP Capability Identifier Register (D0:F0) Address Offset: Default Value: Attribute: Size: A0–A3h 0030 0002h RO 32 bits This register provides the standard identifier for AGP capability. Read by drivers. Bits Default, Access 31:24 23:20 19:16 15:8 7:0 3.5.27 Description Reserved 3h RO 0h RO 00h RO 02h RO Major AGP Revision Number (MAJREV). These bits provide a major revision number of AGP specification to which this version of MCH conforms.
Register Description Bits 5 4 3 Default, Access 0b RO 1b Description Greater Than Four Gigabyte Support (GT4GIG). Hardwired to 0. The MCH does not support addresses greater than 4 GB. RO Fast Write Support (FW). Hardwired to a 1. The MCH supports Fast Writes from the processor to the AGP master. It is xb AGP 3.0 Signaling Mode. This bit is set by the hardware on reset based on the AGP 8x detection via the VREF Comparator. RO 0 = AGP 2.0 signaling mode (1.5 V). 1 = Graphics card is AGP 8x mode.
Register Description 3.5.28 AGPCMD—AGP Command Register (D0:F0) Address Offset: Default Value: Attribute: Size: A8–ABh 0000 0000h R/W 32 bits This register provides control of the AGP operational parameters. Set by drivers. Bits Default, Access 31:13 12:10 Description Reserved 000b RO Programmed Calibration Period (PCAL_Cycle). 000 = 4 ms Side Band Addressing Enable (SBAEN). 9 0b R/W 0 = Disable. 1 = Enable. In AGP 3.
Register Description 3.5.29 AGPCTRL—AGP Control Register (D0:F0) Address Offset: Default Value: Attribute: Size: B0–B3h 0000 0000h RO, R/W 32 bits This register provides for additional control of the AGP interface. Set by drivers Bits Default, Access 31:8 Description Reserved GTLB Enable (GTLBEN). 0 = Disable. The GTLB is flushed by clearing the valid bits associated with each entry. In this mode of operation all accesses that require translation bypass the GTLB.
Register Description 3.5.30 APSIZE—Aperture Size Register (D0:F0) Address Offset: Default Value: Attribute: Size: B4h 00h RO, R/W 8 bits This register determines the effective size of the Graphics Aperture used for a particular MCH configuration. This register can be updated by the MCH-specific BIOS configuration sequence before the PCI standard bus enumeration sequence takes place. If the register is not updated, the default value will select an aperture of maximum size (i.e., 256 MB).
Register Description 3.5.31 ATTBASE—Aperture Translation Table Register (D0:F0) Address Offset: Default Value: Attribute: Size: B8–BBh 0000 0000h R/W 32 bits This register provides the starting address of the Graphics Aperture Translation Table (GART) Base located in the main memory.
Register Description 3.5.33 LPTT—AGP Low Priority Transaction Time Register (D0:F0) Address Offset: Default Value: Attribute: Size: BDh 00h R/W 8 bits LPTT is an 8-bit register similar in function to AMTT. This register is used to control the minimum tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or SB mechanisms.
Register Description 3.5.34 TOLM—Top of Low Memory Register (D0:F0) Address Offset: Default Value: Attribute: Size: C4–C5h 0800h R/W 16 bits This register contains the maximum address below 4 GB that should be treated as a memory access, and is defined on a 128-MB boundary. Usually, it will sit below the areas configured for hub interface and PCI memory and the graphics aperture. Note that the memory address found in DRB7 reflects the top of total memory.
Register Description 3.5.36 REMAPLIMIT—Remap Limit Address Register (D0:F0) Address Offset: Default Value: Attribute: Size: Bits Default, Access 15:10 9:0 C8–C9h 0000h RO, R/W 16 bits Description Reserved 00h R/W Remap Limit Address 35:26. The value in this register defines the upper boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A25:0 of the Remap Limit Address are assumed to be Fhs.
Register Description 3.6 Chipset Host RAS Controller Registers (Device 0, Function 1) The Chipset Host RAS Controller Error Reporting registers are in Device 0 (D0), Function 1 (F1). Table 3-4 provides the register address map for this device, function. Warning: Address locations that are not listed the table are considered reserved register locations. Writes to “Reserved” registers may cause system failure. Reads to “Reserved” registers may return a nonzero value. Table 3-4.
Register Description 3.6.1 VID—Vendor Identification Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 00–01h 8086h No RO 16 bits The VID register contains the vendor identification number. This 16-bit register combined with the Device Identification register uniquely identify any PCI device. Bits 15:0 3.6.2 Default, Access 8086h RO Description Vendor Identification (VID). This register field contains the PCI standard identification for Intel, 8086h.
Register Description 3.6.3 PCICMD—PCI Command Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 04–05h 0000h No RO, R/W 16 bits Since MCH Device 0 does not physically reside on PCI_A many of the bits are not implemented. Bits Default, Access 15:9 Description Reserved SERR Enable (SERRE). This bit is a global enable bit for Device 0 SERR messaging. The MCH does not have an SERR signal.
Register Description 3.6.5 RID—Revision Identification Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 08h see table below No RO 8 bits This register contains the revision number of the MCH Device 0. Bits 7:0 Default, Access Description 00h Revision Identification Number (RID). This is an 8-bit value that indicates the revision identification number for the MCH Device 0. This number is always the same as the RID for function 0. RO 03h = B-0 Stepping. 3.6.
Register Description 3.6.8 MLT—Master Latency Timer Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 0Dh 00h No RO 8 bits Device 0 in the MCH is not a PCI master; therefore, this register is not implemented. Bits Default, Access 7:0 3.6.9 Description Reserved HDR—Header Type Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 3.6.10 0Eh 01h No RO 8 bits Bits Default, Access Description 7:0 01h RO PCI Header (HDR).
Register Description 3.6.12 FERR_GLOBAL—Global First Error Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 40–43h 0000 0000h Yes RO, R/WC 32 bits This register is used to report various error conditions. An SERR is generated on a 0-to-1 transition of any of these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is enabled and generated. This register stores the FIRST global error.
Register Description 3.6.13 NERR_GLOBAL—Global Next Error Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 44–47h 0000 0000h Yes RO, R/WC 32 bits The FIRST global error will be stored in FERR_GLOBAL. This register stores all future global errors. Multiple bits in this register may be set. Note: To prevent the same error from being logged twice in FERR_GLOBAL and NERR_GLOBAL, a FERR_GLOBAL bit being set blocks the respective bit in the NERR_GLOBAL Register from being set.
Register Description 3.6.14 HIA_FERR—HI_A First Error Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 50h 00h Yes RO, R/WC 8 bits This register stores the first error related to the HI_A interface. Only 1 error bit will be set in this register. Any future errors (NEXT errors) will be set in the HIA_NERR Register. No further error bits in this register will be set until the existing error bit is cleared. Note: Software must write a 1 to clear bits that are set.
Register Description 3.6.15 HIA_NERR—HI_A Next Error Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 52h 00h Yes RO, R/WC 8 bits The first HI_A error will be stored in the HIA_FERR Register. This register stores all future HI_A errors. Multiple bits in this register may be set. Note: Software must write a 1 to clear bits that are set. Bits Default, Access 7 Reserved HI_A Target Abort. 0b 6 R/WC 5 R/WC 3:1 HI_A Data Parity Error Detected.
Register Description 3.6.17 SMICMD_HIA—SMI Command Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 5Ah 00h No RO, R/W 8 bits This register determine whether SMI will be generated when the associated flag is set in either the HIA_FERR or HIA_NERR Register. When an error flag is set in the HIA_FERR or HIA_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Register Description 3.6.19 SB_FERR—System Bus First Error Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 60h 00h Yes R/WC 8 bits This register stores the first error related to the system bus interface. Any future errors (next errors) will be set in the SB_NERR Register. No further error bits in this register will be set until the existing error bit is cleared. Note: Software must write a 1 to clear bits that are set.
Register Description 3.6.20 SB_NERR—System Bus Next Error Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 62h 00h Yes R/WC 8 bits The first system bus error will be stored in the SB_FERR Register. This register stores all future system bus errors. Multiple bits in this register may be set. Note: Software must write a 1 to clear bits that are set. Bits 7 Default, Access 0b R/WC Description System Bus BINIT# Detected. 0 = No system bus BINIT# detected.
Register Description 3.6.21 SCICMD_SB—SCI Command Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 68h 00h No R/W 8 bits This register determine whether SCI will be generated when the associated flag is set in either the SB_FERR or SB_NERR Register. When an error flag is set in the SB_FERR or SB_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Register Description 3.6.22 SMICMD_SB—SMI Command Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 6Ah 00h No R/W 8 bits This register determines whether SMI will be generated when the associated flag is set in either the SB_FERR or SB_NERR Register. When an error flag is set in the SB_FERR or SB_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Register Description 3.6.23 SERRCMD_SB—SERR Command Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 6Ch 00h No R/W 8 bits This register determines whether SERR will be generated when the associated flag is set in either the SB_FERR or SB_NERR Register. When an error flag is set in the SB_FERR or SB_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Register Description 3.6.24 DRAM_FERR—DRAM First Error Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 80h 00h Yes RO, R/WC 8 bits This register stores the FIRST ECC error on the DRAM interface. Only 1 error bit will be set in this register. Any future errors (NEXT errors) will be set in the DRAM_NERR Register. No further error bits in this register will be set until the existing error bit is cleared. Note: Software must write a 1 to clear bits that are set.
Register Description 3.6.26 SCICMD_DRAM —SCI Command Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 88h 00h No RO, R/W 8 bits This register determines whether SCI will be generated when the associated flag is set in the DRAM_FERR or DRAM_NERR Register. When an error flag is set in the DRAM_FERR or DRAM_NERR Registers, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Register Description 3.6.28 SERRCMD_DRAM—SEER Command Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: 8Ch 00h No RO, R/W 8 bits This register determines whether SERR will be generated when the associated flag is set in the DRAM_FERR or DRAM_NERR Register. When an error flag is set in the DRAM_FERR or DRAM_NERR Registers, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Register Description 3.6.30 DRAM_UELOG_ADD—DRAM First Uncorrectable Memory Error Address Register (D0:F1) Address Offset: Default Value: Sticky Attribute: Size: B0–B3h 0000 0000h Yes RO 32 bits This register contains the address of the first uncorrectable memory error. When a bit in either the DRAM_FERR or DRAM_NERR Register is set, this register is locked. This register is only valid if a bit in either the DRAM_FERR or DRAM_NERR Register is set.
Register Description 3.7 PCI-to-AGP Bridge Registers (Device 1, Function 0) The PCI-to-AGP registers are in Device 1 (D1), Function 0 (F0). Table 3-5 provides the register address map for this device, function. Warning: Address locations that are not listed the table are considered reserved register locations. Writes to “Reserved” registers may cause system failure. Reads to “Reserved” registers may return a nonzero value. Table 3-5.
Register Description 3.7.1 VID1—Vendor Identification Register (D1:F0) Address Offset: Default Value: Attribute: Size: 00–01h 8086h RO 16 bits The VID register contains the vendor identification number. This 16-bit register combined with the Device Identification register uniquely identify any PCI device. Bits 15:0 3.7.2 Default, Access 8086h RO Description Vendor Identification Device 1 (VID1). This register field contains the PCI standard identification for Intel, 8086h.
Register Description 3.7.3 PCICMD1—PCI Command Register (D1:F0) Address Offset: Default Value: Attribute: Size: Bits Default, Access 15:10 9 8 7 6 3 Description Reserved 0b RO 0b R/W 0b RO 0b RO 5 4 04–05h 0000h RO, R/W 16 bits Fast Back-to-Back Enable (FB2B). Hardwired to 0. Not Applicable. SERR Message Enable (SERRE). This bit is a global enable bit for Device 1 SERR messaging. The MCH communicates the SERR# condition by sending an SERR message to the Intel® ICH4.
Register Description 3.7.4 PCISTS1—PCI Status Register (D1:F0) Address Offset: Default Value: Attribute: Size: 06–07h 00A0h/00B0h RO, R/WC 16 bits PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with primary side of the virtual PCI-to-PCI bridge embedded within the MCH. Bits 15 Default, Access 0b RO Description Detected Parity Error (DPE). Hardwired to 0. Parity is not supported on the primary side of this device. Signaled System Error (SSE).
Register Description 3.7.5 RID1—Revision Identification Register (D1:F0) Address Offset: Default Value: Attribute: Size: 08h see table below RO 8 bits This register contains the revision number of the MCH device 1. These bits are read only and writes to this register have no effect. Bits 7:0 Default, Access Description 00h Revision Identification Number (RID). This is an 8-bit value that indicates the revision identification number for the MCH device 1. It is always the same as the value in RID.
Register Description 3.7.8 MLT1—Master Latency Timer (Scratch Pad) Register (D1:F0) Address Offset: Default Value: Attribute: Size: 0Dh 00h R/W, RO 8 bits This functionality is not applicable. It is described here since these bits should be implemented as a read/write to prevent standard PCI-to-PCI bridge configuration software from getting “confused.” Bits 7:3 Default, Access 00000b R/W 2:0 3.7.9 Description Scratch pad MLT (NA7.3).
Register Description 3.7.10 APBASELO—AGP Aperture Base Address Register (D1:F0) Address Offset: Default Value: Attribute: Size: 10–13h 0000 0008h R/W, RO 32 bits Note that the intention is that the APSIZE register force individual bits to Read Only as 0, although the E7505 (and other chips) implementation only causes them to be Read Only, and does not force them to 0.
Register Description 3.7.11 PBUSN1—Primary Bus Number Register (D1:F0) Address Offset: Default Value: Attribute: Size: 18h 00h RO 8 bits This register identifies that virtual PCI-to-PCI bridge is connected to bus #0. Bits 7:0 3.7.12 Default, Access 00h RO Description Primary Bus Number (BUSN). Configuration software typically programs this field with the number of the bus on the primary side of the bridge.
Register Description 3.7.14 SMLT1—Secondary Bus Master Latency Timer Register (D1:F0) Address Offset: Default Value: Attribute: Size: 1Bh 00h R/W, RO 8 bits This register controls the bus tenure of the MCH on AGP/PCI the same way device 0 MLT controls the access to the PCI_A bus. Bits 7:3 Default, Access 00000b R/W 2:0 3.7.15 Description Secondary MLT Counter Value (MLT).
Register Description 3.7.16 IOLIMIT1—I/O Limit Address Register (D1:F0) Address Offset: Default Value: Attribute: Size: 1Dh 00h R/W, RO 8 bits This register controls the processor-to-AGP I/O access routing based on the following formula: IO_BASE ≤ address ≤ IO_LIMIT1 Only the upper 4 bits are programmable. For the purpose of address decode, address bits A11:0 are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KB aligned address block.
Register Description 3.7.17 SSTS1—Secondary Status Register (D1:F0) Address Offset: Default Value: Attribute: Size: 1E–1Fh 02A0h R/W 16 bits SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with the secondary side (i.e., AGP side) of the virtual PCI-to-PCI bridge in the MCH. Note: Software writes a 1 to clear bits that are set.
Register Description 3.7.18 MBASE1—Memory Base Address Register (D1:F0) Address Offset: Default Value: Attribute: Size: 20–21h FFF0h R/W, RO 16 bits This register controls the processor-to-AGP non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20 of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read.
Register Description 3.7.19 MLIMIT1—Memory Limit Address Register (D1:F0) Address Offset: Default Value: Attribute: Size: 22–23h 0000h R/W, RO 16 bits This register controls the processor-to-AGP non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20 of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read.
Register Description 3.7.20 PMBASE1—Prefetchable Memory Base Address Register (D1:F0) Address Offset: Default Value: Attribute: Size: 24–25h FFF0h R/W, RO 16 bits This register controls the processor-to-AGP prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20 of the 32-bit address.
Register Description 3.7.21 PMLIMIT1—Prefetchable Memory Limit Address Register (D1:F0) Address Offset: Default Value: Attribute: Size: 26–27h 0000h R/W, RO 16 bits This register controls the processor-to-AGP prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20 of the 32-bit address.
Register Description 3.7.23 BCTRL1—Bridge Control Register (D1:F0) Address Offset: Default Value: Attribute: Size: 3Eh 00h R/W, RO 8 bits This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI bridges. The BCTRL provides additional control for the secondary interface (i.e., AGP) as well as some bits that affect the overall behavior of the virtual PCI-to-PCI bridge embedded within MCH (e.g., VGA compatible address ranges mapping).
Register Description 3.7.24 ERRCMD1—Error Command Register (D1:F0) Address Offset: Default Value: Attribute: Size: 40h 00h R/W 8 bits Set by drivers. Bits Default, Access 7:4 Description Reserved SERR on AGP Access Outside of Graphics Aperture (OOGF). 3 0b R/W 0 = Disable. Reporting of this condition is disabled. 1 = Enable. MCH generates a SERR special cycle over HI_A when an AGP access occurs to an address outside of the graphics aperture. SERR on Invalid AGP Access (IAAF).
Register Description 3.7.25 ERRSTS1—Error Status Register (D1:F0) Address Offset: Default Value: Attribute: Size: 42h 00h R/WC 8 bits Set by drivers. Note: Software writes a 1 to clear bits that are set. Bits Default, Access 7:4 Description Reserved AGP Access Outside of Graphics Aperture Flag (OOGF). 3 2 1 0b R/WC 0b R/WC 0b R/WC 0 3.7.26 1 = AGP access occurred to an address outside of the graphics aperture range. This bit will be set for accesses outside of the aperture for AGP 2.
Register Description 3.7.27 AGPSTAT1—AGP Status Register (D1:F0) Address Offset: Default Value: Attribute: Size: 64–67h see table below RO 32 bits This register reports AGP device capability/status. Read by drivers. Bits 31:24 Default, Access 1Fh RO 23:16 15:13 12:10 Description Request Queue (RQ). Hardwired to 1Fh. This field contains the maximum number of AGP command requests the MCH is configured to manage. 1Fh = 32 outstanding AGP command requests maximum can be handled by the MCH.
Register Description 3.7.28 AGPCMD—AGP Command Register (D1:F0) Address Offset: Default Value: Attribute: Size: 68–6Bh 0000 0000h RO, R/W 32 bits This register provides control of the AGP operational parameters. Set by drivers. Bits Default, Access 31:13 12:10 Description Reserved 000b R/W Programmed Calibration Period (PCAL_Cycle). These bits are programmed with the period for core-logic initiated bus cycles for calibrating the I/O buffers for both master and target.
Register Description Bits Default, Access Description Fast Write Enable (FWEN). 4 0b R/W 0 = Disable. When this bit it is 0 or when the data rate bits are set to 1x mode, the Memory Write transactions from the MCH to the AGP master use standard PCI protocol. 1 = Enable. MCH uses the Fast Write protocol for memory write transactions from the MCH to the AGP master. Fast Writes occur at the data transfer rate selected by the data rate bits (2:0) in this register.
Register Description 3.7.29 AGPCTRL1—AGP Control Register (D1:F0) Address Offset: Default Value: Attribute: Size: 70–73h 0000 0000h RO, R/W 32 bits This register provides for additional control of the AGP interface. Set by drivers. Bits Default, Access 31:10 Description Reserved Calibration Disable. 0 = Enable. 9 0b 8 1 = Disable. Calibration cycle operation is disabled by the core logic. Note that calibration cycle should be automatically disabled by core-logic when not in AGP 3.
Register Description 3.7.30 APSIZE1—AGP Aperture Size Register (D1:F0) Address Offset: Default Value: Attribute: Size: 74–75h 0000h R/W 16 bits This register determines the effective size of the Graphics Aperture used for a particular MCH configuration. This register can be updated by the MCH-specific BIOS configuration sequence before the PCI standard bus enumeration sequence takes place. If the register is not updated then a default value will select an aperture of maximum size (i.e., 256 MB).
Register Description 3.7.31 ATTBASE1—AGP GART Pointer Register (D1:F0) Address Offset: Default Value: Attribute: Size: 78–7Bh 0000 0000h R/W, RO 32 bits This register determines the starting address of the GART table. It must be on a 4-KB boundary, regardless of its size. The size of the table is determined by the APSIZE1 register as shown in the table below. Set by drivers. Bits 31:12 11:0 Default, Access 00000h R/W Description Graphics Aperture Remapping Table Starting Address (GART).
Register Description 3.8 Hub Interface_B PCI-to-PCI Bridge Registers (Device 2, Function 0) The Hub Interface_B (HI_B) registers are in Device 2 (D2), Function 0 (F0). Table 3-6 provides the register address map for this device, function. Warning: Address locations that are not listed the table are considered reserved register locations. Writes to “Reserved” registers may cause system failure. Reads to “Reserved” registers may return a nonzero value. Table 3-6.
Register Description 3.8.1 VID2—Vendor Identification Register (D2:F0) Address Offset: Default Value: Attribute: Size: 00–01h 8086h RO 16 bits The VID register contains the vendor identification number. This 16-bit register combined with the Device Identification register uniquely identify any PCI device. Bits 15:0 3.8.2 Default, Access 8086h RO Description Vendor Identification Device 2 (VID2). This register field contains the PCI standard identification for Intel, 8086h.
Register Description 3.8.3 PCICMD2—PCI Command Register (D2:F0) Address Offset: Default Value: Attribute: Size: 04–05h 0000h RO, R/W 16 bits Many of these bits are not applicable since the primary side of this device is not an actual PCI bus. Bits Default, Access 15:10 9 8 Description Reserved 0b RO 0b R/W Fast Back-to-Back Enable (FB2B). Hardwired to 0. Not Applicable. SERR Message Enable (SERRE). This bit is a global enable bit for Device 2 SERR messaging. The MCH does not have an SERR# signal.
Register Description 3.8.4 PCISTS2—PCI Status Register (D2:F0) Address Offset: Default Value: Attribute: Size: 06–07h 00A0h RO, R/WC 16 bits PCISTS2 is a 16-bit status register that reports the occurrence of error conditions associated with the primary side of the virtual PCI-to-PCI bridge embedded within the MCH. Note: Software writes a 1 to clear set bits. Bits 15 Default, Access 0b RO Description Detected Parity Error (DPE). Hardwired to 0.
Register Description 3.8.5 RID2—Revision Identification Register (D2:F0) Address Offset: Default Value: Attribute: Size: 08h see table below RO 8 bits This register contains the revision number of the MCH device 2. Bits 7:0 3.8.6 Default, Access Description 00h Revision Identification Number (RID). This is an 8-bit value that indicates the revision identification number for the MCH device 2. It is always the same as the value in RID.
Register Description 3.8.8 MLT2—Master Latency Timer (Scratch Pad) Register (D2:F0) Address Offset: Default Value: Attribute: Size: 0Dh 00h R/W, RO 8 bits This functionality is not applicable. It is described here since these bits should be implemented as a read/write to prevent standard PCI-to-PCI bridge configuration software from getting “confused.” Bits 7:3 Default, Access Description Scratch pad MLT (NA7.3).
Register Description 3.8.11 SBUSN2—Secondary Bus Number Register (D2:F0) Address Offset: Default Value: Attribute: Size: 19h 00h R/W 8 bits This register identifies the bus number assigned to the second bus side of the virtual PCI-to-PCI bridge (the HI_B connection). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to a second bridge device connected to HI_B. Bits 7:0 3.8.12 Default, Access 00h R/W Description Secondary Bus Number (BUSN).
Register Description 3.8.13 IOBASE2—I/O Base Address Register (D2:F0) Address Offset: Default Value: Attribute: Size: 1Ch F0h R/W, RO 8 bits This register control the processor-to-HI_B I/O access routing based on the following formula: IO_BASE2 ≤ address ≤ IO_LIMIT2 Only the upper 4 bits are programmable. For the purpose of address decode, address bits A11:0 are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB boundary. Bits 7:4 Default, Access Fh R/W 3:0 3.
Register Description 3.8.15 SEC_STS2—Secondary Status Register (D2:F0) Address Offset: Default Value: Attribute: Size: 1E–1Fh 02A0h R/WC, RO 16 bits SSTS2 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., HI_B side) of the virtual PCI-to-PCI bridge in the MCH. Note: Software writes a 1 to clear bits that are set.
Register Description 3.8.16 MBASE2—Memory Base Address Register (D2:F0) Address Offset: Default Value: Attribute: Size: 20–21h FFF0h R/W, RO 16 bits This register controls the processor-to-HI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE2 ≤ address ≤ MEMORY_LIMIT2 The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20 of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read.
Register Description 3.8.18 PMBASE2—Prefetchable Memory Base Address Register (D2:F0) Address Offset: Default Value: Attribute: Size: 24–25h FFF0h R/W, RO 16 bits This register controls the processor-to-HI_B prefetchable memory accesses. The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20 of the 36-bit address. For the purpose of address decode, bits A19:0 are assumed to be 0.
Register Description 3.8.20 BCTRL2—Bridge Control Register (D2:F0) Address Offset: Default Value: Attribute: Size: 3Eh 00h RO, R/W 8 bits This register provides extensions to the PCICMD2 register that are specific to PCI-to-PCI bridges. The BCTRL provides additional control for the secondary interface (i.e., HI_B) as well as some bits that affect the overall behavior of the virtual PCI-to-PCI bridge in the MCH (e.g., VGA compatible address range mapping).
Register Description 3.9 Hub Interface_B PCI-to-PCI Bridge Error Reporting Registers (Device 2, Function 1) The Hub Interface_B (HI_B) error reporting registers are in Device 2 (D2), Function 1 (F1). Table 3-7 provides the register address map for this device, function. Warning: Address locations that are not listed the table are considered reserved register locations. Writes to “Reserved” registers may cause system failure. Reads to “Reserved” registers may return a nonzero value. Table 3-7.
Register Description 3.9.1 VID—Vendor Identification Register (D2:F1) Address Offset: Default Value: Sticky Attribute: Size: 00–01h 8086h No RO 16 bits The VID register contains the vendor identification number. This 16-bit register combined with the Device Identification register uniquely identify any PCI device. Bits 15:0 3.9.2 Default, Access 8086h RO Description Vendor Identification (VID). This register field contains the PCI standard identification for Intel, 8086h.
Register Description 3.9.3 PCICMD—PCI Command Register (D2:F1) Address Offset: Default Value: Sticky Attribute: Size: Bits Default, Access 15:9 8 Description Reserved 0b R/W 7:0 3.9.4 04–05h 0000h No RO, R/W 16 bits SERR Enable (SERRE). This bit is a global enable bit for Device 2 SERR messaging. The MCH does not have an SERR# signal. The MCH communicates the SERR condition by sending an SERR message over HI_A to the Intel® ICH4. 0 = Disable.
Register Description 3.9.5 RID—Revision Identification Register (D2:F1) Address Offset: Default Value: Sticky Attribute: Size: 08h see table below No RO 8 bits This register contains the revision number of the MCH Device 0. These bits are read only and writes to this register have no effect. Bits 7:0 Default, Access Description 00h Revision Identification Number (RID). This is an 8-bit value that indicates the revision identification number for the MCH Device 0.
Register Description 3.9.8 HDR—Header Type Register (D2:F1) Address Offset: Default Value: Sticky Attribute: Size: Bits 7:0 3.9.9 0Eh 00h No RO 8 bits Default, Access 00h RO Description PCI Header (HDR). Reads and writes to this location have no effect. SVID—Subsystem Vendor Identification Register (D2:F1) Address Offset: Default Value: Sticky Attribute: Size: 2C–2Dh 0000h No R/WO 16 bits This value is used to identify the vendor of the subsystem. Bits 15:0 3.9.
Register Description 3.9.11 HIB_FERR—HI_B First Error Register (D2:F1) Address Offset: Default Value: Sticky Attribute: Size: 80h 00h Yes R/WC 8 bits This register store the FIRST error related to the HI_B interface. Only one error bit will be set in this register. Any future errors (NEXT Errors) will be set in the HIB_NERR register. No further error bits in this register will be set until the existing error bit is cleared. Note: Software must write a 1 to clear bits that are set.
Register Description 3.9.12 HIB_NERR—HI_B Next Error Register (D2:F1) Address Offset: Default Value: Sticky Attribute: Size: 82h 00h Yes R/WC 8 bits The FIRST error related to HI_B will be stored in the HIB_FERR Register. This register store all future errors related to the HI_B. Multiple bits in this register may be set. Note: Software must write a 1 to clear bits that are set. Bits Default, Access 7 6 Description Reserved 0b R/WC MCH Received SERR from HI_B. 0 = No SERR from HI_B received.
Register Description 3.9.13 SERRCMD2—SERR Command Register (D2:F1) Address Offset: Default Value: Sticky Attribute: Size: A0h 00h No RO, R/W 8 bits This register determines whether SERR will be generated when the associated flag is set in FERR or NERR. When an error flag is set in the FERR or NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Register Description 3.9.14 SMICMD2—SMI Command Register (D2:F1) Address Offset: Default Value: Sticky Attribute: Size: A2h 00h No RO, R/W 8 bits This register determines whether SMI will be generated when the associated flag is set in FERR or NERR. When an error flag is set in the FERR or NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Register Description 3.9.15 SCICMD2—SCI Command Register (D2:F1) Address Offset: Default Value: Sticky Attribute: Size: A4h 00h No RO, R/W 8 bits This register determines whether SCI will be generated when the associated flag is set in the FERR or NERR Register. When an error flag is set in the FERR or NERR Register, it can generate an SERR, SMI, or SCI when enabled in the ERRCMD, SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
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System Address Map 4 System Address Map A system based on the E7505 chipset supports 16 GB–64 MB (see note) of host-addressable memory space and 64 KB + 3 of host-addressable I/O space. The I/O and memory spaces are divided by system configuration software into regions. The memory ranges are useful either as system memory or as specialized memory, while the I/O regions are used to control the operation of devices in the system. Note: 4.1 The maximum usable memory address decode is 15.
System Address Map These address ranges are always mapped to system memory, regardless of the system configuration. Memory may be allocated from the main memory segment (0_0100_0000h to TOLM) for use by System Management Mode (SMM) hardware and software. The top of main memory is defined by the Top of Low Memory (TOLM) register. Note that the address of the highest 64-MB (dual channel) quantity of valid memory in the system is placed into the DRB7 register (32 MB for single channel).
System Address Map Figure 4-3.
System Address Map 4.1.1 VGA and MDA Memory Spaces Video cards use these legacy address ranges to map a frame buffer or a character-based video buffer. The address ranges in this memory space are: • VGAA • MDA • VGAB 0_000A_0000h to 0_000A_FFFFh 0_000B_0000h to 0_000B_7FFFh 0_000B_8000h to 0_000B_FFFFh By default, accesses to these ranges are forwarded to HI_A.
System Address Map 4.1.
System Address Map 4.1.3 I/O APIC Memory Space The I/O APIC spaces are used to communicate with I/O APIC interrupt controllers that may be populated on HI_A through HI_B. Since it is difficult to relocate an interrupt controller using plugand-play software, fixed address decode regions have been allocated for them. The address ranges are: • I/OAPIC0 (HI_A) • I/OAPIC1 (HI_B) 0_FEC0_0000h to 0_FEC7_FFFFh 0_FEC8_0000h to 0_FEC8_0FFFh Processor accesses to the IOAPIC0 region are always sent to HI_A.
System Address Map 4.1.6.1 AGP DRAM Graphics Aperture The APBASE register follows the standard base address register template defined by the PCI 2.1 specification; however, the size of the range claimed by the APBASE register is programmed via the APSIZE register. System BIOS programs this register before PCI Enumeration to be 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB or 256 MB.
System Address Map 4.3 SMM Space 4.3.1 System Management Mode (SMM) Memory Range The E7505 chipset supports the use of main memory as System Management RAM (SMM RAM), which enables the use of System Management Mode. The MCH supports three SMM options: • Compatible SMRAM (C_SMRAM) • High Segment (HSEG) • Top of Memory Segment (TSEG). System Management RAM space provides a memory area that is available for the SMI handlers and code and data storage.
System Address Map 4.3.3 High SMM Memory Space The HIGHSMM space (0_FEDA_0000h to 0_FEDB_FFFFh) allows cacheable access to the compatible SMM space by remapping valid SMM accesses between 0_FEDA_0000h and 0_FEDB_FFFFh to accesses between 0_000A_0000h and 0_000B_FFFFh. The accesses are remapped when SMRAM space is enabled; an appropriate access is detected on the system bus, and when ESMRAMC.H_SMRAME allows access to high SMRAM space.
System Address Map 4.4 Memory Re-claim Background The following memory-mapped I/O devices are typically located below 4 GB: • • • • • • High BIOS HSEG XAPIC Local APIC System Bus Interrupts HI_B BAR In previous generation MCHs, the physical main memory overlapped by the logical address space allocated to these memory-mapped I/O devices was unusable. In workstation systems the memory allocated to memory-mapped I/O devices could easily exceed 1 GB.
Functional Description Functional Description 5 This chapter covers the MCH functional units including: System Bus, AGP, DRAM, SMBus, power management, MCH clocking, MCH system reset and power sequencing. 5.1 System Bus Overview 5.1.1 Source Synchronous Transfers The MCH is optimized for use with processors based on the Intel® NetBurst™ microarchitecture.
Functional Description 5.1.4 Dynamic Bus Inversion The MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data from the processor. DBI limits the number of data signals that are driven to a low voltage on each quad pumped data phase. This decreases the worst-case power consumption of the MCH. The DINV[3:0]# signals indicate if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase (see following table).
Functional Description The MCH supports re-directing lowest priority delivery mode interrupts to the processor which is executing the lowest priority task thread. The MCH re-directs interrupts based on the task priority status of each processor thread. The task priority of each processor thread is periodically downloaded to the MCH via the xTPR (Task Priority Register) special transaction. The MCH redirects hub interface and PCI originated interrupts as well as IPIs.
Functional Description 5.4 AGP 8x Interface The MCH supports AGP 8x with backwards compatibility to AGP 4x. The electrical signal levels supported by the MCH for the AGP 8x interface are 0.8 V levels for 8x, 4x (AGP 3.0) transfers. The MCH can also operate in 4x, 2x, and 1x (AGP 2.0) modes: these modes are only at 1.5 V signal levels. Note: The MCH does not support 3.3 V signal levels. The MCH has a 32-deep AGP request queue that is used for Asynchronous modes.
Functional Description 5.4.3 AGP 3.0 and AGP 2.0 Signaling Mode Differences Table 5-1. Key Differences Between AGP 3.0 and AGP 2.0 Signaling Modes AGP 3.0 Signaling Mode AGP 2.0 Signaling Mode Data Rate 8x or 4x 4x, 2x, or 1x Electricals 0.8 V swing, parallel termination 1.
Functional Description 5.4.4 AGP 3.0 Downshift (4x data rate) Mode AGP 3.0 supports both 8x and 4x data rates. By supporting the 4x data rate, a system has the capability of supporting a legacy AGP 4x graphic card (1.5 V signal levels). In addition, there may be instances where system-related deficiencies may cause an 8x graphic card to downshift to the 4x data rate. All of the AGP 3.0 protocols are used during 4x data rate transfers. Table 5-2. AGP 3.0 Downshift Mode Parameters AGP3.
Functional Description 5.4.5 AGP Target Operations As an initiator, the MCH does not initiate cycles using AGP enhanced protocols. The MCH supports AGP target interface to main memory only. The MCH supports interleaved AGP and PCI transactions. Table 5-3. AGP 3.0 and AGP 2.0 Support Command Types 5.4.6 GC/BE[3:0]# (GC#/BE[3:0]) Encoding AGP 3.0 Command AGP 2.
Functional Description 5.4.7 AGP Aperture and GART The MCH contains the AGP aperture and GART capabilities to allow address translation of AGP accesses. This capability is very similar to previous chipsets. The AGP aperture may be anywhere from 4 MB to 256 MB in size in binary increments The default is 256 MB. It is placed above the top of low memory by the PCI plug-and-play software. The GART address is always naturally aligned to its size, as is required by PCI plug-and-play.
Functional Description GC_DET# is grounded by the graphics card to indicate that it is an AGP 3.0-capable graphics controller and is floated by an AGP 2.0 graphics controller. An AGP 2.0-only motherboard ignores this signal. An AGP 3.0-capable motherboard uses this signal to select between a 0.35 V (AGP 3.0) or 0.75 V (AGP 2.0) VREF. This VREF is sent back to the graphics controller card. The graphic controller card can use the VREF level or the MB_DET# signal to determine the electrical mode.
Functional Description 5.4.12 Fast Writes The Fast Write (FW) transaction is from the core logic to the AGP master acting as a PCI target. This type of access is required to pass data/control directly to the AGP master instead of placing the data into main memory and then having the AGP master read the data. For 1x transactions, the protocol follows the PCI bus specification.
Functional Description 5.5 Main Memory Interface The memory interface supports a dual channel DDR system memory with registered or unbuffered SDRAM DIMMs. The MCH only supports DDR-SDRAM type of memory. The MCH does not support SDR SDRAM (PC-100/133) type of memory. Table 5-6 defines the some of the terms used in this section Table 5-6. DRAM Terminology Term Definition DDR Double Data Rate. This term describes the type of DRAMs that transfer two data items per clock on each pin.
Functional Description Table 5-6. DRAM Terminology (Continued) Term 5.5.1 Definition Page A page is a section of a DRAM bank that is opened by an activate command. Once opened, multiple locations (columns) of a page can be read or written without requiring a precharge and activate command. Row Address The row address is presented to the DRAMs during an Activate command and indicates which page to open within the specified bank (the bank number is also presented).
Functional Description 5.5.3 DRAM Technologies and Types Supported • • • • • 5.5.4 128-Mb, 256-Mb, 512-Mb, and 1-Gb technology DRAMs x4, x8 registered x8, x16 unbuffered (Double-sided x16 is not supported) 4 bank devices only Page sizes supported: 4 KB, 8 KB, 16 KB, 32 KB, and 64 KB. They are selectable per row pair. Memory Capacity The maximum memory capacity supported by the MCH is 16 GB–64 MB (see note below).
Functional Description 5.5.6 Intel® x4 SDDC Technology ECC The MCH supports Intel® x4 Single Device Data Correction (x4 SDDC) technology ECC. The ECC code spans 144 bits of data. ECC may be disabled by the System BIOS. No performance gain is achieved. The x4 SDDC technology ECC performs the following: • Corrects any number of errors contained in a 4-bit naturally aligned nibble. • Detects all errors contained entirely with two 4-bit naturally aligned nibbles.
Functional Description 5.6 System Manageability Bus 2.0 The MCH supports the following features: • Address Resolution Protocol (ARP) • Alert Standard Forum (ASF) • Packet Error Checking (PEC) SMBus Signaling The System Management Bus (SMBus) is a two-wire interface where the system can communicate with other devices. A system using SMBus passes messages to and from devices.
Functional Description 5.7.1 Processor States C0 (Full On) This is the only state that runs software. All clocks are running, STPCLK# is deasserted and the processor core is active. The processor can service snoops and maintain cache coherency in this state. C1 (Auto-Halt) The first level of power reduction occurs when the processor executes an Auto-Halt instruction. This stops the execution of the instruction stream and greatly reduces the processors power consumption.
Functional Description 5.7.3 Clock Control The clocks in the platform fall into three categories: • The first category consists of those clocks that turn on and off during normal operation (e.g., a serial port clock). • The second category consists of clocks that never turn off. Only the 32.768 kHz RTC clock falls into this category. • The third category consists of those clocks that must be active in normal operation but are actively controlled by the platform to manage power.
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Electrical Characteristics 6 Electrical Characteristics This chapter provides the absolute maximum ratings, thermal characteristics, and DC characteristics for the MCH1. NOTE: 6.1 1.) VCC is set at 1.2 V or 1.3V depending on the part. Please refer to the E7505 Chipset Memory Controller Hub Specification Update for more information Absolute Maximum Ratings Table 6-1 lists the MCH’s maximum environmental stress ratings.
Electrical Characteristics Table 6-2. DC Characteristics Functional Operating Range 174 Iagp 1.5 V AGP 0.6 A IVTT 1.525 V AGTL+ 2.1 A Idd_DDR 2.5 V Vdd DDR (2 channel) 6.
Electrical Characteristics 6.3 I/O Interface Signal Groupings The signal description includes the type of buffer used for the particular signal: • AGTL+ Open Drain AGTL+ interface signal. The MCH integrates AGTL+ termination resistors. • • • • CMOS 1.2 V CMOS buffers. SSTL-2 DDR Signaling Interface HI-2 Hub Interface buffer type AGP AGP Interface Buffer Type Table 6-3.
Electrical Characteristics Table 6-5. Signal Groups AGP Interface Signal Group Signal Type Signals Notes (k) AGP I/O GDEVSEL# (2.0), GDEVSEL (3.0), GAD[31:0], GC/BE[3:0]# (2.0), GC/BE[3:0] (3.0), GPAR, DBI_LO (3.0 only), AD_STB0 (2.0), AD_STBF0 (3.0), AD_STB0# (2.0), AD_STBS0 (3.0), AD_STB1 (2.0), AD_STBF1 (3.0), AD_STB1# (2.0), AD_STBS1 (3.0), PIPE# (2.0), DBI_HI (3.0), GIRDY# (2.0), GIRDY (3.0), GTRDY# (2.0), GTRDY (3.0), GSTOP# (2.0), GSTOP(3.0), PRCOMP_AGPx, GFRAME# (2.0), GFRAME (3.
Electrical Characteristics 6.4 DC Characteristics This section provides DC Characteristics at VCC1_2 = 1.2 V ± 5% and at VCC1_3 = 1.3 V ± 5% Table 6-9. Operating Condition Supply Voltage Symbol VTT Signal Group (f) Parameter Min Nom Max Unit Host AGTL+ Termination Voltage 1.15 1.525 V VCCDDR DDR Buffer Voltage 2.375 2.5 2.625 V VCCMCH MCH Core Voltage 1.14 1.2 1.26 V VCCAGP AGP Voltage 1.425 1.5 1.575 V GTLREF Host AGTL+ Reference Voltage Notes 0.
Electrical Characteristics Table 6-11. DDR Interface DC Characteristics Symbol Signal Group VIL (DC) (g), (i) DDR Input Low Voltage VIH (DC) (g), (i) DDR Input High Voltage VIL (AC) (g), (i) DDR Input Low Voltage VIH (AC) (g), (i) DDR Input High Voltage VOL (g), (h) DDR Output Low Voltage 0 0.5 V 1 VOH (g), (h) DDR Output High Voltage 1.9 VCC2_5 V 1 2.5 Parameter Min Nom Max Unit DVREF_x – 0.150 V DVREF_x + 0.150 V DVREF_x – 0.310 DVREF_x + 0.
Electrical Characteristics Table 6-12. AGP Interface DC Characteristics Symbol Signal Group VIL_AGP (k),(m) Parameter Min Nom AGP Interface Input Low Voltage VIH_AGP (k),(m) AGP Interface Input High Voltage 0.450 VOL_AGP (k),(l) AGP Interface Output Low Voltage -0.3 VOH_AGP (k),(l) Unit 0.25 V V 0.750 0.850 V Pull-Down Impedance 0.90Ztarg 1.10Ztarg Ω ZPU Pull-Up Impedance 0.90Ztarg 1.10Ztarg Ω VCC1_5 I/O Supply Voltage 1.425 1.5 1.
Electrical Characteristics Table 6-14. Hub Interface 1.5 (HI_A) with Parallel Buffer Mode Configured for 50 Ω Symbol Signal Group VIL_HI (r) VIH_HI Parameter Min Nom Max Unit Hub Interface Input Low Voltage -0.3 0 HIVREF– 0.1 V (r) Hub Interface Input High Voltage HIVREF+ 0.1 0.7 1.2 V 0 0.05 V 0.75 0.8 0.
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Electrical Characteristics 182 Intel® E7505 Chipset MCH Datasheet
Ballout and Package Information 7 Ballout and Package Information This chapter provides the ballout and mechanical specifications for the E7505 chipset MCH. This information is intended to help with component placement and board routing. 7.1 Ballout Assignment Figure 7-1 is a footprint of the package ballout showing the layout coordinates for the component balls and general ballout location of the MCH interfaces.
Ballout and Package Information Figure 7-2.
Ballout and Package Information Figure 7-3.
Ballout and Package Information Table 7-1. MCH Ball List by Signal Name Signal Name AD_STB0# (AD_STBS0) 186 Ball # Table 7-1. MCH Ball List by Signal Name Signal Name Ball # Table 7-1.
Ballout and Package Information Table 7-1. MCH Ball List by Signal Name Signal Name Ball # Table 7-1. MCH Ball List by Signal Name Signal Name Ball # Table 7-1.
Ballout and Package Information Table 7-1. MCH Ball List by Signal Name Signal Name 188 Ball # Table 7-1. MCH Ball List by Signal Name Signal Name Table 7-1.
Ballout and Package Information Table 7-1. MCH Ball List by Signal Name Signal Name Ball # Table 7-1. MCH Ball List by Signal Name Signal Name Ball # Table 7-1.
Ballout and Package Information Table 7-1. MCH Ball List by Signal Name Signal Name Signal Name HI_B18 AG3 MA_B8 HI_B20 AF6 HI_B21 AL2 HIT# Table 7-1.
Ballout and Package Information Table 7-1. MCH Ball List by Signal Name Signal Name Ball # Table 7-1. MCH Ball List by Signal Name Signal Name Table 7-1.
Ballout and Package Information Table 7-1. MCH Ball List by Signal Name Signal Name 192 Table 7-1. MCH Ball List by Signal Name Ball # Signal Name Table 7-1.
Ballout and Package Information Table 7-1. MCH Ball List by Signal Name Signal Name Table 7-1. MCH Ball List by Signal Name Ball # Signal Name Table 7-1.
Ballout and Package Information Table 7-1. MCH Ball List by Signal Name Signal Name 194 Table 7-1. MCH Ball List by Signal Name Ball # Signal Name Table 7-1.
Ballout and Package Information Table 7-2. MCH Ball List by Ball Number Ball # Signal Name Table 7-2. MCH Ball List by Ball Number Ball # Signal Name Table 7-2.
Ballout and Package Information Table 7-2. MCH Ball List by Ball Number Ball # 196 Signal Name Table 7-2. MCH Ball List by Ball Number Ball # D22 HD28# E27 D23 HD25# D24 VSS D25 D26 Signal Name Table 7-2.
Ballout and Package Information Table 7-2. MCH Ball List by Ball Number Ball # Signal Name Table 7-2. MCH Ball List by Ball Number Ball # Signal Name Table 7-2.
Ballout and Package Information Table 7-2. MCH Ball List by Ball Number Ball # 198 Signal Name Table 7-2. MCH Ball List by Ball Number Ball # Signal Name Table 7-2.
Ballout and Package Information Table 7-2. MCH Ball List by Ball Number Ball # Signal Name Table 7-2. MCH Ball List by Ball Number Ball # Signal Name Table 7-2.
Ballout and Package Information Table 7-2.
Ballout and Package Information Table 7-2. MCH Ball List by Ball Number Ball # AC33 Signal Name DQ_B24 Table 7-2. MCH Ball List by Ball Number Ball # Signal Name Table 7-2.
Ballout and Package Information Table 7-2. MCH Ball List by Ball Number Ball # 202 Signal Name Table 7-2. MCH Ball List by Ball Number Ball # AG15 DQ_A50 AH20 AG16 VSS AG17 DQ_A46 AG18 Signal Name Table 7-2.
Ballout and Package Information Table 7-2. MCH Ball List by Ball Number Ball # Signal Name Table 7-2. MCH Ball List by Ball Number Ball # Signal Name Table 7-2.
Ballout and Package Information 7.2 Package Specifications The MCH package is a 42.5 mm x 42.5 mm FCBGA with 1005 LANDS. Figure 7-4 and Figure 7-5 show the package dimensions for the MCH. For more detailed package information, refer to the Intel® E7500/E7505 Chipset Thermal Design Guide. Figure 7-4. Package Dimensions (Bottom View) AN AM Detail A AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K 21.250 J H G F E D C B 1.
Ballout and Package Information Figure 7-5. Package Dimensions (Top and Side Views) 1.940 ± 0.150 mm Die Substrate 1.10 ± 0.10 mm 0.20 –C– Seating Plane 0.60 ± 0.10 mm See note 3. NOTES: 1. All dimensions are in millimeters. 2. Substrate thickness and package overall height are thicker than standard 492-L-PBGA 3. Primary datum —C— and seating plane are defined by the spherical crowns of the solder balls. 4. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Ballout and Package Information 7.3 Interface Trace Length Compensation In this section, detailed information is given about the internal component package trace lengths to enable trace length compensation. Trace length compensation is required for platform design. These lengths must be considered when matching trace lengths as described in the Intel® Xeon™ Processor and Intel® E7505 Chipset Platform Design Guide. Note that these lengths represent the actual lengths from pad to ball.
Ballout and Package Information 7.3.1 System Bus Signal Package Trace Length Data Table 7-3 provides the MCH package trace length information for the system bus. Table 7-3. MCH LPKG Data for the System Bus Signal Ball No.
Ballout and Package Information Table 7-3. MCH LPKG Data for the System Bus (Continued) Signal HDSTBN2# HDSTBP2# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# DINV2# 208 Ball No. B21 C20 A23 B22 C23 D20 B24 C21 D19 A20 B18 B19 E19 C18 H19 E18 H18 G19 A19 LPKG (mils) 682 597 727 678 639 450 738 598 524.
Ballout and Package Information 7.3.2 DDR Channel A Signal Package Trace Length Data Table 7-4 provides the MCH package trace length information for channel A of the DDR memory interface. Table 7-4. MCH LPKG Data for DDR Channel A Signal Ball No. LPKG (mils) Signal Ball No.
Ballout and Package Information Table 7-4. MCH LPKG Data for DDR Channel A (Continued) Signal 210 Ball No.
Ballout and Package Information 7.3.3 DDR Channel B Signal Package Trace Length Data Table 7-5 provides the MCH package trace length information for channel B of the DDR memory interface. Table 7-5. MCH LPKG Data for DDR Channel B Signal Ball No. LPKG (mils) Signal Ball No.
Ballout and Package Information Table 7-5. MCH LPKG Data for DDR Channel B (Continued) Signal 212 Ball No.
Ballout and Package Information 7.3.4 Hub Interface_A Signal Package Trace Length Data Table 7-6 provides the MCH package trace length information for Hub Interface_A. Table 7-6. MCH LPKG Data for Hub Interface_A Signal Ball No. PSTRBF_0 PSTRBS_0 HI_A0 HI_A1 HI_A2 HI_A3 HI_A4 HI_A5 HI_A6 HI_A7 HI_A8 HI_A9 HI_A10 HI_A11 7.3.
Ballout and Package Information 7.3.6 AGP Signal Package Trace Length Data Table 7-8 provides the MCH package trace length information for AGP. Note that only the AGP 2.0 signal names are shown. Table 7-8. MCH LPKG Data for AGP Signal 214 Ball No.
Testability 8 Testability For Automated Test Equipment (ATE), the MCH supports XOR-tree testing. XOR-tree testing allows board-level interconnections to be tested. An XOR-Tree is a chain of XOR gates, with each having one input pin or one bi-directional pin (used as an input pin only) connected to it. Figure 8-1. XOR Test Tree Chain VCC1_2 XOR Out Input Input Input Input Input or sd 8.1 XOR Test Mode Initialization XOR mode can be entered by driving the XORMODE# pin (ball G1) low.
Testability Table 8-1.
Testability Table 8-2.
Testability Table 8-3.
Testability Table 8-4.
Testability Table 8-5.
Testability Table 8-6.
Testability Table 8-7.
Testability Table 8-8.
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Working page only. Do not distribute. 1 Introduction ...........................................................................................................15 1.1 1.2 1.3 2 Signal Description ..............................................................................................21 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 Terminology ...................................................................................................15 Reference Documents .............................................
Working page only. Do not distribute. 3.6 2 3.5.21 REROTC—Receive Enable Reference Output Timing Control Register (D0:F0)66 3.5.22 CLOCK_DIS—CK/CK# Clock Disable Register (D0:F0) .................. 66 3.5.23 DDR_CNTL—DDR Memory Control Register (D0:F0) ..................... 67 3.5.24 SMRAM—System Management RAM Control Register (D0:F0)...... 68 3.5.25 ESMRAMC—Extended System Management RAM Control Register (D0:F0)69 3.5.26 ACAPID—AGP Capability Identifier Register (D0:F0) ...................... 70 3.5.
Working page only. Do not distribute. 3.7 3.8 3.6.30 DRAM_UELOG_ADD—DRAM First Uncorrectable Memory Error Address Register (D0:F1)97 3.6.31 DRAM_CELOG_SYNDROME—DRAM First Correctable Memory Error Register (D0:F1) ........................................................97 PCI-to-AGP Bridge Registers (Device 1, Function 0) ....................................98 3.7.1 VID1—Vendor Identification Register (D1:F0) ..................................99 3.7.2 DID1—Device Identification Register (D1:F0) ..........
Working page only. Do not distribute. 3.8.15 3.8.16 3.8.17 3.8.18 3.9 4 System Address Map ...................................................................................... 145 4.1 4.2 4.3 4.4 5 System Memory Spaces.............................................................................. 145 4.1.1 VGA and MDA Memory Spaces ..................................................... 148 4.1.2 PAM Memory Spaces ..................................................................... 149 4.1.
Working page only. Do not distribute. 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6 Electrical Characteristics ..............................................................................173 6.1 6.2 6.3 6.4 7 5.1.5 System Bus Interrupt ......................................................................156 Hub Interface_A (HI_A)................................................................................157 Hub Interface_B (HI_B)............................................................................
Working page only. Do not distribute. 8 Testability ............................................................................................................ 215 8.1 6 XOR Test Mode Initialization ....................................................................... 215 8.1.1 XOR Chains ....................................................................................
Working page only. Do not distribute. 1-1 2-1 3-1 3-2 4-1 4-2 4-3 7-1 7-2 7-3 7-4 7-5 8-1 Dual-Processor System Block Diagram ......................................................................19 MCH Interface Signals ................................................................................................22 PAM Registers.............................................................................................................57 Memory Socket Rows Description....................................
Working page only. Do not distribute.
Working page only. Do not distribute. 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 7-1 7-2 7-3 7-4 7-5 7-6 Supported Memory Modes ..........................................................................................18 DIMM Support ............................................................................................................18 Host Interface Signals....
Working page only. Do not distribute. 7-7 7-8 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 2 MCH LPKG Data for Hub Interface_B.................................................................... 213 MCH LPKG Data for AGP ...................................................................................... 214 XOR Chain 0 ............................................................................................................ 216 XOR Chain 1 ..........................................................................
