Intel® Xeon® Processor E78800/4800/2800 v2 Product Family Datasheet - Volume One Electrical, Mechanical and Thermal Specifications - Volume 1 of 3 February 2014 Reference Number: 329594-001
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Table of Contents 1 Overview ................................................................................................................. 11 1.1 Introduction ..................................................................................................... 11 1.1.1 Processor Feature Details ........................................................................ 13 1.1.2 Supported Technologies .......................................................................... 13 1.2 Interfaces .............
3.3 3.4 3.2.6 Package C-State Power Specifications........................................................40 System Memory Power Management ....................................................................40 3.3.1 CKE Power-Down ....................................................................................40 3.3.2 Self Refresh ...........................................................................................41 3.3.3 DRAM I/O Power Management ..............................................
6.10 6.11 6.12 AC Specifications............................................................................................... 93 6.10.1 Signal AC Specifications .......................................................................... 93 AC Timing Waveforms........................................................................................ 97 Signal Quality ................................................................................................. 106 6.12.
4-8 4-9 4-10 4-11 4-12 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 8-1 8-2 8-3 8-4 DTS: 105W 12 - 15 Core Thermal Profile...............................................................54 DTS: 105W 8 - 10 Core Thermal Profile ................................................................55 DTS: 105W 6 Core Thermal Profile .......................................................................
4-3 4-4 4-5 4-6 4-7 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 7-1 7-2 8-1 8-2 8-3 9-1 155W Thermal Profile Table ................................................................................ 49 Tcase: 130W Thermal Specifications .................................................................... 50 130W Thermal Profile Table ...................................
9-2 9-3 9-4 8 Write Byte SMBus Packet .................................................................................. 167 Memory Device SMBus Addressing ..................................................................... 168 128-Byte ROM Checksum Values .......................................................................
Revision History Document Number Revision Number 329594 001 Description Initial Release Revision Date February 2014 § Intel® Xeon® Processor E7-8800/4800/2800 v2 Product Family Datasheet Volume One, February 2014 9
Intel® Xeon® Processor E7-8800/4800/2800 v2 Product Family Datasheet Volume One, February 2014
Overview 1 Overview 1.1 Introduction ALL INFORMATION IN THIS DOCUMENT IS PRELIMINARY AND SUBJECT TO CHANGE. The Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume One provides DC and AC electrical specifications, signal integrity, differential signaling specifications, land and signal definitions, and an overview of additional processor feature interfaces. This document is intended to be distributed as a part of the complete EDS document which consists of three volumes.
Overview Figure 1-1. Intel® Xeon® E7 v2 Processor on a 2 Socket Platform Figure 1-2.
Overview Figure 1-3. Intel® Xeon® E7 v2 Processor on a 8 Socket Platform 1.1.1 Processor Feature Details • Each core supports two threads (Intel® Hyper-Threading Technology), up to 30 threads per socket • 46-bit physical addressing and 48-bit virtual addressing • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data mid-level (L2) cache for each core • Up to 37.5 MB last level cache (LLC): up to 2.
Overview • Intel® Advanced Vector Extensions (Intel® AVX) • Intel® Hyper-Threading Technology • Execute Disable Bit • Intel® Turbo Boost Technology • Intel® Intelligent Power Technology • Enhanced Intel SpeedStep® Technology 1.2 Interfaces 1.2.
Overview 1.2.2 PCI Express* • The PCI Express* port(s) are fully-compliant to the PCI Express* Base Specification, Revision 3.0 (PCIe 3.0) • Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s) • Up to 32 lanes of PCI Express* interconnect for general purpose PCI Express* devices at PCIe* 3.0 speeds that are configurable for up to 8 independent ports • 4 lanes of PCI Express* at PCIe* 2.
Overview • APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of Interrupt” broadcast message when initiated by the processor. • System Management Interrupt (SMI), SCI, and SERR error indication • Static lane numbering reversal support • Supports DMI2 virtual channels VC0, VC1, VCm, and VCp 1.2.4 Intel® QuickPath Interconnect (Intel® QPI) • Compliant with Intel QuickPath Interconnect v1.
Overview 1.3 Power Management Support 1.3.1 Processor Package and Core States • ACPI C-states as implemented by the following processor C-states: — Package: PC0, PC1/PC1E, PC3, PC6 — Core: CC0, CC1/CC1E, CC3, CC6 • Enhanced Intel SpeedStep Technology 1.3.2 System States Support • S0, S1(transitional only),S4, S5 1.3.3 Memory Controller • Memory thermal monitoring via MEM_HOT_C01_N and MEM_HOT_C23_N pins 1.3.4 PCI Express* • L0s and L1 low power states 1.3.
Overview 1.6 Terminology Term ASPM 18 Description Active State Power Management BMC Baseboard Management Controllers Cbo Cache and Core Box. It is a term used for internal logic providing ring interface to LLC and Core.
Overview Term Description Jitter Any timing variation of a transition edge or edges from the defined Unit Interval (UI). IOV I/O Virtualization LGA2011-1 Socket The 2011-0 land FCLGA package mates with the system board through this surface mount, 2011-0 contact socket.
Overview Term Description Storage Conditions A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks.
Overview Table 1-2. Public Specifications (Sheet 2 of 2) Document 1.8 Document Number/ Location DDR3 SDRAM Specification http://www.jedec.org Low (JESD22-A119) and High (JESD-A103) Temperature Storage Life Specifications http://www.jedec.
Overview 22 Intel® Xeon® Processor E7-8800/4800/2800 v2 Product Family Datasheet Volume One, February 2014
Technologies 2 Technologies 2.1 Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets.
Technologies 2.1.
Technologies • Support for hardware based flushing of translated but pending writes and pending reads upon IOTLB invalidation. • Support for page-selective IOTLB invalidation. • Support for ARI (Alternative Requester ID - a PCI SIG ECR for increasing the function number count in a PCIe device) to support IOV devices. 2.1.3.
Technologies These extensions enhance two areas: • The launching of the Measured Launched Environment (MLE). • The protection of the MLE from potential corruption. The enhanced platform provides these launch and control interfaces using Safer Mode Extensions (SMX). The SMX interface includes the following functions: • Measured/Verified launch of the MLE. • Mechanisms to ensure the above measurement is protected and stored in a secure location.
Technologies instructions make Intel AES-NI simple to implement, with reduced code size. This helps reducing the risk of inadvertent introduction of security flaws, such as difficult-todetect side channel leaks. 2.2.4 Execute Disable Bit Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system. • Allows the processor to classify areas in memory by where application code can execute and where it cannot.
Technologies Note: Intel Turbo Boost Technology is only active if the operating system is requesting the P0 state. For more information on P-states and C-states refer to Chapter 3, “Power Management.” 2.5 Enhanced Intel SpeedStep® Technology The processor supports Enhanced Intel SpeedStep Technology as an advanced means of enabling very high performance while also meeting the power-conservation needs of the platform.
Technologies • Power Efficiency - Intel AVX is extremely power efficient. Combined with the high performance that it can deliver, applications that lend themselves heavily to using Intel AVX can be much more energy efficient and realize a higher performance-perwatt. • Extensibility - Intel AVX has built-in extensibility for the future vector extensions: — OS context management for vector-widths beyond 256 bits is streamlined.
Technologies 30 Intel® Xeon® Product 2800/4800/8800 v2 Product Family Datasheet Volume One, February 2014
Power Management 3 Power Management This chapter provides information on the following power management topics: • ACPI States • System States • Processor Core/Package States • Integrated Memory Controller (IMC) and System Memory States • Direct Media Interface Gen 2 (DMI2)/PCI Express Link States • Intel QuickPath Interconnect States 3.1 ACPI States Supported The ACPI states supported by the processor are described in this section. 3.1.1 System States Table 3-1. System States State 3.1.
Power Management Table 3-2. Package C-State Support (Sheet 2 of 2) Package C-State Core States PC3 - Light Retention CC3-CC6 • • • • Core C-state Snoop Response Time Interrupt Response Time Non Snoop Response Time PC6 Deeper Retention CC6 • • • • LLC ways open Snoop Response Time Non Snoop Response Time Interrupt Response Time LLC Fully Flushed Notes1 Vcc = retention PLL = OFF No 2,3,4 Vcc = retention PLL = OFF No 2,3,4 Retention and PLL-Off Limiting Factors Notes: 1.
Power Management Table 3-4. System Memory Power States (Sheet 2 of 2) State Self-Refresh Description CKE de-asserted. In this mode, no transactions are executed and the system memory consumes the minimum possible power. Self refresh modes apply to all memory channels for the processor. • IO-MDLL Off: Option that sets the IO master DLL off when self refresh occurs. • PLL Off: Option that sets the PLL off when self refresh occurs.
Power Management 3.2 Processor Core/Package Power Management While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power Cstates have longer entry and exit latencies. 3.2.
Power Management Figure 3-1. Idle Power Management Breakdown of the Processor Cores T h re a d 0 T h re a d 1 C o r e 0 S ta te T h re a d 0 T h re a d 1 C o r e N S ta te P r o c e s s o r P a c k a g e S ta te Figure 3-2. Thread and Core C-State Entry and Exit C0 MWAIT(C1), HLT MWAIT(C6), P_LVL3 I/O Read MWAIT(C3), P_LVL2 I/O Read C1 C3 C6 While individual threads can request low power C-states, power saving actions only take place once the core C-state is resolved.
Power Management For legacy operating systems, P_LVLx I/O reads are converted within the processor to the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be enabled in the BIOS. Note: The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as follows. Table 3-8.
Power Management 3.2.4.3 Core C3 State Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while maintaining its architectural state. All core clocks are stopped at this point.
Power Management — If the break event is masked, the processor attempts to re-enter its previous package state. • If the break event was due to a memory access or snoop request. — But the platform did not request to keep the processor in a higher package C-state, the package returns to its previous C-state. — And the platform requests a higher power C-state, the memory access or snoop request is serviced and the package remains in the higher power C-state.
Power Management Figure 3-3. Package C-State Entry and Exit C1 C0 C2 C3 3.2.5.1 C6 Package C0 State The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0. 3.2.5.
Power Management • L3 shared cache retains context and becomes inaccessible in this state. • Additional power savings actions, as allowed by the exit latency requirements, include putting Intel QPI and PCIe* links in L1, the uncore is not available, further voltage reduction can be taken. In package C3, the ring will be off and as a result no accesses to the LLC are possible. The content of the LLC is preserved. 3.2.5.
Power Management The memory controller transitions the DRAM to power-down by de-asserting CKE and driving a NOP command. The memory controller will tri-state all DDR interface lands except CKE (de-asserted) and ODT while in power-down. The memory controller will transition the DRAM out of power-down state by synchronously asserting CKE and driving a NOP command. When CKE is off the internal DDR clock is disabled and the DDR power is significantly reduced.
Power Management 3.3.2.3 DLL and PLL Shutdown Self refresh, according to configuration, may be a trigger for master DLL shut-down and PLL shut-down. The master DLL shut-down is issued by the memory controller after the DRAMs have entered self refresh. The PLL shut-down and wake-up is issued by the PCU. The memory controller gets a signal from PLL indicating that the memory controller can start working again. 3.3.3 DRAM I/O Power Management Unused signals are tristated to save power.
Thermal Management Specifications 4 Thermal Management Specifications 4.1 Package Thermal Specifications The Intel® Xeon® E7v2 processor requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system, see section Section 6.7.1, “Storage Conditions Specifications”.
Thermal Management Specifications The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT_N (see Section 6, “Electrical Specifications”). Systems that implement fan speed control must be designed to use this data. Systems that do not alter the fan speed need to guarantee the case temperature meets the thermal profile specifications.
Thermal Management Specifications 4.1.3 Intel® Xeon® E7v2 Processor Thermal Profiles Table 4-1. Intel® Xeon® E7v2 Processor SKU Summary Table Thermal Profile TDP SKUs Note: Tcase DTS 155W Figure 4-1 Figure 4-2, Figure 4-5, Figure 4-6 130W Figure 4-7 Figure 4-8 105W Figure 4-7 Figure 4-8 SKUs are subject to change. Please contact your Intel Field Representative to obtain the latest SKU information. 4.1.3.1 155W Thermal Specifications Table 4-2.
Thermal Management Specifications Figure 4-1. Tcase: 155W Thermal Profile Notes: 1. Please refer to Table 4-5 for discrete points that constitute this thermal profile. 2. Refer to the Intel® Xeon® Product 2800/4800/8800 v2 Product FamilyIntel® Xeon® Product 2800/4800/8800 v2 Product Family Thermal/Mechanical Design Guide for system and environmental implementation details.
Thermal Management Specifications Figure 4-2. DTS: 155W 15 Core Thermal Profile Notes: 1. Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 4-5 for discrete points that constitute the thermal profile. 3. Refer to the Intel® Xeon® Product 2800/4800/8800 v2 Product FamilyIntel® Xeon® Product 2800/4800/8800 v2 Product Family Thermal/Mechanical Design Guide for system and environmental implementation details.
Thermal Management Specifications Figure 4-3. DTS: 155W 10 Core Thermal Profile Notes: 1. Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 4-5 for discrete points that constitute the thermal profile. 3. Refer to the Intel® Xeon® Product 2800/4800/8800 v2 Product FamilyIntel® Xeon® Product 2800/4800/8800 v2 Product Family Thermal/Mechanical Design Guide for system and environmental implementation details.
Thermal Management Specifications Figure 4-4. DTS: 155W 6 Core Thermal Profile Notes: 1. Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 4-5 for discrete points that constitute the thermal profile. 3. Refer to the Intel® Xeon® Product 2800/4800/8800 v2 Product FamilyIntel® Xeon® Product 2800/4800/8800 v2 Product Family Thermal/Mechanical Design Guide for system and environmental implementation details.
Thermal Management Specifications Table 4-3. 155W Thermal Profile Table (Sheet 2 of 2) Power (W) Max TCASE (°C) 15 Core Max DTS (°C) 10 Core Max DTS (°C) 6 Core Max DTS (°C) 85 64.6 70.9 75.3 79.7 90 65.5 72.2 76.9 81.5 95 66.5 73.5 78.4 83.3 100 67.4 74.8 80.0 85.1 105 68.3 76.1 81.5 86.9 110 69.2 77.4 83.1 88.7 115 70.1 78.7 84.6 90.5 120 71.1 80.0 86.2 92.4 125 72.0 81.3 87.7 94.2 130 72.9 82.5 89.3 96.0 135 73.8 83.8 90.8 97.8 140 74.7 85.
Thermal Management Specifications Figure 4-5. Tcase: 130W Thermal Profile Notes: 1. Please refer to Table 4-7 for discrete points that constitute this thermal profile. 2. Refer to the Intel® Xeon® Product 2800/4800/8800 v2 Product FamilyIntel® Xeon® Product 2800/4800/8800 v2 Product Family Thermal/Mechanical Design Guide for system and environmental implementation details.
Thermal Management Specifications Figure 4-6. DTS: 130W 12-15 Core Thermal Profile Notes: 1. Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 4-5 for discrete points that constitute the thermal profile. 3. Refer to the Intel® Xeon® Product 2800/4800/8800 v2 Product FamilyIntel® Xeon® Product 2800/4800/8800 v2 Product Family Thermal/Mechanical Design Guide for system and environmental implementation details.
Thermal Management Specifications Table 4-5. 130W Thermal Profile Table (Sheet 2 of 2) Power (W) Max TCASE (°C) 12-15 Core Max DTS (°C) 90 65.6 72.5 95 66.5 73.8 100 67.5 75.2 105 68.4 76.5 110 69.3 77.8 115 70.2 79.1 120 71.2 80.4 125 72.1 81.7 130 73.0 83 4.1.3.3 105W Thermal Specifications Table 4-6. Tcase: 105W Thermal Specifications Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) 105 5 See Figure 4-7 and Table 4-7 Notes 1, 2, 3, 4, 5 Notes: 1.
Thermal Management Specifications Figure 4-7. Tcase: 105W Thermal Profile Notes: 1. Please refer to Table 4-7 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Product 2800/4800/8800 v2 Product FamilyIntel® Xeon® Product 2800/4800/8800 v2 Product Family Thermal/Mechanical Design Guide for system and environmental implementation details. Figure 4-8.
Thermal Management Specifications Notes: 1. Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 4-7 for discrete points that constitute this thermal profile. 3. Refer to the Intel® Xeon® Product 2800/4800/8800 v2 Product FamilyIntel® Xeon® Product 2800/4800/8800 v2 Product Family Thermal/Mechanical Design Guide for system and environmental implementation details. Figure 4-9.
Thermal Management Specifications Figure 4-10. DTS: 105W 6 Core Thermal Profile Notes: 1. Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 4-7 for discrete points that constitute this thermal profile. 3. Refer to the Intel® Xeon® Product 2800/4800/8800 v2 Product FamilyIntel® Xeon® Product 2800/4800/8800 v2 Product Family Thermal/Mechanical Design Guide for system and environmental implementation details.
Thermal Management Specifications Table 4-7. 4.1.4 105W Thermal Profile Table (Sheet 2 of 2) Power (W) Max TCASE (°C) Max 12/15 Core DTS (°C) Max 8/10 Core DTS (°C) Max 6Core DTS (°C) 70 61.7 66.3 70.3 73.7 75 62.6 67.6 71.9 75.4 80 63.5 68.8 73.4 77.2 85 64.4 70.0 74.9 79.0 90 65.3 71.3 76.4 80.7 95 66.2 72.5 78.0 82.5 100 67.1 73.8 79.5 84.2 105 68.0 75.0 81.0 86.
Thermal Management Specifications 4.2 Processor Core Thermal Features 4.2.1 Processor Temperature A new feature in the Intel® Xeon® E7v2 processor is a software readable field in the IA32_TEMPERATURE_TARGET register that contains the minimum temperature at which the TCC will be activated and PROCHOT_N will be asserted.
Thermal Management Specifications This method includes multiple operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. The remaining points consist of both lower operating frequencies and voltages. When the TCC is activated, the processor automatically transitions to the new lower operating frequency. This transition occurs very rapidly (on the order of microseconds).
Thermal Management Specifications been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. Clock modulation is automatically engaged as part of the TCC activation when the Frequency/SVID targets are at their minimum settings.
Thermal Management Specifications With a properly designed and characterized thermal solution, it is anticipated that PROCHOT_N will be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT_N in the anticipated ambient environment may cause a noticeable performance loss. 4.2.
Thermal Management Specifications 4.2.6.3 Integrated Dual SMBus Master Controllers for System Memory Interface The processor includes two integrated SMBus master controllers running at 100 KHz for dedicated PCU access to the serial presence detect (SPD) devices and thermal sensors (TSoD) on the DIMMs. Each controller is responsible for a pair of memory channels and supports up to eight SMBus slave devices. Note that clock-low stretching is not supported by the processor.
Signal Descriptions 5 Signal Descriptions This chapter describes the Intel® Xeon® E7v2 processor signals. They are arranged in functional groups according to their associated interface or category. 5.1 System Memory Interface Table 5-1. Memory Channel Signals Signal Name Description MEM_SCL_C{3:0} MEM_SDA_C{3:0} SMBus clock for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs. VMSE{0/1/2/3}_CLK_N VMSE{0/1/2/3}_CLK_P Clocks to the memory buffer.
Signal Descriptions 5.4 Intel QuickPath Interconnect Signals Table 5-4. Intel QPI Port 0, 1 and 2 Signals Signal Name Description QPI{2:0}_CLKRX_DN/DP Reference Clock Differential Input. These pins provide the PLL reference clock differential input. 100 MHz typ. QPI{2:0}_CLKTX_DN/DP Reference Clock Differential Output. These pins provide the PLL reference clock differential input. 100 MHz typ. QPI{2:0}_DRX_DN/DP[19:00] Intel QPI Receive data input.
Signal Descriptions Table 5-7. JTAG and TAP Signals (Sheet 2 of 2) Signal Name Description TDI TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TMS TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
Signal Descriptions 5.10 Processor Asynchronous Sideband and Miscellaneous Signals Table 5-10. Processor Asynchronous Sideband Signals (Sheet 1 of 2) Signal Name Description CAT_ERR_N Indicates that the system has experienced a fatal or catastrophic error and cannot continue to operate. The processor will assert CAT_ERR_N for nonrecoverable machine check errors and other internal unrecoverable errors. It is expected that every processor in the system will wire-OR CAT_ERR_N for all processors.
Signal Descriptions Table 5-10. Processor Asynchronous Sideband Signals (Sheet 2 of 2) Signal Name Description THERMTRIP_N Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible critical over-temperature conditions: One, the processor junction temperature has reached a level beyond which permanent silicon damage may occur and Two, the system memory interface has exceeded a critical temperature limit set by BIOS.
Signal Descriptions Table 5-11. Miscellaneous Signals (Sheet 2 of 2) Signal Name 5.11 Description RSVD RESERVED. All signals that are RSVD must be left unconnected on the board. SKTOCC_N SKTOCC_N (Socket occupied) will be pulled to ground in the processor package to indicate that the processor is present. There is no connection to the processor silicon for this signal. 4.7kW pull-up to 3.
Electrical Specifications 6 Electrical Specifications 6.1 Processor Signaling Intel® Xeon® E7 v2 processors include 2011 lands, which utilize various signaling technologies. Signals are grouped by electrical characteristics and buffer type into various signal groups.
Electrical Specifications 6.1.5 Platform Environmental Control Interface (PECI) PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices. The Intel® Xeon® E7 v2 processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP, BCLK{0/1}_DN inputs are provided in Table 6-21 and AC specifications in Table 6-26. These specifications must be met while also meeting the associated signal quality specifications outlined in Section 6.12.
Electrical Specifications Table 6-1. Power and Ground Lands Power and Ground Lands Comments 218 Each VCC land must be supplied with the voltage determined by the SVID Bus signals. Table 6-3 Defines the voltage level associated with each core SVID pattern.Table 6-12, Figure 6-2, and Figure 6-4 represent VCC static and transient limits. VCC has a VBOOT setting of 0.0 V. VCC33 1 VCC33 supplies a fixed 3.3 volt stand by voltage to supply PIROM and the OEM scratch ROM.
Electrical Specifications 6.1.9.3.1 SVID Commands The Intel® Xeon® E7 v2 processor provides the ability to operate while transitioning to a new VID setting and its associated processor voltage rail (VCC and VSA). This is represented by a DC shift. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target voltage. Transitions above the maximum specified VID are not supported.
Electrical Specifications 6.1.9.3.5 SVID Power State Functions: SetPS The processor has three power state functions and these will be set seamlessly via the SVID bus using the SetPS command. Based on the power state command, the SetPS commands sends information to VR controller to configure the VR to improve efficiency, especially at light loads.
Electrical Specifications Figure 6-2. VR Power-State Transitions PS0 PS1 6.1.9.3.6 PS2 PS3 SVID Voltage Rail Addressing The processor addresses 2 different voltage rail control segments within VR12 (VCC and VSA). The SVID data packet contains a 4-bit addressing code: Table 6-2. SVID Address Usage PWM Address (HEX) Intel® Xeon® E7v2 00 Vcc 01 Vsa 02 VMSE MC0 03 +1 not used 04 VMSE MC0 05 +1 not used 06 VMSE MC1 07 +1 not used 08 VMSE MC1 Notes: 1.
Electrical Specifications Table 6-3. HEX VR12.0 Reference Code Voltage Identification (VID) VCC, VSA HEX VCC, VSA HEX VCC, VSA HEX VCC, VSA HEX VCC, VSA HEX VCC, VSA 00 0.00000 55 0.67000 78 0.84500 9B 1.02000 BE 1.19500 E1 1.37000 33 0.50000 56 0.67500 79 0.85000 9C 1.02500 BF 1.20000 E2 1.37500 34 0.50500 57 0.68000 7A 0.85500 9D 1.03000 C0 1.20500 E3 1.38000 35 0.51000 58 0.68500 7B 0.86000 9E 1.03500 C1 1.21000 E4 1.38500 36 0.51500 59 0.
Electrical Specifications 6.1.10 Reserved or Unused Signals All Reserved (RSVD) signals must not be connected. Connection of these signals to power, ground or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 7, “Processor Land Listing” for a land listing of the processor and the location of all Reserved signals. For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level.
Electrical Specifications Table 6-5.
Electrical Specifications Table 6-5. Signal Groups (Sheet 3 of 3) Differential/Single Ended Signals1 Buffer Type Processor Asynchronous Sideband Signals Single ended CMOS1.05v Input BIST_ENABLE BMCINIT FRMAGENT PWRGOOD PMSYNC RESET_N SOCKET_ID[2:0] TXT_AGENT TXT_PLTEN Open Drain CMOS Input/Output CAT_ERR_N CPU_ONLY_RESET MEM_HOT_C{01/23}_N PROCHOT_N Open Drain CMOS Output ERROR_N[2:0] THERMTRIP_N Miscellaneous Signals N/A Output PROC_ID[1:0] SKTOCC_N Power/Other Signals 1. Table 6-6.
Electrical Specifications Table 6-6. Signals with On-Die Termination (Sheet 2 of 2) Pull Up /Pull Down Rail SVID_IDLE_N PU VTT TCK PD TDI PU TRST_N PU TMS PU VTT TXT_AGENT PD TXT_PLTEN PU Signal Name Value Units Notes 1k-6k Ohms 1 1k-6k Ohms 1 VTT 1k-6k Ohms 1 VTT 1k-6k Ohms 1 VTT 1k-6k Ohms 1 1k-6k Ohms 1 1K-6K Ohms 1 Notes: 1. Refer to Table 6-19 for details on the RON (Buffer on Resistance) value for this signal. 6.
Electrical Specifications since this is the path to the system BIOS. See Table 6-9 for a list of output tri-state FRB signals. Socket level FRB will tri-state processor outputs via the PROCHOT_N signal. Assertion of the PROCHOT_N signal through RESET_N de-assertion will tri-state processor outputs. Note, that individual core disabling is also supported for those cases where disabling the entire package is not desired.
Electrical Specifications Mixing processors of different steppings but the same model (as per CPUID instruction) is supported. Details regarding the CPUID instruction are provided in the AP-485, Intel® Processor Identification and the CPUID Instruction application note. 6.6 Flexible Motherboard Guidelines (FMB) The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the Intel® Xeon® E7 v2 processor will have over certain time periods.
Electrical Specifications device storage conditions for a sustained period of time. At conditions outside sustained limits, but within absolute maximum and minimum ratings, quality & reliability may be affected. Table 6-10. Storage Condition Ratings Symbol Parameter Min Max Unit Tabsolute storage The minimum/maximum device storage temperature beyond which damage (latent or otherwise) may occur when subjected to for any length of time.
Electrical Specifications 6.9 DC Specifications DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting specifications for case temperature (TCASE specified in Section 4), clock frequency, and input voltages. Care should be taken to read all notes associated with each specification. 6.9.1 Voltage and Current Specifications Table 6-12.
Electrical Specifications 12. 13. 14. 15. 16. 17. FMB is the flexible motherboard guidelines. See Section 6.6 for FMB details. DC + AC + Ripple = Total Tolerance For Power State Functions see Section 6.1.9.3.5. VSA_VID does not have a loadline, the output voltage is expected to be the VID value. VVMSE tolerance at processor pins. Tolerance for VR at remote sense is ±2.0%*VVMSE. The VCCPLL, VVMSE01, VVMSE23 voltage specification requirements are measured across vias on the platform.
Electrical Specifications 3. 4. 5. 6. ICC_TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used for the voltage regulator thermal assessment. The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion. Specification is at TCASE = 50 °C. Characterized by design (not tested).
Electrical Specifications Table 6-14. VCC Static and Transient Tolerance Intel® Xeon® E7 v2 Processor (Sheet 2 of 2) ICC (A) VCC_MAX (V) VCC_TYP (V) VCC_MIN (V) Notes 165 VID - 0.117 VID - 0.132 VID - 0.147 1,2,3,4,5,6 170 VID - 0.121 VID - 0.136 VID - 0.151 1,2,3,4,5,6 175 VID - 0.125 VID - 0.140 VID - 0.155 1,2,3,4,5,6 180 VID - 0.129 VID - 0.144 VID - 0.159 1,2,3,4,5,6 185 VID - 0.133 VID - 0.148 VID - 0.163 1,2,3,4,5,6 190 VID- 0.137 VID - 0.152 VID - 0.
Electrical Specifications 6.9.2 Die Voltage Validation Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 6-15 when measured across the VCC_SENSE and VSS_VCC_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. Figure 6-4.
Electrical Specifications Figure 6-5. VCC Overshoot Example Waveform VOS_MAX Voltage [V] VID + VOS_MAX VccMAX (I1) TOS_MAX 0 5 10 15 20 25 30 Time [us] Notes: 1. VOS_MAX is the measured overshoot voltage. 2. TOS_MAX is the measured time duration above VccMAX(I1). 3. Istep: Load Release Current Step, for example, I2 to I1, where I2 > I1. 4. VccMAX(I1) = VID - I1*RLL + 15 mV 6.9.3 Signal DC Specifications Table 6-16.
Electrical Specifications Table 6-17. System Reference Clock (BCLK{0/1}) DC Specifications Symbol Parameter Signal Min 0.150 VBCLK_diff_ih Differential Input High Voltage Differential VBCLK_diff_il Differential Input Low Voltage Differential Vcross (abs) Absolute Crossing Point Single Ended Vcross(rel) Relative Crossing Point ΔVcross Max Unit Figure Notes1 N/A V 6-13 -0.150 V 6-13 0.250 0.550 V 6-10 6-14 2, 4, 7 Single Ended 0.250 + 0.5*(VHavg 0.700) 0.550 + 0.5*(VHavg 0.
Electrical Specifications Table 6-19. JTAG and TAP Signals DC Specifications (Sheet 2 of 2) Symbol Parameter Min IIL Input Leakage Current Signals BPM_N[7:0], TDO, EAR_N (RTEST = 50 ohm) IO Output Current Signal PRDY_N (RTEST = 500 ohm) -1.50 Input Edge Rate Signals: BPM_N[7:0], EAR_N, PREQ_N, TCK, TDI, TMS, TRST_N 0.05 Max Units +900 uA +1.50 uA Notes V/ns 1 Note: 1. These are measured between VIL and VIH. Table 6-20.
Electrical Specifications Table 6-21. Processor Asynchronous Sideband DC Specifications (Sheet 2 of 2) Symbol Parameter Min Max Units Notes -1.50 +1.50 uA 1,2 IO_CMOS1.0v Output Current (RTEST = 500 ohm) ANM_Rise Non-Monotonicity Amplitude, Rising Edge Signal PWRGOOD 0.135 V 4 ANM_Fall Non-Monotonicity Amplitude, Falling Edge Signal PWRGOOD 0.165 V 4 0.
Electrical Specifications Intel® Xeon® E7 v2 processor DC specifications for the Intel® QPI interface are available in the Intel® QuickPath Interconnect V1.1 Base Electrical Specification and Validation Methodologies. This document will provide only the processor exceptions to the Intel® QuickPath Interconnect V1.1 Base Electrical Specification and Validation Methodologies. 6.9.3.4 Reset and Miscellaneous Signal DC Specifications For a power-on Reset, RESET_N must stay active for at least 3.
Electrical Specifications Table 6-24. BCLK{0/1} Periods with Spread Spectrum Clocking (SSC) SSC On 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns Notes: 1. SSC is Spread Spectrum Clocking. The processor core clock frequency is derived from BCLK{0/1}. The system reference clock to processor core clock ratio is determined during initialization. 2. Ideal Period Nominal: This is as an ideal reference target (0 ppm) to use for calculating the rest of the period measurement values. 3.
Electrical Specifications Table 6-26. JTAG and TAP Signal AC Specifications (Sheet 2 of 2) T# Parameter Min Typ Max T5: TDO Clock to Output Valid Delay Unit Figure Notes1,2 4 5 ns 6-17 1 8.6 ns 6-17 T5: BCLK0 to PRDY_N Output Valid Delay N/A 5 ns 6-17 Ts: TDI, TMS Setup Time 6.5 ns 6-18 3 Th: TDI, TMS Hold Time 6.
Electrical Specifications Table 6-28.
Electrical Specifications 6.10.1.2 DMI2/PCI Express AC Specifications Intel® Xeon® E7 v2 processor AC specifications for the PCI Express* are available in the PCI Express® Base Specification 2.0 and 1.0. This document will provide only the processor exceptions to the PCI Express® Base Specification 2.0 and 1.0. 6.10.1.3 Intel® QuickPath Interconnect AC Specifications Intel® QuickPath Interconnect specifications are defined at the processor lands.
Electrical Specifications Figure 6-7. VMSE Command / Control and Clock Timing Waveform CK (IMC) BIOS Programmable Delay RAS_N CAS_N WE_N (IMC) Tcmd_co Tcmd_co Tctrl_cs Tctrl_cs Control Signals (IMC) Figure 6-8. VMSE Clock to Output Timing Waveform Figure 6-9. VMSE Clock to DQS_DN Skew Timing Waveform CK (IMC) TDQS_CO DQS (IMC) 98 TDQS_CO 0.
Electrical Specifications Figure 6-10. BCLK{0/1} Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 550 + 0.5 (VHavg - 700) 450 400 250 + 0.5 (VHavg - 700) 350 300 250 mV 250 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 6-11. BCLK{0/1} Differential Clock Measurement Points for Duty Cycle and Period Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) 0.
Electrical Specifications Figure 6-13. BCLK{0/1} Differential Clock Measurement Point for Ringback T STABLE VRB-Differential VIH = +150 mV VRB = +100 mV 0.0V VRB = -100 mV VIL = -150 mV REFCLK + T STABLE VRB-Differential Figure 6-14. BCLK{0/1} Single Ended Clock Measurement Points for Absolute Cross Point and Swing VMAX = 1.40V BCLK_DN VCROSS MAX = 550mV VCROSS MIN = 250mV BCLK_DP VMIN = -0.30V Figure 6-15.
Electrical Specifications Figure 6-16. SMBus Timing Waveform t t LOW tF R t HD;STA Clk t HD;STA t t HIGH HD;DAT t SU;DAT t SU;STA t SU;STO Data tBUF P STOP S S START START P STOP Figure 6-17. BCLK to JTAG/TAP Signals Output Valid Delay BCLK V T5 Data Valid Signal V = 0.5 * VTT Figure 6-18. JTAG/TAP Output Valid Delay Timing Waveform TCK V Ts Th Data Valid Signal V = 0.
Electrical Specifications Figure 6-19. PROCHOT_N Setup and Hold Timing Waveforms V BCLK TS Th PROCHOT_N Ts = Setup Time Th = Hold Time V = 0.5 * VTT PROCHOT_N Setup / Hold Time Figure 6-20.
Electrical Specifications Figure 6-21.
Electrical Specifications Figure 6-22. Voltage Sequence Timing Requirements Notes: 1. Once up, VVMSE and VVMSE23, must stay up, even during memory hot plug. 2. Timing must be greater than 0ms. 3. VCCPECI is used by next generation CPUs. The pad is a no connect on package for Intel® Xeon® E7v2. Can be supplied via local VTT (and VCCIO_IN) of each socket, in which case VCCPECI somes up with VTT. Could also be supplied with Intel® C600 series chipset VPROC_IO (VCC_CPU_IO) at 1.
Electrical Specifications 11. If necessary, staggering of processor loads assumes all eternal rails to the processor in a node are powered on together, and staggering occurs with the PWRGOOD signals. If the PWRGOOD signals are staggered, then assertions of PWRGOOD must be at every 864 bclocks for Intel® Xeon® E7v2 and 384 bclocks for later CPUs. There is no setup or hold requirement to the bclock. 12. <5ms 13. SVID driven by processor 14. For Intel® Xeon® E7v2, VCC is 0V until SVID drives data.
Electrical Specifications Figure 6-24. PWRGOOD Signal Waveform Vovershoot TNM VIL_MAX ANM_rise ANM_fall VIH_MIN TNM Vundershoot 6.12 Signal Quality Data transfer requires the clean reception of data signals and clock signals. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swings will adversely affect system timings. Ringback and signal non-monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines.
Electrical Specifications 6.12.2 I/O Signal Quality Specifications Signal Quality specifications for PCIe Signals are included as part of the PCIe DC specifications and PCIe AC specifications. Various scenarios have been simulated to generate a set of layout guidelines. 6.12.
Electrical Specifications Table 6-29. Processor I/O Overshoot/Undershoot Specifications Minimum Undershoot Signal Group Intel QuickPath Interconnect Processor Asynchronous Sideband Signals System Reference Clock (BCLK{0/1}) Miscellaneous Signals PWRGOOD Signal Maximum Overshoot Overshoot Duration Undershoot Duration Notes -0.2 * VTT 1.2 * VTT 39 ps 15 ps 1,2 -0.35 * VTT 1.35 * VTT 1.25 ns 0.5 ns 1,2 N/A N/A 1,2 N/A N/A 4 -0.3V 1.15V -0.35*Vtt 1.35*Vtt -0.420V VTT + 0.
Processor Land Listing 7 Processor Land Listing This chapter provides sorted land list in Section 7.1 and Section 7.2. Table 7-1 is a listing of all Intel® Xeon® E7v2 processor lands ordered alphabetically by land name. Table 7-2 is a listing of all processor lands ordered by land number. 7.1 Listing by Land Name Table 7-1. Land Name (Sheet 1 of 50) Land Name BCLK0_DN Land No. AF46 Buffer Type CMOS Table 7-1. Directio n Land Name (Sheet 2 of 50) Land Name Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 3 of 50) Land No. Buffer Type Directio n Table 7-1. Land Name Land Name (Sheet 4 of 50) Land No.
Processor Land Listing Table 7-1. Land Name (Sheet 5 of 50) Land Name Land No. Buffer Type Directio n Table 7-1. Land Name (Sheet 6 of 50) Land Name Land No.
Processor Land Listing Table 7-1. Land Name (Sheet 7 of 50) Land Name Land No. Buffer Type Directio n Table 7-1. Land Name (Sheet 8 of 50) Land Name Land No.
Processor Land Listing Table 7-1. Land Name (Sheet 9 of 50) Land Name Land No. Buffer Type Directio n Table 7-1. Land Name (Sheet 10 of 50) Land Name Land No.
Processor Land Listing Table 7-1. Land Name (Sheet 11 of 50) Land Name Land No. Buffer Type Directio n Table 7-1. Land Name (Sheet 12 of 50) Land Name Land No.
Processor Land Listing Table 7-1. Land Name (Sheet 13 of 50) Land Name Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 14 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 15 of 50) Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 16 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 17 of 50) Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 18 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 19 of 50) Land No. Buffer Type Directio n Table 7-1. Land Name Land Name (Sheet 20 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 21 of 50) Land No. Buffer Type Directio n Table 7-1. Land Name Land Name (Sheet 22 of 50) Land No.
Processor Land Listing Table 7-1. Land Name (Sheet 23 of 50) Land Name Land No. Buffer Type Directio n Table 7-1. Land Name Land Name (Sheet 24 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 25 of 50) Land No. Buffer Type Directio n Table 7-1. Land Name (Sheet 26 of 50) Land Name Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 27 of 50) Land No. Buffer Type Directio n Table 7-1. Land Name (Sheet 28 of 50) Land Name Land No.
Processor Land Listing Table 7-1. Land Name (Sheet 29 of 50) Land Name Land No. Buffer Type Directio n Table 7-1. Land Name Land Name (Sheet 30 of 50) Land No.
Processor Land Listing Table 7-1. Land Name (Sheet 31 of 50) Land Name Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 32 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 33 of 50) Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 34 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 35 of 50) Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 36 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 37 of 50) Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 38 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 39 of 50) Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 40 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 41 of 50) Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 42 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 43 of 50) Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 44 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 45 of 50) Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 46 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 47 of 50) Land No. Buffer Type Table 7-1. Directio n Land Name Land Name (Sheet 48 of 50) Land No.
Processor Land Listing Table 7-1. Land Name Land Name (Sheet 49 of 50) Land No. Buffer Type Table 7-1. Directio n Land Name (Sheet 50 of 50) Land Name Land No.
Processor Land Listing 7.2 Listing by Land Number Table 7-2. Land Number (Sheet 1 of 50) Land No. Land Name Buffer Type Table 7-2. Land Number (Sheet 2 of 50) Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 3 of 50) Land Name Buffer Type Directio n Table 7-2. Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 5 of 50) Land Name Buffer Type Directio n Table 7-2. Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 7 of 50) Land Name Buffer Type Directio n Table 7-2. Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 9 of 50) Land Name AP46 RSVD AP48 VSS Buffer Type Directio n GND Table 7-2. Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 11 of 50) Land Name Buffer Type Directio n Table 7-2. Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 13 of 50) Land Name Buffer Type BB58 QPI1_DRX_DN[2] QPI BB6 VSS GND Table 7-2. Land Number (Sheet 14 of 50) Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 15 of 50) Land Name Buffer Type Table 7-2. Land Number (Sheet 16 of 50) Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 17 of 50) Land Name Buffer Type Table 7-2. Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 19 of 50) Land Name Buffer Type Table 7-2. Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 21 of 50) Land Name C25 VCC C3 RSVD Buffer Type Directio n PWR Table 7-2. Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 23 of 50) Land Name Buffer Type Table 7-2. Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 25 of 50) Land Name Buffer Type Table 7-2. Land Number (Sheet 26 of 50) Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 27 of 50) Land Name Buffer Type Table 7-2. Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 29 of 50) Land Name Buffer Type Table 7-2. Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 31 of 50) Land Name Buffer Type Directio n Table 7-2. Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 33 of 50) Land Name Buffer Type Table 7-2. Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 35 of 50) Land Name Buffer Type Table 7-2. Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 37 of 50) Land Name Buffer Type Table 7-2. Land Number (Sheet 38 of 50) Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 39 of 50) Land Name Buffer Type Table 7-2. Directio n Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 41 of 50) Land Name Buffer Type Directio n Table 7-2. Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 43 of 50) Land Name Buffer Type Directio n Table 7-2. Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 45 of 50) Land Name Buffer Type Directio n Table 7-2. Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 47 of 50) Land Name Buffer Type Directio n Table 7-2. Land No.
Processor Land Listing Table 7-2. Land No. Land Number (Sheet 49 of 50) Land Name Buffer Type Directio n Table 7-2. Land No.
Package Mechanical Specifications 8 Package Mechanical Specifications The Intel® Xeon® E7v2 processor is packaged in a Flip-Chip Land Grid Array (FCLGA10) package that interfaces with the baseboard via an LGA2011-1 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications 6. All drawing dimensions are in mm. 7. Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the Intel® Xeon® Processor E72800/4800/8800 v2 Processor Family Thermal/Mechanical Design Guide.
Package Mechanical Specifications Figure 8-2.
Package Mechanical Specifications Figure 8-3.
Package Mechanical Specifications 8.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Do not contact the Test Pad Area with conductive material. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 8-2 and Figure 8-3 for keep-out zones.
Package Mechanical Specifications 8.6 Processor Mass Specification The typical mass of the processor is currently up to 50 grams. This mass [weight] includes all the components that are included in the package. 8.7 Processor Materials Table 8-3 lists some of the package components and associated materials. Table 8-3. Processor Materials Component Material Integrated Heat Spreader (IHS) Nickel Plated Copper Substrate Halogen Free, Fiber Reinforced Resin Substrate Lands 8.
PIROM 9 PIROM 9.1 Processor Information ROM The Processor Information ROM (PIROM) is a memory device located on the processor and is accessible via the System Management Bus (SMBus) which contains information regarding the processor’s features. These features are listed in table 10.1.1 below. The PIROM resides in the lower half of the memory component (addresses 00 - 7Fh), which is permanently write-protected by Intel. The upper half comprises the Scratch EEPROM (addresses 80 - FFh). 9.1.
PIROM Offset/ Section # of Bits Function Notes Examples 28h 8 Core Voltage Tolerance, Low Allowable negative DC shift Two 4-bit hex digits (mV) 15h = 15mV1 29h 8 Reserved Reserved for future use 00h Processor Uncore Data 2A-2Bh 16 Maximum Intel QPI Link Transfer Rate Four 4-bit hex digits (in MT/s) 8000h = 8.000 GT/s1 2C-2Dh 16 Maximum PCIe Link Transfer Rate Four 4-bit hex digits (in MT/s) 8000h = 8.000 GT/s1 2E-31h 32 Intel QPI Version Number Four 8-bit ASCII Characters 01.
PIROM Offset/ Section # of Bits 76h 8 Function Notes Static Checksum Examples 1 byte checksum Add up by byte and take 2’s complement. Electronic Signature Coded binary N/A Electronic Signature Checksum 1 byte checksum Add up by byte and take 2’s complement. Other 77-7Eh 64 7Fh 8 1. Uses Binary Coded Decimal (BCD) translation. 9.1.
PIROM 9.2 SMBus Memory Component Addressing Of the addresses broadcast across the SMBus, the memory component claims those of the form “10100XXZb”. The “XX” bits are defined by pull-up and pull-down of the SKTID[1:0] pins. Note that SKTID[2] does not affect the SMBus address for the memory component.
PIROM Note: Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not rely on this model. 9.3.1 Header To maintain backward compatibility, the Header defines the starting address for each subsequent section of the PIROM. Software should check for the offset before reading data from a particular section of the ROM. Example: Code looking for the processor uncore data of a processor would read offset 05h to find a value of 29.
PIROM Offset: 03h Bit 7:0 Description Processor Data Address Byte pointer to the Processor Data section 00h: Processor Data section not present 01h - 0Dh: Reserved 0Eh: Processor Data section pointer value 0Fh-FFh: Reserved 9.3.1.4 PCDA: Processor Core Data Address This location provides the offset to the Processor Core Data Section. Writes to this register have no effect.
PIROM 9.3.1.7 PNDA: Part Number Data Address This location provides the offset to the Part Number Data Section. Writes to this register have no effect. Offset: 07h Bit Description 7:0 Part Number Data Address Byte pointer to the Part Number Data section 00h: Part Number Data section not present 01h - 52h: Reserved 53h: Part Number Data section pointer value 54h-FFh: Reserved 9.3.1.8 TRDA: Thermal Reference Data Address This location provides the offset to the Thermal Reference Data Section.
PIROM 9.3.1.10 ODA: Other Data Address This location provides the offset to the Other Data Section. Writes to this register have no effect. Offset: 0Ah Bit 7:0 Description Other Data Address Byte pointer to the Other Data section 00h: Other Data section not present 01h - 78h: Reserved 79h: Other Data section pointer value 7Ah- FFh: Reserved 9.3.1.11 RES1: Reserved 1 This location is reserved. Writes to this register have no effect.
PIROM Offset: 0Eh-13h Bit 47:40 Description Character 6 S-Spec or QDF character or 20h 00h-0FFh: ASCII character 39:32 Character 5 S-Spec or QDF character or 20h 00h-0FFh: ASCII character 31:24 Character 4 S-Spec or QDF character 00h-0FFh: ASCII character 23:16 Character 3 S-Spec or QDF character 00h-0FFh: ASCII character 15:8 Character 2 S-Spec or QDF character 00h-0FFh: ASCII character 7:0 Character 1 S-Spec or QDF character 00h-0FFh: ASCII character 9.3.2.
PIROM Offset: 15h Bit 9.3.2.4 Description 7:2 Number of cores 1:0 Number of threads per core SCS: System Clock Speed This location contains the system clock frequency information. Systems may need to read this offset to decide if all installed processors support the same system clock speed. The data provided is the speed, rounded to a whole number, and reflected in binary coded decimal. Writes to this register have no effect.
PIROM Offset: 1Bh-1Ch Bit 15:13 Description Reserved 00b-11b: Reserved 12:12 Processor Type 0b-1b: Processor Type 11:8 Processor Family 0h-Fh: Processor Family 7:4 Processor Model 0h-Fh: Processor Model 3:0 Processor Stepping 0h-Fh: Processor Stepping 9.3.3.2 RES3: Reserved 3 This locations are reserved. Writes to this register have no effect. Offset: 1Dh-1Eh Bit 15:0 Description RESERVED 0000h-FFFFh: Reserved 9.3.3.
PIROM Offset: 21h-22h Bit 15:0 Description Maximum P0 Core Frequency 0000h-FFFFh: MHz 9.3.3.5 MAXVID: Maximum Core VID This location contains the maximum Core VID (Voltage Identification) voltage that may be requested via the VID pins. This field, rounded to the next thousandth, is in mV and is reflected in binary coded decimal. Writes to this register have no effect. Example: A voltage of 1.350 V maximum core VID would contain 1350h.
PIROM 9.3.3.8 VTL: Core Voltage Tolerance, Low This location contains the maximum Core Voltage Tolerance DC offset low. This field, rounded to the next thousandth, is in mV and is reflected in binary coded decimal. Writes to this register have no effect. A value of FF indicates that this value is undetermined. Writes to this register have no effect. Example: 15 mV tolerance would be saved as 15h. Offset: 28h Bit 7:0 Description Core Voltage Tolerance, Low 00h-FFh: mV 9.3.3.
PIROM Example: The Intel® Xeon® E7 v2 processor supports a maximum PCIe link transfer rate of 8.0 GT/s. Therefore, offset 2Ah-2Bh has a value of 8000. Offset: 2Ch-2Dh Bit 15:0 Description Minimum Intel QPI Transfer Rate 0000h-FFFFh: MHz 9.3.4.3 QPIVN: Intel QPI Version Number The Intel QPI Version Number is provided as four 8-bit ASCII characters. Writes to this register have no effect. Example: The Intel® Xeon® E7 v2 processor supports Intel QPI Version Number 1.1.
PIROM Example: The Intel® Xeon® E7 v2 processor supports a maximum Intel SMI2 performance transfer rate of 2.666 GT/s. Therefore, offset 33h-34h has a value of 2666h. Offset: 33h-34h Bit 15:0 Description Maximum Intel SMI Transfer Rate 0000h-FFFFh: MHz 9.3.4.6 MAXSML: Maximum Intel SMI2 Lock Step Transfer Rate Systems may need to read this offset to decide on compatible processors and Intel C102/C104 Scalable Memory Buffer capabilities.
PIROM Offset: 39-4Ah Bit 15:0 Description MIN VSA VID 0000h-FFFFh: mV 9.3.4.9 RES4: Reserved 4 This location is reserved. Writes to this register have no effect. Offset: 3Bh-3Eh Bit 31:0 Description RESERVED 00000000h-FFFFFFFFh: Reserved 9.3.4.10 L2SIZE: L2 Cache Size This location contains the size of the level-two cache in kilobytes. Writes to this register have no effect. Data format is decimal. Example: The Intel® Xeon® E7 v2 processor has a 256K L2 cache.
PIROM Offset: 43h-44h Bit 15:0 Description Cache Voltage ID 0000h-FFFFh: mV 9.3.4.13 VTT: VTT This field contains the voltage requested for the Vtt pins. This field is in mV and is reflected in hex. Some systems read this offset to determine if all processors support the same default Vtt settings. Writes to this register have no effect. Example: A voltage of 1.000 VTT would contain an Offset 43-44h value of 1000h. Offset: 45-46h Bit 15:0 Description Cache Voltage Tolerance, High 0000h-FFFFh: mV 9.
PIROM Offset: 4Ch-4Fh Bit 31:24 Description Character 4 ASCII character or 20h 00h-0FFh: ASCII character 23:16 Character 3 ASCII character 00h-0FFh: ASCII character 15:8 Character 2 ASCII character 00h-0FFh: ASCII character 7:0 Character 1 ASCII character 00h-0FFh: ASCII character 9.3.5.2 Substrate Revision Software ID This location is a place holder for the Substrate Revision Software ID. Writes to this register have no effect.
PIROM Example: A processor with a part number of AT80604******** will have the following data found at offset 38-3Eh: 41h, 54h, 38h, 30h, 36h, 30h, 34h.
PIROM Offset: 5Bh=62h Bit 39:32 Description Character 5 ASCII character or 20h 00h-0FFh: ASCII character 31:24 Character 4 ASCII character 00h-0FFh: ASCII character 23:16 Character 3 ASCII character 00h-0FFh: ASCII character 15:8 Character 2 ASCII character 00h-0FFh: ASCII character 7:0 Character 1 ASCII character 00h-0FFh: ASCII character 9.3.6.3 RES7: Reserved 7 This location is reserved. Writes to this register have no effect.
PIROM Offset: 67h Bit 7:0 Description Thermal Calibration Offset 0000h-FFFFh: Reserved 9.3.7.3 TCASE: TCASE Maximum This location provides the maximum TCASE for the processor. The field reflects temperature in degrees Celsius in binary coded decimal format. The thermal specifications are specified at the case Integrated Heat Spreader (IHS). Writes to this register have no effect. Example: A temperature of 66 degrees C would contain a value of 66h.
PIROM 9.3.8.1 PCFF: Processor Core Feature Flags This location contains a copy of results in EDX[31:0] from Function 1 of the CPUID instruction. These details provide instruction and feature support by product family. Writes to this register have no effect. Example: A value of BFEBFBFFh can be found at offset 6C - 6Fh. Offset: 6Ch-6Fh Bit 31:0 Description Processor Core Feature Flags 00000000h-FFFFFFFFF: Feature Flags 9.3.8.
PIROM Bits are set when a feature is present, and cleared when they are not. 9.3.8.4 MPSUP: Multiprocessor Support This location contains 2 bits for representing the supported number of physical processors on the bus. These two bits are LSB aligned where 00b equates to nonscalable 2 socket (2S) operation, 01b to scalable 2 socket (S2S), 10 to scalable 4 socket (S4S), and scalable 8 socket (S8S). The Intel® Xeon® E7 v2 processor is a S2S, S4S, or S8S processor.
PIROM 9.3.8.7 STTCKS: Static Checksum This location provides the checksum of the static values per SKU. Writes to this register have no effect. Offset: 76h Bit 7:0 Description Static Checksum One-byte checksum of the Static Checksum 00h- FFh: See Section 9.3.10 for calculation of this value. 9.3.9 Electronic Signature This section contains a large reserved area, and items added after the original format for the Intel® Xeon® E7 v2 processor PIROM was set. 9.3.9.
PIROM Example: For a byte string of AA445Ch, the resulting checksum will be B6h.
PIROM 190 Intel® Xeon® Product 2800/4800/8800 v2 Product Family Datasheet Volume One, February 2014
