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Reference Number: 329595-002

Intel

Xeon

Processor E7 v2

2800/4800/8800 Product Family

Datasheet - Volume Two

March 2014

Summary of content (504 pages)

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Intel® Xeon® Processor E7 v2 2800/4800/8800 Product Family Datasheet - Volume Two March 2014 Reference Number: 329595-002
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents 1 Overview ................................................................................................................. 17 1.1 Introduction ..................................................................................................... 17 1.2 Terminology ..................................................................................................... 18 1.3 Related Documents ........................................................................................... 21 1.
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.6 iMC Interface ....................................................................................................37 4.6.1 HA to MC Interface .................................................................................37 4.6.2 Target Address Decode (TAD)...................................................................37 5 iMC Functional Description .......................................................................................39 5.1 Overview ............................................
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7.5 7.6 7.4.10 Intel SMI2 Half-Width Failover Mode ......................................................... 56 7.4.11 Memory Migration .................................................................................. 57 IIO RAS ........................................................................................................... 57 7.5.1 IIO RAS Overview .................................................................................. 57 7.5.2 IIO Module Error Reporting ...........................
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13.2 13.3 13.4 13.5 13.6 13.7 14 6 13.1.6 CCR ......................................................................................................86 13.1.7 CLSR.....................................................................................................86 13.1.8 PLAT .....................................................................................................87 13.1.9 HDR......................................................................................................87 13.1.
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14.2.15IOLIM ................................................................................................. 203 14.2.16SECSTS .............................................................................................. 204 14.2.17MBAS ................................................................................................. 205 14.2.18MLIM .................................................................................................. 206 14.2.19PBAS ...........................................
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14.3 8 14.2.71ERRCAPHDR......................................................................................... 252 14.2.72UNCERRSTS ......................................................................................... 252 14.2.73UNCERRMSK ........................................................................................ 253 14.2.74UNCERRSEV......................................................................................... 253 14.2.75CORERRSTS..............................................
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14.4 14.5 14.3.1 DMIVC0RCAP ....................................................................................... 299 14.3.2 DMIVC0RCTL ....................................................................................... 300 14.3.3 DMIVC0RSTS ....................................................................................... 301 14.3.4 DMIVC1RCAP ....................................................................................... 301 14.3.5 DMIVC1RCTL ..........................................
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14.6 10 14.5.1 CHANCNT ............................................................................................ 334 14.5.2 XFERCAP ............................................................................................. 335 14.5.3 GENCTRL ............................................................................................. 335 14.5.4 INTRCTRL ............................................................................................ 335 14.5.5 ATTNSTATUS .................................
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14.7 14.6.19MMCFG_LIMIT ..................................................................................... 362 14.6.20TSEG .................................................................................................. 363 14.6.21GENPROTRANGE[1:0]_BASE .................................................................. 363 14.6.22GENPROTRANGE[1:0]_LIMIT ................................................................. 364 14.6.23GENPROTRANGE2_BASE ......................................................
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14.8 12 14.7.14VTD[0:1]_PROT_LOW_MEM_BASE .......................................................... 412 14.7.15VTD[0:1]_PROT_LOW_MEM_LIMIT .......................................................... 412 14.7.16VTD[0:1]_PROT_HIGH_MEM_BASE ......................................................... 412 14.7.17VTD[0:1]_PROT_HIGH_MEM_LIMIT ......................................................... 413 14.7.18VTD[0:1]_INV_QUEUE_HEAD ................................................................. 413 14.7.
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14.9 14.8.39GSYSCTL............................................................................................. 448 14.8.40GFFERRST, GFNERRST .......................................................................... 448 14.8.41GNFERRST, GNNERRST ......................................................................... 449 14.8.42IRPP[0:1]ERRST................................................................................... 449 14.8.43IRPP[0:1]ERRCTL .....................................................
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.10 Device 5 Function 4 I/OxAPIC............................................................................ 489 14.10.1INDEX ................................................................................................. 490 14.10.2WINDOW ............................................................................................. 490 14.10.3EOI..................................................................................................... 490 14.10.4Device 5 Function 4 Window 0 ..................
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Revision History Doc ID Description Date 329595-001 Initial Release February 2014 329595-002 Added Chapters 12 through 15 February 2014 § Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014 15
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Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
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Overview 1 Overview 1.1 Introduction The Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family processors are the next generation of 64-bit, multi-core enterprise processors built on 22-nanometer process technology. The Intel Xeon processor E7 v2 product family implements multiple multi-threaded (two threads) cores based upon the Intel Xeon processor E7 v2 product family core design. A large, up to 37.5 MB, last-level cache (LLC) has been implemented to be shared across all active cores.
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Overview — One Intel® C102/C104 Scalable Memory Buffer per Intel SMI2 channel, with up to two DDR3 channels per Intel C102/C104 Scalable Memory Buffer and up to eight DDR3 channels per socket. — Supports 1067, 1333 and 1600 MT/s DDR3 frequencies. — Supports up to 3 DIMMs per DDR3 channel. — Supports 2 GB, 4 GB and 8 GB DRAM technologies • PCI Express* interfaces: Up to 32 lanes each operating at PCI Express 3.0 speed (PCIe* 3.0) and 4 lanes of DMI2/PCI Express 2.0 (PCIe* 2.0) interface.
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Overview Table 1-1. Processor Terminology (Sheet 2 of 4) Term Description Functional Operation Refers to the normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical, and thermal, are satisfied. GSSE Extension of the SSE/SSE2 (Streaming SIMD Extensions) floating point instruction set to 256b operands. ICU Instruction Cache Unit. Part of the Intel Xeon processor E7 v2 product family core architecture. IFU Instruction Fetch Unit.
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Overview Table 1-1. Processor Terminology (Sheet 3 of 4) Term 20 Description MLC Mid Level Cache NCTF Non-Critical to Function: NCTF locations are typically redundant ground or noncritical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. NEBS Network Equipment Building System. NEBS is the most common set of environmental design guidelines applied to telecommunications equipment in the United States.
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Overview Table 1-1. Processor Terminology (Sheet 4 of 4) Term Description Uncore The portion of the processor comprising the shared cache, iMC, HA, PCU, UBox, and Intel QPI link interface. Unit Interval Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If a number of edges are collected at instances t1, t2, tn,...., tk then the UI at instance “n” is defined as: UI 1.
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Overview Table 1-3. Public Specifications (Sheet 2 of 2) Document Document Number/ Location Intel® Trusted Execution Technology Software Development Guide 1.4 http://www.intel.com/technology/security/ State of Data The data contained within this document is preliminary. It is the most accurate information available by the publication date of this document. The information in this revision of the document is based on early data. Processor feature set and capabilities may change prior to production.
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The Processor Architecture Overview 2 The Processor Architecture Overview This section describes the key architecture features of the core and uncore modules of the Intel Xeon processor E7 v2 product family. Figure 2-1 shows a high level view of the processor integrating: • Multiple Intel Xeon processor E7-2800/4800/8800 v2 product family cores • Up to 3 Intel QPI interfaces • Up to 32 PCI Express* 3.0 lanes • 1 x4 DMI2/PCIe* 2.0 interface Figure 2-1.
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The Processor Architecture Overview 2.1.1 Frequency The processor cores are designed to run at a rated frequency and the architecture allows operating at lower frequencies in order to make appropriate power/performance trade-off. Along with the ability to slow down cores for power optimization, “Intel Turbo Boost Technology” allows the ability to increase a core’s speed to optimize single threaded applications. 2.1.
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The Processor Architecture Overview 2.2 Uncore Features This section describes key features supported by each of the uncore modules designed specifically for the server and workstation market space. Further details of the key modules is provided in subsequent chapters. 2.2.1 The Ring The processor implements a proprietary, ring topology, interconnect between the core and uncore elements as used by the Intel QPI interface.
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The Processor Architecture Overview Note that in a 2S configuration, if parallel Intel QPI ports are to be used, Port 2 cannot be used in the parallel topology. Only ports 0 and 1 support a parallel topology. The Intel Xeon processor E7 v2 product family supports 3 Intel QPI interfaces. Ports 0, 1 must always operate at the same link frequency, and link 2 can operate at its own supported link frequency. The supported link frequencies for top SKU processor is targeting 6.4, 7.2, and 8.0 GT/s.
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The Processor Architecture Overview • Home Snoop Protocol Support: The Home Agent implements Intel QPI v1.1 “home snoop protocol” by initiating snoops on behalf of the requestor. The HA also offers Opportunistic Snoop Broadcast to further optimize performance. • Directory Mode Support: The HA only operates in the directory mode. 2.2.
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The Processor Architecture Overview • PCI Express Interfaces: The I/O module incorporates PCI Express interface. The processor can support up to 32 lanes of PCI Express.
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Cbo Functional Description 3 Cbo Functional Description The Intel Xeon processor E7 v2 product family core to the last level cache (LLC) interface is managed by the LLC coherence unit (Cbo). The Cbo handles all core and PCIe to Intel QuickPath Interconnect messages and system interface logic. There is at most one Cbo per core in a given socket. The LLC is 20-ways associative, and is an inclusive cache for the mid level cache in the cores.
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Cbo Functional Description 3.2 Source Address Decoder Within the Cbo, requests go through the Source Address Decoder (SAD) at the same time that they are allocating into the TOR and are sent to the LLC. Non-LLC message class types go through the SAD when they are allocating into the TOR as well. The SAD receives the address, the address space, opcode, and a few other transaction details.
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Cbo Functional Description 3.2.2.2 IIO Address Decoders Although many of the address ranges for the IIO address decoders are now integrated into Cbo system address decoder, there are still significant portions of IIO address decoding logic that reside inside IIO. IIO Address decoders will provide protection, address translation and proper sub decoding to support IO related transactions. 3.2.3 SAD Address Spaces The memory address space primarily contains cache coherent DRAM.
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Cbo Functional Description 3.2.3.1 SAD Decoders and Priority There are a total of four types of decoders in the SAD. Each of them covers a different part of the address map. These decoders do sometimes overlap, with explicit priorities defined for the cases when matches in multiple decoders occur in parallel so that we can ensure no holes in the address map exist. Below are the four types of decoders in SAD: • DRAM decoders: These are the decoders used to program DRAM configuration in the system.
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Cbo Functional Description 3.2.6 TSEG Range (CSR_TSEG <= addr) The TSEG range is used to manage the SMM memory region for DMA accesses. The protection is done by the core (through SMRR) and the IIO (through registers) thus it is not the responsibility of the uncore Cbo SAD. 3.2.7 Configuration Address Space Configuration accesses to Uncore control registers are originally in the I/O address space. There is also a range for PCI Express* configuration registers access in the memory address space.
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Cbo Functional Description 3.3 Viral Support The Intel Xeon processor E7 v2 product family supports Viral mode of the operation where the processor report fatal error conditions by setting the viral bit in the Intel QPI header packets, as well as assertion of the Error pin on the processor package. The system wide attempt to detect viral error conditions is another way to improve on the data reliability and error containment.
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Home Agent Functional Description 4 Home Agent Functional Description The Intel Xeon processor E7 v2 product family supports up to two Home Agents (HA) on-die. The HA is responsible for handling all DRAM requests homed at its node. It accepts incoming home requests, snoop responses, and write back messages from the ring, and in turn it sends data, completion, and snoop packets to the ring. The aggregate of HAs enforce the memory coherency for the system.
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Home Agent Functional Description 4.1.3 Intel QPI Home Logic The home logic is responsible for detecting and resolving the coherency conflict and memory access ordering for memory accesses. 4.1.4 Home Agent Data Buffer (HADB) The HADB is a set of data buffers. It is a temporary storage for transferring the data between the ring and memory controller. It has 128 entries, one for each Home Tracker. 4.1.
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Home Agent Functional Description 4.6 iMC Interface The HA operates at the same frequency as Cbo in the uncore clock domain, whereas the iMC is operated at the fixed DRAM clock domain, called Dclock domain. The HA sends the DRAM reads, writes, and other commands to the MC interface. It receives the return data, completion, error signals, and other request and acknowledgements from the MC. 4.6.
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Home Agent Functional Description 38 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
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iMC Functional Description 5 iMC Functional Description 5.1 Overview The Intel Xeon processor E7 v2 product family implements two internal memory controllers (iMC). Each memory controller supports two Intel SMI 2 interfaces and two Intel C102/C104 Scalable Memory Buffer expansion per iMC. Intel C102/C104 Scalable Memory Buffer provides support for two DDR3 buses. Intel SMI 2 is the technology used covering communication across the iMC and Intel C102/C104 Scalable Memory Buffer silicon.
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iMC Functional Description Figure 5-1.
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iMC Functional Description In Intel Xeon processor E7 v2 product family channel 0 can be used to control two DDR3 DRAM channels behind the Intel SMI 2 bus in Sub channel lockstep mode, while Channel 2 controls two DRAM channels behind a second Intel SMI 2 bus. Each pair of channels (Channels 0&1, Channels 2&3) shares a Write Push Logic unit, while each channel has a Intel SMI 2 Retry buffer and a Intel SMI 2 Command Encoder.
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iMC Functional Description The memory address decoder supports channel and rank interleaving, several DIMM and DRAM device types, and both open and closed page optimized address mappings. There is a requirement that at each level of interleaving, the set of targets must each contribute an equal amount of memory. For example, 8 GB of system space can be 2way socket interleaved, and then 4-way channel interleaved on one socket and 2-way channel interleaved on the other.
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iMC Functional Description Execution of a single refresh is tRFC, and it takes 110 – 350 ns according to DDR3 density. iMC is equipped with CLTT temperature monitor and be able to issue auto refresh at the 2x rate (3.9 us). 5.3.3.1 Refresh Priorities There are 3 levels of refresh priorities 1. Opportunistic 2. High-priority 3. Panic The opportunistic refresh is executed when the scheduler thinks that it can issue it without a significant penalty.
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iMC Functional Description 44 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
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IIO Functional Description 6 IIO Functional Description 6.1 Integrated I/O Module Overview The IIO module provides: • x32 PCI Express interface for general purpose PCI Express devices at 3.
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IIO Functional Description • 2.5 GHz (1.0) and 5 GHz (2.0) and 8 GHz (3.0) • Full peer-to-peer support between PCI Express interfaces • Full support for software-initiated PCI Express power management • x8 Server I/O Module (SIOM) 6.1.2 Direct Media Interface (DMI2) Features • One x4 DMI 2.0 link interface supporting 2.5 GB/s/direction (PCIe physical layer) peak bandwidth • Can also operate as a x4 2.0 PCIe link 6.1.3 PCIe* 3.
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IIO Functional Description 6.2 PECI and JTAG 6.2.1 PECI PECI provides access to both DMI and PCIe CSRs. 6.2.2 JTAG 6.2.2.1 JTAG Configuration Register Access JTAG provides an access mechanism that allows a user to access any register in the IO module and PCH components connected to the processor via the DMI link. 6.2.2.2 JTAG Initiated Southbound Configuration Cycles The processor allows access to registers in other components in the system which are connected to the PCIe ports. 6.
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IIO Functional Description Figure 6-2. PCI Express Lane Partitioning Port 0 DMI / PCIe Port 2 PCIe Port 3 PCIe IOU2 IOU0 IOU1 Transaction Transaction Transaction Link Link Link Physical 6.3.3.1 Physical Physical 0...3 0...3 4...7 8...11 12...15 0...3 4...7 8...11 12...
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IIO Functional Description 6.3.4 Technologies Supported over PCI Express 6.3.4.1 3.0 Protocol Enhancements Supported enhancements are • Transaction Processing Hints (TPH) • Atomic Operation Completer Capability 6.3.5 32/64 Bit Addressing For inbound and outbound memory reads and writes, the IIO module supports the 64bit address format. If an outbound transaction’s address is less than 4 GB, the IIO module will issue the transaction with a 32-bit addressing format on PCI Express.
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IIO Functional Description 50 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
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Reliability, Availability, Serviceability, and Manageability 7 Reliability, Availability, Serviceability, and Manageability This chapter describes RASM (Reliability, Availability, Serviceability and Manageability) features of the Intel Xeon processor E7 v2 product family. RASM refers to feature sets that are associated with system robustness and is defined as follows: Reliability: System capability to detect errors, report errors, and correct errors.
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Reliability, Availability, Serviceability, and Manageability 7.1.1 Error Sources In general two kinds of errors could occur in a system - Hard Errors or Soft Errors. Hard Errors are caused by various sources of electrical noise or by electrical marginality of the physical links and power supplies. Hard errors generally manifest as ‘stuck-lane’ or ‘stuck-bit’. Note: Within the silicon, often “Hard Errors” are defined as permanent circuit level faults.
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Reliability, Availability, Serviceability, and Manageability mode all the UC errors are reported as ‘Fatal’, and lead to MCE1 (Machine Check Exception) which is an abort class exception resulting in system reset. Such errors are also called as DUE (Detected but Uncorrected Error). When the Intel Xeon processor E7 v2 product family is configured in Corrupt Data Containment mode and when certain types of UC error are detected, it does not lead to MCE (Machine Check Exception) at the time of detection.
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Reliability, Availability, Serviceability, and Manageability Several of the RASM features require BIOS/SMM and SW1 support. Therefore, system architects implementing RASM features are advised to comprehend software implications and any feature limitation due to a given software architecture. 7.2 Error Detection and Correction Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family incorporates error detection and correction logic within each module to meet the desired reliability requirements. 7.
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Reliability, Availability, Serviceability, and Manageability The expectation is that a system cold reset must be performed when a fatal error/viral condition is detected. 7.4 Memory RAS This chapter describes the Intel Xeon processor E7 v2 product family memory RAS features. 7.4.1 Features and Capabilities The memory controller implements several RAS features that provide increasing levels of reliability in exchange for certain system costs. 7.4.
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Reliability, Availability, Serviceability, and Manageability 7.4.4.2 Rank Sparing 7.4.4.2.1 Usage Rank sparing enables a failing rank to be replaced by ranks installed in an unused space. An unused spare rank on the channel can be used to copy the contents of a failing rank on that channel. Note: The iMC will not support sparing across sockets or SMI2 channels. 7.4.
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Reliability, Availability, Serviceability, and Manageability 7.4.11 Memory Migration The Intel Xeon processor E7 v2 product family will provide support for migration of memory to a spare FRU. Only one migration target in the system will be supported at a time which means that there will only be one master home and one slave home in the system. 7.5 IIO RAS 7.5.
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Reliability, Availability, Serviceability, and Manageability 7.5.2.1.3 Fatal Errors (Severity 2 Error) Fatal errors are uncorrectable error conditions which render the IO module hardware unreliable. For fatal error, inband reporting to the CPU is still possible. A reset may be required to return to reliable operation. 7.5.2.2 Inband Error Reporting Inband error reporting signals the system of a detected error via inband cycles. 7.5.2.2.1 IIO Viral Viral containment is now supported in the IIO.
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Reliability, Availability, Serviceability, and Manageability 7.5.3.3.1 PCIe Error Severity Mapping PCIe errors can be classified as two types: Uncorrectable errors and Correctable errors. Uncorrectable errors can further be classified as Fatal or Non-Fatal. This classification is compatible and mapped with IO module’s error classification: Correctable as Correctable, Non-Fatal as Recoverable, and Fatal as Fatal. 7.5.3.3.
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Reliability, Availability, Serviceability, and Manageability 60 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
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Reset Flow 8 Reset Flow This chapter describes the reset flow for the Intel Xeon processor E7 v2 product family as applicable to the platform. 8.1 Introduction The processor supports the following reset types: Cold Reset (also known as PowerOn Reset) and Warm Reset. The Cold Reset provides the baseline framework for the Warm Reset flow: in general, the flows are identical, except in cases where a particular step required for Cold Reset may be skipped. 8.1.
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Reset Flow 62 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
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Ubox Functional Description 9 Ubox Functional Description 9.1 Ubox Overview The UBOX is the piece of logic that deals with the non mainstream flows in the system. This includes transactions like the register accesses, interrupt flows, lock flows and events. The UBOX also serves as the coordination point for the PCU for power management flows. In addition, the UBOX houses co-ordination for the perfmon architecture, and also houses scratch pad registers and semaphore registers.
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Ubox Functional Description 9.4.2 TAP Access The TAP port into the socket will be a master on the message channel. Just like any other access, the TAP will be able to send in a transaction on the uncore and access any register in the uncore.
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PCU Functional Description 10 PCU Functional Description This chapter describes the PCU module features along with PECI interfaces in more detail. 10.1 Introduction Power and thermal management functions require the collection of inputs from a wide variety of sources on the platform. These sources could be dedicated sensors in the processor or a collection of microarchitectural events.
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PCU Functional Description Figure 10-1. Power and Thermal Management Architecture Overview 10.2 Platform Environment Control Interface (PECI) The Platform Environment Control Interface (PECI) uses a single wire for self-clocking and data transfer. The bus requires no additional control lines. PECI also includes variable data transfer rate established with every message. In this way, it is highly flexible even though underlying logic is simple.
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PCU Functional Description — Note that platform ‘power’ management includes monitoring and control for both the processor and DRAM subsystem to assist with data center power limiting. 10.2.1.1 Thermal Management Processor fan speed control is managed by comparing Digital Thermal Sensor (DTS) thermal readings acquired via PECI against the processor-specific fan speed control reference point, or TCONTROL. Both TCONTROL and DTS thermal readings are accessible via the processor PECI client.
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PCU Functional Description many operating conditions under which one or more cores in the processor would be capable of running at much higher frequency without exceeding the power related constraints for the part. Furthermore, there are cases that the processor could exceed its rated power without exceeding the cooling capability of the platform, for significant duration or infinitely. 10.6 DDR3 Power and Thermal Management 10.6.
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Performance Monitoring 11 Performance Monitoring This chapter will provide an overview of the Intel Xeon processor E7 v2 product family performance monitoring (perfmon) features and describe how the architecture works at a high level. 11.1 Terminology • UNIT: A UNIT means any non IA-Core unit supporting PerfMon including: Cbos, Home Agent (HA), Memory Controller (iMC), Intel QPI Agent, Ubox, and PCU.
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Performance Monitoring 70 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
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Registers Overview and Configuration Process 12 Registers Overview and Configuration Process This volume of the Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet documents a part of the Configuration Status Registers (CSRs) of each individual functional block in the uncore logic. Refer to Intel® Xeon® Processor E72800/4800/8800 v2 Product Family External Design Specification (EDS) for a complete CSRs.
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Registers Overview and Configuration Process Figure 12-1.
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Registers Overview and Configuration Process 12.1.2 Processor Uncore Devices (CPUBUSNO (1)) The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket. Bus number is derived by the max bus range setting and processor socket number. Figure 12-2.
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Registers Overview and Configuration Process • PCI Configuration Registers (CSRs): CSRs are chipset specific registers that are located in PCI defined address space. • Machine Specific Registers (MSRs): MSRs are machine specific registers that can be accessed by specific read and write instructions. MSRs are OS ring 0 and BIOS accessible. • Memory-mapped I/O registers: These registers are mapped into the system memory map as MMIO low or MMIO high.
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Registers Overview and Configuration Process Table 12-1.
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Registers Overview and Configuration Process Table 12-1.
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Registers Overview and Configuration Process Table 12-1. Functions specifically handled by the processor (Sheet 3 of 3) Register Group 12.2.1.
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Registers Overview and Configuration Process • Devices that are hidden from host configuration space via the DEVHIDE register are not hidden from the configuration space as seen from the JTAG/SMBus/PECI port of an IIO. All PCI devices are always visible via JTAG/SMBus/PECI. • Devices or functions when turned off are always hidden (and not programmable to be unhidden) from host configuration space and also from JTAG/SMBus/PECI.
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Registers Overview and Configuration Process 12.2.2 MSR Access Machine Specific Registers are architectural and accessed by using specific ReadMSR/WriteMSR instructions. MSRs are also accessible for Reads via PECI. MSRs are always accessed as a naturally aligned 4- or 8-byte quantity. 12.2.3 Memory-Mapped I/O Registers The PCI standard provides not only configuration space registers but also registers which reside in memory-mapped space.
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Registers Overview and Configuration Process Table 12-3. Register attribute definitions (Sheet 2 of 2) Attribute Description RW_LB Read/Write Lock Bypass: Similar to RW_L, these bits can be read and written by software. HW can make these bits “Read Only” via a separate configuration bit or other logic. However, RW_LB is a special case where the locking is controlled by the lock-bypass capability that is controlled by the lock-bypass enable bits.
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Registers Overview and Configuration Process 12.4 Notational Conventions 12.4.1 Socket ID In cases where the target is only 3 bits, NID[2] is assumed to be zero. Therefore, the socket ID will be NID[3,1:0]. 12.4.2 Hexadecimal and Binary Numbers Base 16 numbers are represented by a string of hexadecimal digits followed by the character H (for example, F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.
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Registers Overview and Configuration Process 82 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
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Processor Uncore Configuration Registers 13 Processor Uncore Configuration Registers This chapter contains the Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Processor Uncore Configuration Registers, including Intel® Integrated Memory Controller, R2PCIE, Intel® QuickPath Interconnect, Processor Utility Box (UBox) and Power Control Unit (PCU). 13.1 PCI Standard Registers Register name 13.1.
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Processor Uncore Configuration Registers 13.1.2 DID Type: Bus: Offset: CFG 1 0x2 PortID: N/A Device Identification Number (device_identification_number): 15:0 13.1.3 RO Varies Device ID values vary from function to function. Bits 15:8 are equal to 0xE. Refer to Table 12-1 for the DID of each device. PCICMD Type: Bus: Offset: CFG 1 0x4 PortID: Bit Attr Default 15:11 RV - N/A Description Reserved.
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Processor Uncore Configuration Registers 13.1.4 PCISTS Type: Bus: Offset: Bit CFG 1 0x6 Attr PortID: Default N/A Description Detected Parity Error (detected_parity_error): 15:15 RO 0x0 14:14 RO 0x0 This bit is set when the device receives a packet on the primary side with an uncorrectable data error including a packet with poison bit set or an uncorrectable address / control parity error. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register.
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Processor Uncore Configuration Registers 13.1.5 RID Type: Bus: Offset: CFG 1 0x8 Bit Attr PortID: N/A Default Description revision_id: 7:0 RO_V Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in any Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family function.
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Processor Uncore Configuration Registers 13.1.8 PLAT Type: Bus: Offset: CFG 1 0xd PortID: Bit Attr Default 7:0 RO 0x0 N/A Description Primary Latency Timer (primary_latency_timer): Not applicable to PCI Express. Hardwired to 00h. 13.1.
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Processor Uncore Configuration Registers 13.1.12 SDID Type: Bus: Offset: CFG 1 0x2e PortID: Bit Attr Default 15:0 RW_O 0x0 N/A Description Subsystem Device Identification Number (subsystem_device_identification_number): Assigned by the subsystem vendor to uniquely identify the subsystem 13.1.13 CAPPTR Type: Bus: Offset: CFG 1 0x34 PortID: Bit Attr Default 7:0 RO 0x40 N/A Description Capability Pointer (capability_pointer): Points to the first capability structure for the device. 13.
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Processor Uncore Configuration Registers 13.1.16 MINGNT Type: Bus: Offset: CFG 1 0x3e PortID: Bit Attr Default 7:0 RO 0x0 N/A Description Minimum Grant Value (mgv): Not applicable and hardwired to 0. 13.1.17 MAXLAT Type: Bus: Offset: CFG 1 0x3f PortID: Bit Attr Default 7:0 RO 0x0 N/A Description Maximum Latency Value (mlv): Not applicable and hardwired to 0. 13.
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Processor Uncore Configuration Registers Bus 1 13.2.1 Device 30 Function 6 7 2 3 Memory Channel Memory Memory Memory Memory Channel Channel Channel Channel 0 1 2 3 Comments iMC 1 Test Registers Device 15, 29 Function 0 The Device 15 and 29 Function 0 contains general and MemHot registers. The registers in Device 29 Function 0 are identical to those in Device 15 Function 0, respectively. The Device 15 registers address iMC 0, while the Device 29 registers address iMC 1.
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Processor Uncore Configuration Registers Register name Offset MCMTR2 0xb0 32 MC_INIT_STATE_G 0xb4 32 RCOMP_TIMER 13.2.1.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x40 Attr PortID: Device: Device: Default 15 29 N/A Function: Function: 0 0 Description Capability Version (capability_version): PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec. 19:16 RO 0x1 Note: This capability structure is not compliant with Versions beyond 1.0, since they require additional capability registers to be reserved.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x7c Attr PortID: Device: Device: Default N/A 15 Function: 29 Function: 0 0 Description CPGC_IOSAV (trng_mode): 11:10 RW_LB 0x0 00: IOSAV mode 01: CPGC Mode- Setting to be used post VMSE CMD training (including EV) 10: CPGC VMSE CMD training mode - Set until VMSE CMD (coarse/fine) bus is trained 11: Normal Mode Converged Pattern Generation and Checking (CPGC) is described in the System Agent BIOS specification.
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Processor Uncore Configuration Registers For 1-way interleave, channel 1-3 mirror pair: target list = <1,3,x,x>, TAD ways = “00” For 2-way interleave, 0-2 mirror pair and 1-3 mirror pair: target list = <0,1,2,3>, TAD ways = “01” For 1-way interleave, lockstep + mirroring, target list = <0,2,x,x>, TAD ways = “00” Type: Bus: Bus: Offset: Bit CFG PortID: 1 Device: 1 Device: 0x80, 0x84, 0x88, 0x8c, Attr Default N/A 15 Function: 0 29 Function: 0 0x90, 0x94, 0x98, 0x9c, 0xa0, 0xa4, 0xa8, 0xac Description TAD
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Processor Uncore Configuration Registers 13.2.1.4 MCMTR2 MC Memory Technology Register 2 Type: Bus: Bus: Offset: CFG 1 1 0xb0 PortID: Device: Device: Bit Attr Default 31:4 RV - N/A 15 Function: 29 Function: 0 0 Description Reserved. MONROE_CHN_FORCE_SR (monroe_chn_force_sr): 3:0 13.2.1.5 RW_L 0x0 Monroe Technology software channel force SRcontrol. When set, the corresponding channel is ignoring the ForceSRExit. A new transaction arrive at this channel will still cause the SR exit.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0xb4 Attr PortID: Device: Device: Default N/A 15 Function: 29 Function: 0 0 Description DDRIO Reset (internal logic) (reset_io): 5:5 RW_L 0x1 Training Reset for DDRIO. It resets TX/RX FIFO pointers, and some read related FSMs inside MCIO. It goes to both the left and right DDRIO blocks on MC on only the left side DDRIO block on Intel Xeon processor E7 v2 Series-based platform.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: CFG 1 1 0xc0 PortID: Device: Device: Bit Attr Default 21:21 RW 0x0 N/A 15 Function: 29 Function: 0 0 Description ignore_mdll_locked_bit: Ignore DDRIO MDLL lock status during rcomp when set no_mdll_fsm_override: 20:20 RW 0x0 19:17 RV - Do not force DDRIO MDLL on during rcomp when set Reserved.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: CFG 1 1 0x104 PortID: Device: Device: Bit Attr Default 17:17 RW 0x0 N/A 15 Function: 29 Function: 0 0 Description MHOT_EXT_SMI_EN (mhot_ext_smi_en): Generate SMI event when either MEM_HOT[1:0]# is externally asserted. Enabling external MEM_HOT sensing logic (mh_sense_en): 16:16 RW 0x0 Externally asserted MEM_HOT sense control enable bit. When set, the MEM_HOT sense logic is enabled.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x10c Attr Default PortID: Device: Device: N/A 15 Function: 29 Function: 0 0 Description CNFG_500_NANOSEC (cnfg_500_nanosec): 500 ns equivalent in DCLK. BIOS calculate number of DCLK to be equivalent to 500 nanoseconds. This value is loaded into CNTR_500_NANOSEC when it is decremented to zero. For presilicon validation, minimum 2 can be set to speed up the simulation. 9:0 13.2.1.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x118 Attr PortID: Device: Device: Default N/A 15 Function: 29 Function: 0 0 Description MH1_IO_CNTR (mh1_io_cntr): 31:22 RW_LV 0x0 MEM_HOT[1:0]# Input Output Counter in number of CNTR_500_NANOSEC. When MH_IO_CNTR is zero, the counter is loaded with MH_SENSE_PERIOD in the next CNTR_500_NANOSEC.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x11c Attr PortID: Device: Device: Default N/A 15 Function: 29 Function: 0 0 Description MH1_1ST_CHN_ASTN (mh1_1st_chn_astn): 19:16 RO 0xa 15:8 RV - MemHot[1]# 1st Channel Association bit 19: is valid bit. Note: Valid bit means the association is valid and it does not implies the channel is populated. bit 18-16: 1st channel ID within this MEMHOT domain Note: This register is hardcoded in design.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x120 Attr PortID: Device: Device: Default N/A 15 Function: 29 Function: 0 0 Description MH1_DIMM_CID (mh1_dimm_cid): 30:28 RW 0x0 Hottest DIMM Channel ID for MEM_HOT[1]#. PCU microcode search the hottest DIMM temperature and write the hottest temperature and the corresponding Hottest DIMM CID/ID. 000 - Channel0 001 - Channel1 010 - Channel2 011 - Channel3 100- 111 Reserved.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x120 Attr PortID: Device: Device: Default N/A 15 Function: 29 Function: 0 0 Description MH0_DIMM_ID (mh0_dimm_id): 11:8 RW 0x0 Hottest DIMM ID for MEM_HOT[0]#. PCU microcode search the hottest DIMM temperature and write the hottest temperature and the corresponding Hottest DIMM CID/ID. 000 - DIMM0 001 - DIMM1 010 - DIMM2 011- 111 Reserved. MH0_TEMP (mh0_temp): 7:0 13.2.1.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG PortID: 1 Device: 1 Device: 0x180, 0x190 Attr Default N/A 15 Function: 29 Function: 0 0 Description SMB_RDO (smb_rdo): 31:31 RO_V 0x0 Read Data Valid This bit is set by iMC when the Data field of this register receives read data from the SPD/TSOD after completion of an SMBus read command. It is cleared by iMC when a subsequent SMBus read command is issued.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG PortID: 1 Device: 1 Device: 0x180, 0x190 Attr Default N/A 15 Function: 29 Function: 0 0 Description Last Issued TSOD Slave Address (tsod_sa): This field captures the last issued TSOD slave address.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG PortID: 1 Device: 1 Device: 0x184, 0x194 Attr Default N/A 15 Function: 29 Function: 0 0 Description SMB_PNTR_SEL (smb_pntr_sel): 30:30 RWS 0x0 Pointer Selection: SMBus/I2C present pointer based access enable when set; otherwise, use random access protocol. Hardware based TSOD polling will also use this bit to enable the pointer word read.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG PortID: 1 Device: 1 Device: 0x188, 0x198 Attr Default N/A 15 Function: 29 Function: 0 0 Description SMB_DTI (smb_dti): 31:28 RWS 0xa Device Type Identifier: This field specifies the device type identifier. Only devices with this device-type will respond to commands. '0011' specifies TSOD. '1010' specifies EEPROM's. '0110' specifies a write-protect operation for an EEPROM.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG PortID: 1 Device: 1 Device: 0x188, 0x198 Attr Default N/A 15 Function: 29 Function: 0 0 Description SMB_SOFT_RST (smb_soft_rst): SMBus software reset strobe to graceful terminate pending transaction (after ACK) and keep the SMB from issuing any transaction until this bit is cleared.
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Processor Uncore Configuration Registers 13.2.1.19 SMB_PERIOD_CFG SMBus Clock Period Config. Type: Bus: Bus: Offset: CFG 1 1 0x1a0 Bit Attr Default 31:16 RV - PortID: Device: Device: N/A 15 Function: 29 Function: 0 0 Description Reserved1: Reserved SMB_CLK_PRD (smb_clk_prd): 15:0 RWS 0xfa0 This field specifies both SMBus Clock in number of DCLK. Note: In order to generate a 50% duty cycle SCL, half of the SMB_CLK_PRD is used to generate SCL high.
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Processor Uncore Configuration Registers 13.2.2 Device 15, 29 Function 1 The Device 15 and 29 Function 1 contain the extended and RAS registers. The registers in Device 29 Function 1 are identical to those in Device 15 Function 1, respectively. The Device 15 registers address iMC 0, while the Device 29 registers address iMC 1. Register name 13.2.2.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: CFG 1 1 0x40 PortID: Device: Device: Bit Attr Default 29:25 RO 0x0 N/A 15 Function: 29 Function: 1 1 Description Interrupt Message Number (interrupt_message_number): N/A for this device Slot Implemented (slot_implemented): 24:24 RO 0x0 N/A for integrated endpoints Device/Port Type (device_port_type): 23:20 RO 0x9 Device type is Root Complex Integrated Endpoint Capability Version (capability_version): PCI Express Capability is
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Processor Uncore Configuration Registers 13.2.2.3 SPARECTL Type: Bus: Bus: Offset: CFG 1 1 0x90 PortID: Device: Device: N/A 15 Function: 29 Function: Bit Attr Default Description 31:30 RV 0x0 Reserved. 1 1 DisWPQWM (diswpqwm): Disable WPQ level based water mark, so that sparing wm is only based on HaFifoWM.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x90 Attr PortID: Device: Device: Default N/A 15 Function: 29 Function: 1 1 Description CHANNEL SELECT FOR THE SPARE COPY (chn_sel): Since there is only one spare-copy logic for all channels, this field selects the channel or channel-pair for the spare-copy operation.
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Processor Uncore Configuration Registers 13.2.2.5 SCRUBADDRESSLO Scrub Address Low. This register contains part of the address of the last patrol scrub request issued. When running memtest, the failing address is logged in this register on memtest errors. Software can write the next address to be scrubbed into this register. The STARTSCRUB bit will then trigger the specified address to be scrubbed. Patrol scrubs must be disabled to reliably write this register.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: CFG 1 1 0xa0 PortID: Device: Device: Bit Attr Default 31:31 RW_L 0x0 N/A 15 Function: 29 Function: 1 1 Description Scrub Enable (scrub_en): Scrub Enable when set. Stop on complete (stop_on_cmpl): 30:30 RW 0x0 Stop patrol scrub at end of memory range. This mode is meant to be used as part of memory migration flow.
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Processor Uncore Configuration Registers 13.2.2.8 SPAREINTERVAL Defines the interval between normal and sparing operations. Interval is defined in dclk. Type: Bus: Bus: Offset: CFG 1 1 0xa8 PortID: Device: Device: Bit Attr Default 31:29 RV - N/A 15 Function: 29 Function: 1 1 Description Reserved. NUMSPARE (numspare): 28:16 RW 0x320 15:0 RW 0xc80 Sparing operation duration. System requests will be blocked during this interval and only sparing copy operations will be serviced.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: CFG 1 1 0xb4 PortID: Device: Device: Bit Attr Default 15:15 RW 0x0 N/A 15 Function: 29 Function: 1 1 Description INTRPT_SEL_SMI (intrpt_sel_smi): SMI enable. Set to enable SMI signaling. Clear to disable SMI signaling. 14:0 13.2.2.11 RV - Reserved. LEAKY_BUCKET_CFG The leaky bucket is implemented as a 53-bit DCLK counter.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0xb8 Attr PortID: Device: Device: Default N/A 15 Function: 29 Function: 1 1 Description LEAKY_BKT_CFG_HI (leaky_bkt_cfg_hi): 11:6 RW 0x0 This is the higher order bit select mask of the two hot encoding threshold. The value of this field specify the bit position of the mask: 00h: reserved 01h: LEAKY_BUCKET_CNTR_LO bit 1, i.e. bit 12 of the full 53b counter ... 1Fh: LEAKY_BUCKET_CNTR_LO bit 31, i.e.
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Processor Uncore Configuration Registers 13.2.2.13 LEAKY_BUCKET_CNTR_HI Type: Bus: Bus: Offset: CFG 1 1 0xc4 PortID: Device: Device: N/A 15 Function: 29 Function: Bit Attr Default Description 31:10 RV - Reserved. 1 1 Leaky Bucket Counter High Limit (leaky_bkt_cntr_hi): 9:0 13.2.3 RW_V 0x0 This is the upper 10-bit of the leaky bucket counter. The full counter is actually a 53b “DCLK” counter. There is a least significant 11b of the 53b counter is not captured in CSR.
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Processor Uncore Configuration Registers Register name 13.2.3.1 Offset Size DIMMMTR_2 0x88 32 PXPENHCAP 0x100 32 PXPCAP Type: Bus: Bus: Offset: CFG 1 1 0x40 PortID: Device: Device: N/A 15 Function: 29 Function: Bit Attr Default Description 31:30 RV - Reserved.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG PortID: 1 Device: 1 Device: 0x80, 0x84, 0x88 Attr Default N/A 15 Function: 29 Function: 2,3,4,5 2,3,4,5 Description RANK_DISABLE control (rank_disable): RANK Disable Control to disable patrol, refresh and ZQCAL operation. This bit setting must be set consistently with TERM_RNK_MSK, i.e. both corresponding bits cannot be set at the same time. In the other word, a disabled rank must not be selected for the termination rank.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG PortID: 1 Device: 1 Device: 0x80, 0x84, 0x88 Attr Default N/A 15 Function: 29 Function: 2,3,4,5 2,3,4,5 Description RA_WIDTH (ra_width): 4:2 RW_LB 0x0 000 - Reserved 001 - Reserved 010 - 14 bits 011 - 15 bits 100 - 16 bits 101 - 17 bits HDRL, if DISABLE_EXTENDED_ADDR_DIMM is 1, setting 101 is decoded as 100..
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Processor Uncore Configuration Registers Register Name Offset Size PCICMD 0x4 16 PCISTS 0x6 16 RID 0x8 8 CCR 0x9 24 CLSR 0xc 8 PLAT 0xd 8 HDR 0xe 8 BIST 0xf 8 SVID 0x2c 16 SDID 0x2e 16 CAPPTR 0x34 8 INTL 0x3c 8 INTPIN 0x3d 8 MINGNT 0x3e 8 MAXLAT 0x3f 8 PXPCAP 0x40 32 PMONCNTR_0 0xa0 64 PMONCNTR_1 0xa8 64 PMONCNTR_2 0xb0 64 PMONCNTR_3 0xb8 64 PMONCNTR_4 0xc0 64 PMONCNTR_FIXED 0xd0 64 PMONCNTRCFG_0 0xd8 32 PMONCNTRCFG_1 0xdc 32 PMONCN
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Processor Uncore Configuration Registers Register Name Offset Size PCICMD 0x4 16 PCISTS 0x6 16 RID 0x8 8 CCR 0x9 24 CLSR 0xc 8 PLAT 0xd 8 HDR 0xe 8 BIST 0xf 8 SVID 0x2c 16 SDID 0x2e 16 CAPPTR 0x34 8 INTL 0x3c 8 INTPIN 0x3d 8 MINGNT 0x3e 8 MAXLAT 0x3f 8 PXPCAP 0x40 32 PMONCNTR_0 0xa0 64 PMONCNTR_1 0xa8 64 PMONCNTR_2 0xb0 64 PMONCNTR_3 0xb8 64 PMONCNTR_4 0xc0 64 PMONCNTR_FIXED 0xd0 64 PMONCNTRCFG_0 0xd8 32 PMONCNTRCFG_1 0xdc 32 PMONCN
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Processor Uncore Configuration Registers Register Name 13.2.4.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x40 Attr PortID: Device: Device: Default N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description Capability Version (capability_version): PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec. 19:16 RO 0x1 Note: This capability structure is not compliant with Versions beyond 1.0, since they require additional capability registers to be reserved.
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Processor Uncore Configuration Registers 13.2.4.4 PMONCNTRCFG_[0:4] Perfmon Counter Control Register Type: Bus: Bus: Offset: Bit CFG 1 1 0xd8 Attr PortID: N/A Device: 16 Function: Device: 30 Function: , 0xdc, 0xe0, 0xe4, 0xe8 Default 0,1,4,5 0,1,4,5 Description Threshold (threshold): 31:24 RW_V 0x0 This field is compared directly against an incoming event value for events that can increment by 1 or more in a given cycle.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0xd8 PortID: N/A Device: 16 Function: Device: 30 Function: , 0xdc, 0xe0, 0xe4, 0xe8 Attr Default 0,1,4,5 0,1,4,5 Description Counter Reset (counterreset): 17:17 WO 0x0 When this bit is set, the corresponding counter will be reset to 0. This allows for a quick reset of the counter when changing event encodings.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0xf4 Attr PortID: Device: Device: Default N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description Reset Counter Configs (resetcounterconfigs): 0:0 13.2.4.6 WO 0x0 When this bit is written to, the counter configuration registers will be reset. This does not effect the values in the counters. PMONUNITSTATUS This field shows which registers have overflowed in the unit.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x100 Attr PortID: Device: Device: Default N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description Next Capability Offset (next_capability_offset): 31:20 RO 0x0 19:16 RO 0x1 Indicates there are no capability structures in the enhanced configuration space. Capability Version (capability_version): Capability Version. Capability ID (capability_id): 15:0 RO 0xb Capability ID. 13.2.4.
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Processor Uncore Configuration Registers 13.2.4.9 CHN_TEMP_STAT Type: Bus: Bus: Offset: CFG 1 1 0x10c PortID: Device: Device: Bit Attr Default 31:4 RV - N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description Reserved.
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Processor Uncore Configuration Registers 13.2.4.11 DIMM_TEMP_TH_[0:2] Type: Bus: Bus: Offset: CFG 1 1 0x120, 0x124, Bit Attr Default 31:27 RV - PortID: Device: Device: 0x128 N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description Reserved. TEMP_THRT_HYST (temp_thrt_hyst): 26:24 RW 0x0 Positive going Threshold Hysteresis Value. Set to 00h if sensor does not support positive-going threshold hysteresis.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x130, 0x134, Attr Default PortID: Device: Device: 0x138 N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description THRT_CRIT (thrt_crit): 23:16 RW 0x0 15:8 RW 0xf Max number of throttled transactions (ACT, READ, WRITE) to be issued during BWLIMITTF. THRT_HI (thrt_hi): Max number of throttled transactions (ACT, READ, WRITE) to be issued during BWLIMITTF. THRT_MID (thrt_mid): 7:0 13.2.4.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: CFG 1 1 0x140, 0x144, Bit Attr Default 10:10 RW 0x0 PortID: Device: Device: 0x148 N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description Assert MEMHOT Event on TEMPLO (ev_mh_templo_en): Assert MEMHOT# Event on TEMPLO Assert MEMHOT Event on TEMPOEMHI (ev_mh_tempoemhi_en): 9:9 RW 0x0 Assert MEMHOT# Event on TEMPOEMHI Assert MEMHOT Event on TEMPOEMLO (ev_mh_tempoemlo_en): 8:8 RW 0x0 Assert MEMHOT# Event on TEMPOEMLO 7:4 RV
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x150 Attr PortID: Device: Device: , 0x154, Default N/A 16 Function: 30 Function: 0x158 0,1,4,5 0,1,4,5 Description Event Asserted on TEMPOEMHI Going High (ev_asrt_tempoemhi): 24:24 RW1C 0x0 Event Asserted on TEMPOEMHI Going High It is assumed that each of the event assertion is going to trigger Configurable interrupt (Either MEMHOT# only or both SMI and MEMHOT#) defined in bit 30 of CHN_TEMP_CFG 23:8 RV - Reserved.
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Processor Uncore Configuration Registers 13.2.4.16 TCDBP Timing Constraints DDR3 Bin Parameter. Type: Bus: Bus: Offset: 13.2.4.17 CFG 1 1 0x200 Bit Attr 31:27 26:26 PortID: Device: Device: N/A 16 Function: 30 Function: Default Description RV - Reserved.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x204 Attr PortID: Device: Default N/A 16 Function: Device: 0,1,4,5 30Function:0,1,4,5 Description T_WTR (t_wtr): DCLK delay from start of internal write transaction to internal read command (must be at least the larger value of 4 DCLK or 7.5ns) iMC's Write to Read Same Rank (T_WRSR) is automatically calculated based from TCDBP.T_CWL + 4 + T_WTR.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x208 Attr PortID: Device: Device: Default N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description T_RWSR (t_rwsr): 26:24 RW 0x2 This field is used as read ODT delay bits 2:0 in Intel® Xeon® Processor E72800/4800/8800 v2 Product Family. Refer to TCOTHP2 for the new register field location for T_RWSR. T_WRDD (t_wrdd): 23:21 RW 0x2 Back to back WRITE to READ from different DIMM separation parameter.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x208 Attr PortID: Device: Device: Default N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description T_RRDD (t_rrdd): 5:3 RW 0x2 Back to back READ to READ from different DIMM separation parameter. The actual READ to READ command separation is TRRDD + 5 DCLKs measured between the clock assertion edges of the two corresponding asserted command CS#.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x20c Attr PortID: Device: Device: Default N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description T_CWL_ADJ (t_cwl_adj): 10:8 RW 0x0 7:5 RW 0x3 This register defines additional WR data delay per channel in order to overcome the WR-flyby issue. The total CAS write latency that the DDR sees is the sum of T_CWL and the T_CWL_ADJ.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x214 Attr PortID: Device: Device: Default N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description T_REFIX9 (t_refix9): 31:25 RW 0x9 period of min between 9 * T_REFI and tRAS maximum (normally 70 micro-sec) in 1024 * DCLK cycles.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x218 Attr PortID: Device: Device: Default N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description T_XSDLL (t_xsdll): 11:0 13.2.4.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: CFG 1 1 0x21c PortID: Device: Device: N/A 16 Function: 30 Function: Bit Attr Default Description 7:6 RV - Reserved. 5:0 RW 0x18 0,1,4,5 0,1,4,5 MR2_SHDW_A5TO0 (mr2_shdw_a5to0): Copy of MR2 A[5:0] shadow 13.2.4.24 TCZQCAL Timing Constraints ZQ Calibration Timing Parameter.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: CFG 1 1 0x22c PortID: Device: Device: N/A 16 Function: 30 Function: Bit Attr Default Description 31:12 RV - Reserved. 0,1,4,5 0,1,4,5 MR0_SHADOW (mr0_shadow): 11:0 13.2.4.27 RW 0x0 BIOS program this field for MR0 register A11:A0 for all DIMMs in this channel. iMC hardware is dynamically issuing MRS to MR0 to control the fast and slow exit PPD (MRS MR0 A12). Other address bits (A[11:0]) is defined by this register field.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x238 Attr Default PortID: Device: Device: N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description ADAPT_PG_CLSE (adapt_pg_clse): 28:28 RW 0x1 This register is programmed in conjunction with MCMTR.CLOSEPG to enable three different modes: 1: Closed Page Mode = Mode -1 MCMTR.CLOSE_PG = 1 and ADAPT_PG_CLSE = 0 2: Open Page Mode = Mode -1 MCMTR.CLOSE_PG = 0 and ADAPT_PG_CLSE = 0 3: Adaptive Open = Open -1 MCMTR.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x23c Attr Default PortID: Device: Device: N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description T_STAB (t_stab): Stabilizing time in number of DCLK, i.e. the DCLK must be stable for T_STAB before any access to the device take place. We have included tCKSRX in the T_STAB programming since processor does not have separate tCKSRX parameter control to delay self-refresh exit latency from clock stopped conditions.
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Processor Uncore Configuration Registers 13.2.4.31 TCMRS Type: Bus: Bus: Offset: CFG 1 1 0x244 Bit Attr Default 31:4 RV - PortID: Device: Device: N/A 16 Function: 30 Function: 0,1,4,5 0,1,4,5 Description Reserved. TMRD_DDR3 (tmrd_ddr3): 3:0 RW 0x8 DDR3 tMRD timing parameter. MRS to MRS minimum delay in number of DCLK. 13.2.4.32 MC_INIT_STAT_C State register per channel. Sets control signals static values. Power-up default is state 0x0 set by global reset.
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Processor Uncore Configuration Registers Register Name 13.2.5.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x40 Attr PortID: Device: Device: Default N/A 16 Function: 30 Function: 2,3,6,7 2,3,6,7 Description Capability Version (capability_version): PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec. 19:16 RO 0x1 Note: This capability structure is not compliant with Versions beyond 1.0, since they require additional capability registers to be reserved.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x104 Attr Default PortID: Device: Device: N/A 16 Function: 30 Function: 2,3,6,7 2,3,6,7 Description RANK 1 CORRECTABLE ERROR COUNT (cor_err_cnt_1): 30:16 RWS_V 0x0 15:15 RW1CS 0x0 The corrected error count for this rank. Hardware automatically clears this field when the corresponding OVERFLOW_x bit is changing from 0 to 1. RANK 0 OVERFLOW (overflow_0): The corrected error count for this rank has been overflowed.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: CFG 1 1 0x10c Bit Attr Default 30:16 RWS_V 0x0 PortID: Device: Device: N/A 16 Function: 30 Function: 2,3,6,7 2,3,6,7 Description RANK 5 COR_ERR_CNT (cor_err_cnt_5): The corrected error count for this rank. RANK 4 OVERFLOW (overflow_4): 15:15 RW1CS 0x0 14:0 RWS_V 0x0 The corrected error count has crested over the limit for this rank. Once set it can only be cleared via a write from BIOS.
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Processor Uncore Configuration Registers Type: Bus: Bus: Offset: Bit CFG 1 1 0x11c Attr Default PortID: Device: Device: N/A 16 Function: 30 Function: 2,3,6,7 2,3,6,7 Description RANK 0 COR_ERR_TH (cor_err_th_0): 14:0 13.2.5.8 RW 0x7fff The corrected error threshold for this rank that will be compared to the per rank corrected error counter. CORRERRTHRSHLD_1 This register holds the per rank corrected error thresholding value.
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Processor Uncore Configuration Registers 13.2.5.10 CORRERRTHRSHLD_3 This register holds the per rank corrected error thresholding value. Type: Bus: Bus: Offset: CFG 1 1 0x128 PortID: Device: Device: N/A 16 Function: 30 Function: Bit Attr Default Description 31:31 RV - Reserved. 2,3,6,7 2,3,6,7 RANK 7 COR_ERR_TH (cor_err_th_7): 30:16 RW 0x7fff 15:15 RV - The corrected error threshold for this rank that will be compared to the per rank corrected error counter. Reserved.
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Processor Uncore Configuration Registers 13.2.5.12 LEAKY_BKT_2ND_CNTR_REG Type: Bus: Bus: Offset: Bit CFG 1 1 0x138 Attr PortID: Device: Device: Default N/A 16 Function: 30 Function: 2,3,6,7 2,3,6,7 Description LEAKY_BKT_2ND_CNTR_LIMIT (leaky_bkt_2nd_cntr_limit): Secondary Leaky Bucket Counter Limit (2b per DIMM). This register defines secondary leaky bucket counter limit for all 8 logical ranks within channel.
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Processor Uncore Configuration Registers For lock-step channel configuration, only one x8 device can be tagged per rank-pair. SMM software must copy the faildevice log from Channel 0/2 to the corresponding register in Channel 1/3, then set EN for both channels in lockstepped pair. There is no hardware logic to report incorrect programming error. Unpredictable error and / or silent data corruption will be the consequence of such programming error.
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Processor Uncore Configuration Registers Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family has two Home Agents: HA0 and HA1. Device 14 registers address HA0, while Device 28 registers address HA1. The registers in Device 14 and Device 28 are identical. 13.3.1 Device 14, 28 Function 0 Register name 13.3.1.
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Processor Uncore Configuration Registers 13.4 PCIe* Ring Interface (R2PCIE) Registers 13.4.1 Device 19 Function 0 Register name 13.
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Processor Uncore Configuration Registers Register name 13.5.1.1 Offset Size Device CAPPTR 0x34 8 8, 9, 24 INTL 0x3c 8 8, 9, 24 INTPIN 0x3d 8 8, 9, 24 MINGNT 0x3e 8 8, 9, 24 MAXLAT 0x3f 8 8, 9, 24 QPIMISCSTAT 0xd4 32 8, 9, 24 QPIMISCSTAT Intel® QPI MISC Status. This is a status register for Common logic in Intel® QPI.
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Processor Uncore Configuration Registers Register name Offset Size MINGNT 0x3e 8 MAXLAT 0x3f 8 PXPCAP 13.5.2.1 0x40 32 PXPENHCAP 0x100 32 FWDC_LCPKAMP_CFG 0x390 32 PXPCAP Type: Bus: Bus: Bus: Offset: CFG 1 1 1 0x40 PortID: Device: Device: Device: N/A 8 Function: 9 Function: 24 Function: Bit Attr Default Description 31:30 RV - reserved.
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Processor Uncore Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 1 1 1 0x100 Attr PortID: Device: Device: Device: Default N/A 8 Function: 9 Function: 24 Function: 4 4 4 Description next_capability_offset: 31:20 RO 0x0 19:16 RO 0x1 Indicates there are no capability structures in the enhanced configuration space. capability_version: Capability Version. capability_id: 15:0 RO 0xb Capability ID. 13.5.2.
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Processor Uncore Configuration Registers 13.6.1 Device 11 Function 0 Register name 13.6.1.
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Processor Uncore Configuration Registers Type: Bus: Offset: CFG 1 0x40 PortID: Device: Bit Attr Default 2:0 RW_LB 0x0 N/A 11 Function: 0 Description NodeId of the local register (LclNodeId): Node Id of the local Socket 13.6.1.2 INTCONTROL Interrupt Configuration Register Type: Bus: Offset: CFG 1 0x48 PortID: Device: N/A 11 Function: Bit Attr Default Description 31:19 RV - Reserved.
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Processor Uncore Configuration Registers Type: Bus: Offset: Bit CFG 1 0x48 PortID: Device: Attr Default N/A 11 Function: 0 Description Redirection Mode Select for Logical Interrupts (RdrModSel): 6:4 RW_LB 0x0 3:2 RV - Selects the redirection mode used for MSI interrupts with lowest-priority delivery mode. The following schemes are used: 000 : Fixed Priority - select the first enabled APIC in the cluster.
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Processor Uncore Configuration Registers Type: Bus: Offset: CFG 1 0x54 PortID: Device: Bit Attr Default 5:3 RW_LB 0x0 N/A 11 Function: 0 Description Node Id 1 (NodeId1): Node Id for group Id 1 Node Id 0 (NodeId0): 2:0 RW_LB 0x0 Node Id for group 0 13.6.1.4 CORECOUNT Number of Cores Reflection of the LTCount2 register Type: Bus: Offset: CFG 1 0x60 PortID: Device: Bit Attr Default 31:5 RV - N/A 11 Function: 0 Description Reserved.
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Processor Uncore Configuration Registers Type: Bus: Offset: CFG 1 0x64 Bit Attr Default 6:6 RWS_V 0x0 PortID: Device: N/A 11 Function: 0 Description SMI Timeout received by UBOX (SMITimeOut): SMI Timeout received by UBOX MMCFG Write Address Misalignment received by UBOX (CFGWrAddrMisAligned): 5:5 RWS_V 0x0 MMCFG Write Address Misalignment received by UBOX MMCFG Read Address Misalignment received by UBOX (CFGRdAddrMisAligned): 4:4 RWS_V 0x0 MMCFG Read Address Misalignment received by UBOX U
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Processor Uncore Configuration Registers 13.6.3 Device 11 Function 3 Register name 13.6.3.1 Offset Size VID 0x0 16 DID 0x2 16 PCICMD 0x4 16 PCISTS 0x6 16 RID 0x8 8 CCR 0x9 24 CLSR 0xc 8 PLAT 0xd 8 HDR 0xe 8 BIST 0xf 8 SVID 0x2c 16 SDID 0x2e 16 CAPPTR 0x34 8 INTL 0x3c 8 INTPIN 0x3d 8 MINGNT 0x3e 8 MAXLAT 0x3f 8 CPUBUSNO 0xd0 32 SMICTRL 0xd8 32 CPUBUSNO Bus Number Configuration for the Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family.
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Processor Uncore Configuration Registers 13.6.3.2 SMICTRL SMI generation control. Type: Bus: Offset: CFG 1 0xd8 PortID: Device: N/A 11 Function: Bit Attr Default Description 31:28 RV - Reserved. 3 Mask SMI Generation on Intel QPI Clock/Data Failover (SMIDis3): 27:27 RW_LB 0x0 Mask SMI generation Intel QPI clock/data failover. 1 - Masked 0 - Unmasked. Note: To get SMI for this Intel QPI Clock/Data Failover event, the QPIERRDIS.smi_en should be set to 1.
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Processor Uncore Configuration Registers Register name 13.7.1.
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Processor Uncore Configuration Registers Type: Bus: Offset: CFG 1 0x60 PortID: Device: Bit Attr Default 7:0 RO_V 0x0 N/A 10 Function: 0 Description Channel 0 Maximum Temperature (Channel0_Max_Temperature): Temperature in Degrees (C). 13.7.1.2 MEM_ACCUMULATED_BW_CH_[0:3] This register contains a measurement proportional to the weighted DRAM BW for the channel including all ranks. The weights are configured in the memory controller channel register PM_CMD_PWR.
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Processor Uncore Configuration Registers Type: Bus: Offset: Bit CFG 1 0x84 Attr PortID: Device: Default N/A 10 Function: 0 Description Minimal Package Power (PKG_MIN_PWR): 30:16 RO_V Varies 15:15 RV - The minimum allowed power limit for a processor that could be used in the PACKAGE_POWER_LIMIT register. The value is in the units identified in POWER_UNIT field in PACKAGE_POWER_SKU_UNIT register. Reserved. TDP Package Power (PKG_TDP): 14:0 13.7.1.
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Processor Uncore Configuration Registers The energy status is reported in units which are defined in PACKAGE_POWER_SKU_UNIT_MSR[ENERGY_UNIT]. The data is updated by PCU microcode and is Read Only for all SW. Type: Bus: Offset: CFG 1 0x90 PortID: Device: Bit Attr Default 31:0 RO_V 0x0 N/A 10 Function: 0 Description Energy Value (DATA): Energy Value 13.7.1.6 PACKAGE_TEMPERATURE Package temperature in degrees (C). This field is updated by FW.
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Processor Uncore Configuration Registers Type: Bus: Offset: CFG 1 0xe4 PortID: Device: N/A 10 Function: Bit Attr Default Description 31:28 RV - Reserved. 0 TJ Max TCC Offset (TJ_MAX_TCC_OFFSET): 27:24 RO_V 0x0 Temperature offset in degrees (C) from the TJ Max. Used for throttling temperature. Will not impact temperature reading.
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Processor Uncore Configuration Registers 13.7.2.1 SSKPD Sticky Scratchpad Data. This register holds 64 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers. Type: Bus: Offset: CFG 1 0x6c PortID: Device: Bit Attr Default 63:0 RWS 0x0 N/A 10 Function: 1 Description Scratchpad Data (SKPD): 4 WORDs of data storage. 13.7.2.2 C2C3TT C2 to C3 Transition Timer. BIOS can update this value during run-time. Unit for this register is usec.
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Processor Uncore Configuration Registers Type: Bus: Offset: Bit CFG 1 0xa4 Attr PortID: Device: Default N/A 10 Function: 1 Description Cores Off Mask (CORE_OFF_MASK): BIOS will set this bit to request that the matching core should not be activated coming out of reset. 15:0 RWS_L 0x0 The default value of this registers means that all cores are enabled. Restrictions: At least one core needs to be left active. Otherwise, FW will ignore the setting altogether. 13.7.
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Processor Uncore Configuration Registers 13.7.3.1 PACKAGE_RAPL_PERF_STATUS This register is used by PCU microcode to report Package Power limit violations in the Platform PBM. Type: Bus: Offset: Bit CFG 1 0x88 Attr PortID: Device: Default N/A 10 Function: 2 Description Power Limit Throttle Counter (PWR_LIMIT_THROTTLE_CTR): 31:0 RO_V 0x0 Reports the number of times the Power limiting algorithm had to clip the power limit due to hitting the lowest power state available.
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Processor Uncore Configuration Registers Type: Bus: Offset: Bit CFG 1 0x90 Attr PortID: Device: Default N/A 10 Function: 2 Description Minimal DRAM Power (DRAM_MIN_PWR): 30:16 RW_L 0x78 The minimal power setting allowed for DRAM. Lower values will be clamped to this value. The minimum setting is typical (not guaranteed). The units for this value are defined in DRAM_POWER_INFO_UNIT_MSR[PWR_UNIT]. 15:15 RV - Reserved.
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Processor Uncore Configuration Registers Dual mapped as PCU IOREG Type: Bus: Offset: Bit CFG 1 0xd8 Attr PortID: Device: Default N/A 10 Function: 2 Description Power Limit Throttle Counter (PWR_LIMIT_THROTTLE_CTR): 31:0 RO_V 0x0 Reports the number of times the Power limiting algorithm had to clip the power limit due to hitting the lowest power state available. Accumulated DRAM throttled time 13.7.3.6 MCA_ERR_SRC_LOG MCA Error Source Log. MCSourceLog is used by the PCU to log the error sources.
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Processor Uncore Configuration Registers Type: Bus: Offset: CFG 1 0xf8 PortID: Device: Bit Attr Default 3:1 RV - N/A 10 Function: 2 Description Reserved1: Reserved. Enable MEM Trip (EN_MEMTRIP): 0:0 RW 0x0 If set to 1, PCU will OR in the MEMtrip information into the ThermTrip OR Tree If set to 0, PCU will ignore the MEMtrip information and ThermTrip will just have the processor indication. Expect BIOS to Enable this in Phase4 13.7.4 Device 10 Function 3 Register name 13.7.4.
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Processor Uncore Configuration Registers Type: Bus: Offset: CFG 1 0x80 PortID: Device: Bit Attr Default 31:28 RV - N/A 10 Function: 3 Description Reserved. CAPID_Version: 27:24 RO_FW 0x1 23:16 RO_FW 0x18 This field has the value 0001b to identify the first revision of the CAPID register definition. CAPID_Length: This field indicates the structure length including the header in Bytes.
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Processor Uncore Configuration Registers Type: Bus: Offset: Bit CFG 1 0x84 Attr PortID: Device: Default N/A 10 Function: 3 Description XSAVE_DIS: 24:24 RO_FW 0x0 23:23 RO_FW 0x0 Disable the following instructions: XSAVE, XSAVEOPT, XRSTOR, XSETBV and XGETBV.
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Processor Uncore Configuration Registers Type: Bus: Offset: CFG 1 0x84 PortID: Device: Bit Attr Default 12:12 RO_FW 0x0 N/A 10 Function: 3 Description HT_DIS: Disable Multi threading LLC_WAY_EN: 11:9 RO_FW 0x0 8:8 RO_FW 0x0 Enable LLC ways value Cache size '000: 0.5 M (4 lower ways) '001: 1 M (8 lower ways) '010: 1.5 M (12 lower ways) '011: 2 M (16 lower ways) '100: 2.
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Processor Uncore Configuration Registers 13.7.4.3 CAPID1 This register is a Capability Register used to expose enable/disable BIOS use. Type: Bus: Offset: Bit CFG 1 0x88 Attr PortID: Device: Default N/A 10 Function: 3 Description DIS_MEM_MIRROR: 31:31 RO_FW 0x0 30:30 RO_FW 0x0 Disable memory channel mirroring mode. In the mirroring mode, the server maintains two identical copies of all data in memory.
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Processor Uncore Configuration Registers Type: Bus: Offset: Bit CFG 1 0x88 Attr PortID: Device: Default N/A 10 Function: 3 Description X2APIC_EN: 7:7 RO_FW 0x0 6:6 RO_FW 0x0 Enable Extended APIC support. When set the enables the support of x2APIC (Extended APIC) in the core and uncore. The being set will impact: a. CPUID indication x2APIC support b. CPU ability to enable x2APIC support c. Uncore ability to generate and send x2APIC messages.
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Processor Uncore Configuration Registers Type: Bus: Offset: CFG 1 0x8c PortID: Device: Bit Attr Default 24:24 RO_FW 0x0 N/A 10 Function: 3 Description QPI_LINK1_DIS: When set Intel® QPI link 1 will be disabled. QPI_LINK0_DIS: 23:23 RO_FW 0x0 When set Intel® QPI link 0 will be disabled. SPARE_SIGNED_FW: 22:22 RO_FW 0x0 Spare (THERMAL_PROFILE): 21:20 RO_FW 0x0 Spare Reserved: 19:19 RV Reserved.
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Processor Uncore Configuration Registers 13.7.4.5 CAPID3 This register is a Capability Register used to expose enable/disable features for BIOS. Type: Bus: Offset: CFG 1 0x90 PortID: Device: N/A 10 Function: Bit Attr Default Description 31:30 RO_FW 0x0 MC_SPARE: 3 MC2GD: 29:24 RO_FW 0x0 MC2GD Bit[5:4]: Tx Pulse Width Control Bit[1:0].
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Processor Uncore Configuration Registers Type: Bus: Offset: Bit CFG 1 0x90 Attr PortID: Device: Default N/A 10 Function: 3 Description DISABLE_RDIMM: 13:13 RO_FW 0x0 RDIMM disable control. When set, RDIMM support is disabled by disabling the RDIMM control word access. In addition, the upper 5 bits of the 13b_T_STAB register will be treated as zeros, i.e.
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Processor Uncore Configuration Registers 13.7.4.6 CAPID4 This register is a Capability Register used to expose enable/disable for BIOS use. Type: Bus: Offset: CFG 1 0x94 PortID: Device: N/A 10 Function: 3 Bit Attr Default Description 31:31 RO_FW 0x0 Disable DRAM Power Meter (DRAM_POWER_METER_DISABLE) 30:30 RO_FW 0x0 Disable DRAM RAPL (DRAM_RAPL_DISABLE) 29:29 RO_FW 0x0 Enable Intelligent Turbo (I_TURBO_ENABLE) 28:15 RV - 14:0 RO_FW 0x0 Reserved: Reserved 13.7.4.
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Processor Uncore Configuration Registers 188 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014
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Integrated I/O (IIO) Configuration Registers 14 Integrated I/O (IIO) Configuration Registers 14.1 Registers Overview 14.1.1 Configuration Registers (CSR) There are two distinct CSR register spaces supported by the IIO Module. The first one is the traditional PCI-defined configuration registers.
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Integrated I/O (IIO) Configuration Registers 14.1.4 PCI Vs. PCIe* Device / Function PCI devices/functions do NOT have a PCIe* capability register set and do not decode offsets 100h and beyond. Accesses to 100h and beyond are master aborted by these devices. I/OxAPIC functions are PCI functions. All other functions in the IIO module are PCIe* functions and these have a PCIe* capability register set and also decode address offsets 100h and beyond. 14.
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Integrated I/O (IIO) Configuration Registers Register name Offset Size Device 0 function Device 2 function Device 3 function RID 0x8 8 0 0-3 0-3 CCR 0x9 24 0 0-3 0-3 CLSR 0xc 8 0 0-3 0-3 PLAT 0xd 8 0 0-3 0-3 HDR 0xe 8 0 0-3 0-3 BIST 0xf 8 0 0-3 0-3 PBUS 0x18 8 0 (PCIe) 0-3 0-3 SECBUS 0x19 8 0 (PCIe) 0-3 0-3 SUBBUS 0x1a 8 0 (PCIe) 0-3 0-3 IOBAS 0x1c 8 0 (PCIe) 0-3 0-3 IOLIM 0x1d 8 0 (PCIe) 0-3 0-3 SECSTS 0x1e 16 0 (PCIe) 0-3 0-3 M
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Integrated I/O (IIO) Configuration Registers Register name 192 Offset Size Device 0 function Device 2 function Device 3 function DEVSTS 0xf2 16 0 (DMI2) DEVSTS 0x9a 16 0 (PCIe) 0-3 0-3 LNKCAP 0x9c 32 0 0-3 0-3 LNKCON 0x1b0 16 0 (DMI2) LNKCON 0xa0 16 0 (PCIe) 0-3 0-3 LNKSTS 0x1b2 16 0 (DMI2) LNKSTS 0xa2 16 0 (PCIe) 0-3 0-3 SLTCAP 0xa4 32 0 (PCIe) 0-3 0-3 SLTCON 0xa8 16 0 (PCIe) 0-3 0-3 SLTSTS 0xaa 16 0 (PCIe) 0-3 0-3 ROOTCON 0xac 16 0 0-3 0-3
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Integrated I/O (IIO) Configuration Registers Register name Offset Size Device 0 function Device 2 function Device 3 function HDRLOG2 0x16c 32 0 0-3 0-3 HDRLOG3 0x170 32 0 0-3 0-3 RPERRCMD 0x174 32 0 0-3 0-3 RPERRSTS 0x178 32 0 0-3 0-3 ERRSID 0x17c 32 0 0-3 0-3 PERFCTRLSTS_0 0x180 32 0 0-3 0-3 PERFCTRLSTS_1 0x184 32 0 0-3 0-3 MISCCTRLSTS_0 0x188 32 0 0-3 0-3 MISCCTRLSTS_1 0x18c 32 0 0-3 0-3 PCIE_IOU_BIF_CTRL 0x190 16 0 0 0 DMICTRL 0x1a0 64
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Integrated I/O (IIO) Configuration Registers Register name 14.2.
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Integrated I/O (IIO) Configuration Registers 14.2.2 DID Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x2 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description For Device 0 Function 0: 0xe00 (DMI2 Mode) 0xe01 (PCIe* Mode) RO 15:0 14.2.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x4 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description serre: 8:8 RW 0x0 7:7 RO 0x0 SERR Enable For PCI Express/DMI ports, this field enables notifying the internal core error logic of occurrence of an uncorrectable error (fatal or nonfatal) at the port.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x4 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description bme: RW 2:2 RO (Device 0 Function 0 DMI mode) 0x0 Bus Master Enable. Controls the ability of the PCI Express port in generating and also in forwarding memory (including MSI writes) or I/O transactions (and not messages) or configuration transactions from the secondary side to the primary side.
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Integrated I/O (IIO) Configuration Registers 14.2.4 PCISTS Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x6 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description dpe: 15:15 RW1C 0x0 Detected Parity Error This bit is set by a root port when it receives a packet on the primary side with an uncorrectable data error (including a packet with poison bit set) or an uncorrectable address/control parity error.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x6 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description sta: 11:11 RW1C 0x0 10:9 RO 0x0 Signaled Target Abort This bit is set when a root port signals a completer abort completion status on the primary side (internal bus of uncore). This condition includes a PCI Express port forwarding a completer abort status received on a completion from the secondary.
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Integrated I/O (IIO) Configuration Registers 14.2.5 RID Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x8 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description revision_id: 7:0 RO_V 0x0 Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in any Intel Xeon processor E7-2800/4800/8800 v2 product family Product Family function.
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Integrated I/O (IIO) Configuration Registers 14.2.8 PLAT Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0xd PortID: Device: Device: Device: Bit Attr Default 7:0 RO 0x0 N/A 0Function:0 2Function:0-3 3Function:0-3 Description primary_latency_timer: Not applicable to PCI Express*. Hardwired to 00h. 14.2.
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Integrated I/O (IIO) Configuration Registers 14.2.11 PBUS Primary Bus Number Register. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x18 Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description pbn: 7:0 14.2.12 RW 0x0 Configuration software programs this field with the number of the bus on the primary side of the bridge. This register has to be kept consistent with the Internal Bus Number 0 in the CPUBUSNO01 register.
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Integrated I/O (IIO) Configuration Registers 14.2.14 IOBAS I/O Base Register. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x1c Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description i_o_base_address: 7:4 RW 0xf Corresponds to A[15:12] of the I/O base address of the PCI Express port. See also the IOLIM register description.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x1d PortID: Device: Device: Device: Bit Attr Default 1:0 RO 0x0 N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description i_o_address_limit_capability: IIO only supports 16 bit addressing 14.2.16 SECSTS Secondary Status Register.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x1e Bit Attr PortID: Device: Device: Device: Default N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description mdpe: 8:8 RW1C 0x0 7:7 RO 0x0 6:6 RV - 5:5 RO 0x0 4:0 RV - Master Data Parity Error This bit is set by the root port on the secondary side (PCI Express link) if the Parity Error Response Enable bit (PERRE) is set in Bridge Control register and either of the following two condition
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Integrated I/O (IIO) Configuration Registers 14.2.18 MLIM Memory Limit Register. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x22 Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description memory_limit_address: Corresponds to A[31:20] of the 32 bit memory window’s limit address that corresponds to the upper limit of the range of memory accesses that will be passed by the PCI Express bridge.
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Integrated I/O (IIO) Configuration Registers 14.2.20 PLIM Prefetchable Memory Limit Register. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x26 Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description prefetchable_memory_limit_address: 15:4 RW 0x0 3:0 RO 0x1 Corresponds to A[31:20] of the prefetchable memory address range’s limit address of the PCI Express port. See also the PLIMU register description.
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Integrated I/O (IIO) Configuration Registers 14.2.22 PLIMU Prefetchable Memory Limit Upper 32 bits. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x2c Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description prefetchable_upper_32_bit_memory_limit_address: Corresponds to A[63:32] of the prefetchable memory address range’s limit address of the PCI Express port.
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Integrated I/O (IIO) Configuration Registers 14.2.24 INTL Interrupt Line Register. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x3c Attr PortID: Device: Device: Device: Default Description RW 7:0 14.2.25 N/A 0Function:0 2Function:0-3 3Function:0-3 interrupt_line: RO (Device 0 Function 0) 0x0 N/A for these devices INTPIN Interrupt Pin Register.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x3e Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description vga16b: This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of alias addresses every 1 KB. 4:4 RW 0x0 0: execute 10-bit address decodes on VGA I/O accesses. 1: execute 16-bit address decodes on VGA I/O accesses.
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Integrated I/O (IIO) Configuration Registers 14.2.27 SCAPID Subsystem Capability Identity. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x40 Attr PortID: Device: Device: Device: Default RO 7:0 14.2.28 N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description capability_id: RW_O (Device 0 Function 0) 0xd Assigned by PCI-SIG for subsystem capability ID SNXTPTR Subsystem ID Next Pointer.
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Integrated I/O (IIO) Configuration Registers 14.2.30 SDID Subsystem Identity. Type: Bus: Offset: CFG 0 0x2e PortID: Device: N/A 0Function:0 (DMI2 Mode) Bus: Bus: Bus: Offset: 0 0 0 0x46 Device: Device: Device: 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Bit Attr Default Description subsystem_device_id: 15:0 14.2.31 RW_O 0x0 Assigned by the subsystem vendor to uniquely identify the subsystem. The default value specifies Intel but can be set to any value once after reset.
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Integrated I/O (IIO) Configuration Registers 14.2.32 MSICAPID MSI Capability ID. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x60 Bit Attr Default 7:0 RO 0x5 PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description capability_id: Assigned by PCI-SIG for MSI root ports. 14.2.33 MSINXTPTR MSI Next Pointer.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x62 Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description mme: 6:4 RW 0x0 Multiple Message Enable. Applicable only to PCI Express ports. Software writes to this field to indicate the number of allocated messages which is aligned to a power of two. When MSI is enabled, the software will allocate at least one message to the device.
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Integrated I/O (IIO) Configuration Registers 14.2.36 MSGDAT MSI Data Register. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x68 PortID: Device: Device: Device: Bit Attr Default Description 31:16 RV - Reserved. N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 data: 15:0 14.2.37 RW 0x0 Refer to the Interrupt Chapter for details of how this field is interpreted by IIO hardware. The definition of this field depends on whether interrupt remapping is enabled or disabled. MSIMSK MSI Mask Bit.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x70 Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description pending_bits: 1:0 RO_V 0x0 Relevant only when MSI is enabled and used for interrupts generated by the root port. When MSI is not enabled or used by the root port, this register always reads a value 0. For each Pending bit that is set, the PCI Express port has a pending associated message.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x92 PortID: Device: Device: Device: Bit Attr Default Description 15:14 RV - Reserved. N/A 0Function:0 2Function:0-3 3Function:0-3 interrupt_message_number: 13:9 RO 0x0 Applies to root ports. This field indicates the interrupt message number that is generated for PM/Hot Plug/BW-change events.
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Integrated I/O (IIO) Configuration Registers 14.2.42 DEVCAP The PCI Express Device Capabilities register identifies device specific information for the device. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x94 PortID: Device: Device: Device: Bit Attr Default Description 31:28 RV - Reserved. 27:26 RO 0x0 N/A 0Function:0 2Function:0-3 3Function:0-3 captured_slot_power_limit_scale: Does not apply to root ports or integrated devices.
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Integrated I/O (IIO) Configuration Registers 14.2.43 DEVCTRL PCI Express Device Control. Type: Bus: Offset: CFG 0 0xf0 PortID: Device: N/A 0Function:0 (DMI2 Mode) Bus: Bus: Bus: Offset: 0 0 0 0x98 Device: Device: Device: 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Bit Attr Default Description 15:15 RV - Reserved. 14:12 RO 0x0 max_read_request_size: PCI Express/DMI ports in Processor do not generate requests greater than 64B and this field is RO.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0xf0 PortID: Device: N/A 0Function:0 (DMI2 Mode) Bus: Bus: Bus: Offset: 0 0 0 0x98 Device: Device: Device: 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Bit Attr Default Description fatal_error_reporting_enable: 2:2 RW 0x0 Controls the reporting of fatal errors that IIO detects on the PCI Express/DMI interface.
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Integrated I/O (IIO) Configuration Registers 14.2.44 DEVSTS PCI Express Device Status. Type: Bus: Offset: CFG 0 0xf2 PortID: Device: N/A 0Function:0 (DMI2 Mode) Bus: Bus: Bus: Offset: 0 0 0 0x9a Device: Device: Device: 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Bit Attr Default Description 15:6 RV - Reserved. 5:5 RO 0x0 4:4 RO 0x0 transactions_pending: Does not apply to Root/DMI ports, that is, bit hardwired to 0 for these devices.
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Integrated I/O (IIO) Configuration Registers 14.2.45 LNKCAP PCI Express Link Capabilities The Link Capabilities register identifies the PCI Express specific link capabilities. The link capabilities register needs some default values setup by the local host. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x9c Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description port_number: 31:24 RW_O 0x0 23:23 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x9c Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description l0s_exit_latency: 14:12 RW_O 0x3 This field indicates the L0s exit latency (i.e L0s to L0) for the PCI Express* port.
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Integrated I/O (IIO) Configuration Registers 14.2.46 LNKCON PCI Express Link Control The PCI Express Link Control register controls the PCI Express Link specific parameters. The link control register needs some default values setup by the local host. Type: Bus: Offset: CFG 0 0x1b0 PortID: Device: N/A 0Function:0 (DMI2 Mode) Bus: Bus: Bus: Offset: 0 0 0 0xa0 Device: Device: Device: 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Bit Attr Default Description 15:12 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x1b0 PortID: Device: N/A 0Function:0 (DMI2 Mode) Bus: Bus: Bus: Offset: 0 0 0 0xa0 Device: Device: Device: 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Bit Attr Default Description retrain_link: 5:5 WO 0x0 A write of 1 to this bit initiates link retraining in the given PCI Express/DMI port by directing the LTSSM to the recovery state if the current state is [L0, L0s or L1].
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Integrated I/O (IIO) Configuration Registers 14.2.47 LNKSTS PCI Express Link Status The PCI Express Link Status register provides information on the status of the PCI Express Link such as negotiated width, training, and so forth. The link status register needs some default values setup by the local host.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x1b2 PortID: Device: N/A 0Function:0 (DMI2 Mode) Bus: Bus: Bus: Offset: 0 0 0 0xa2 Device: Device: Device: 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Bit Attr Default Description link_training: 11:11 RO_V 0x0 10:10 RV - This field indicates the status of an ongoing link training session in the PCI Express port 0: LTSSM has exited the recovery/configuration state.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0xa4 Attr PortID: Device: Device: Device: Default N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description command_complete_not_capable: 18:18 RO 0x0 Intel Xeon processor E7-2800/4800/8800 v2 product family Product Family is capable of command complete interrupt.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0xa4 Attr PortID: Device: Device: Device: Default N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description power_indicator_present: 4:4 RW_O 0x0 This bit indicates that a Power Indicator is implemented for this slot and is electrically controlled by the chassis.
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Integrated I/O (IIO) Configuration Registers 14.2.49 SLTCON PCI Express Slot Control. Any write to this register will set the Command Completed bit in the SLTSTS register, ONLY if the VPP enable bit for the port is set. If the port’s VPP enable bit is set (that is, hotplug for that slot is enabled), then the required actions on VPP are completed before the Command Completed bit is set in the SLTSTS register.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0xa8 Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description attention_indicator_control: 7:6 RW 0x3 If an Attention Indicator is implemented, writes to this field will set the Attention Indicator to the written state.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0xa8 Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description attention_button_pressed_enable: 0:0 14.2.50 RW 0x0 This bit enables the generation of hot-plug interrupts or wake messages via an attention button pressed event. 0: disables generation of hot-plug interrupts or wake messages when the attention button is pressed.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0xaa Attr PortID: Device: Device: Device: Default N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description mrl_sensor_state: 5:5 RO_V This bit reports the status of an MRL sensor if it is implemented. 0: MRL Closed 1: MRL Open Refer to RAS Chapter for details of how this bit is shifted in on the VPP bit stream.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0xac Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description crsswvisen: 4:4 RW 0x0 CRS software visibility Enable This bit, when set, enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0xac Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description senfeen: 1:1 RW 0x0 System Error on Nonfatal Error Enable This field enables notifying the internal IIO core error logic of occurrence of an uncorrectable nonfatal error at the port or below its hierarchy.
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Integrated I/O (IIO) Configuration Registers 14.2.52 ROOTCAP PCI Express Root Capabilities. Type: Bus: Bus: Bus: Offset: PortID: Device: Device: Device: Bit Attr Default Description 15:1 RV - Reserved. RO 0x1 RW_O (Device 0 Function 0) 0x0 (Device 0 Function 0) 0:0 14.2.
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Integrated I/O (IIO) Configuration Registers 14.2.54 DEVCAP2 PCI Express Device Capabilities 2 Register. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0xb4 PortID: Device: Device: Device: Bit Attr Default Description 31:14 RV - Reserved. N/A 0Function:0 2Function:0-3 3Function:0-3 tph_completer_supported: 13:12 RW_O 0x1 11:10 RV - 9:9 RO 0x1 Indicates the support for TLP Processing Hints. Processor does not support the extended TPH header. 00: TPH and Extended TPH Completer not supported.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0xb4 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description cmpltovalsup: 3:0 14.2.55 RO 0xe Completion Timeout Values Supported This field indicates device support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout range.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0xf8 PortID: Device: N/A 0Function:0 (DMI2 Mode) Bus: Bus: Bus: Offset: 0 0 0 0xb8 Device: Device: Device: 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Bit Attr Default Description compltodis: RW_V (Device 2 and 3 Function 0) 4:4 RW (Device 0 Function0, Device 2 and 3 Function 1-3) 0x0 0x1 (Device 0 Function 0) Completion Timeout Disable When set to 1b, this bit disables the Completion Timeout mechanism for all NP
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0xbc Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description lnkspdvec: 0x7 7:1 0:0 240 RW_O RV 0x3 (Device 0 Function 0) - Supported Link Speeds Vector - This field indicates the supported Link speeds of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link speed is not supported.
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Integrated I/O (IIO) Configuration Registers 14.2.57 LNKCON2 Type: Bus: Offset: CFG 0 0x1c0 PortID: Device: N/A 0Function:0 (DMI2 Mode) Bus: Bus: Bus: Offset: 0 0 0 0xc0 Device: Device: Device: 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Bit Attr Default Description compliance_de_emphasis: For 8GT/s Data Rate: This bit sets the Transmitter Preset level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x1c0 PortID: Device: N/A 0Function:0 (DMI2 Mode) Bus: Bus: Bus: Offset: 0 0 0 0xc0 Device: Device: Device: 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Bit Attr Default Description selectable_de_emphasis: 6:6 RW_O 0x0 When the Link is operating at 5.0 GT/s speed, this bit selects the level of deemphasis for an Upstream component.Encodings: 1b -3.5 dB 0b -6 dB When the Link is operating at 2.
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Integrated I/O (IIO) Configuration Registers 14.2.58 LNKSTS2 PCI Express Link Status Register 2. Type: Bus: Offset: CFG 0 0x1c2 PortID: Device: N/A 0Function:0 (DMI2 Mode) Bus: Bus: Bus: Offset: 0 0 0 0xc2 Device: Device: Device: 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Bit Attr Default Description 15:6 RV - Reserved. lnkeqreq: 5:5 RW1CS 0x0 This bit is Set by hardware to request Link equalization process to be performed on the link. Reserved for Device 0 Function 0.
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Integrated I/O (IIO) Configuration Registers 14.2.59 PMCAP Power Management Capabilities The PM Capabilities Register defines the capability ID, next pointer and other power management related support. The following PM registers/capabilities are added for software compliance.
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Integrated I/O (IIO) Configuration Registers 14.2.60 PMCSR Power Management Control and Status Register This register provides status and control information for PM events in the PCI Express port of the IIO.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0xe4 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description power_state: RW 1:0 14.2.61 RW_L (Device 0 Function 0) 0x0 This 2-bit field is used to determine the current power state of the function and to set a new power state as well.
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Integrated I/O (IIO) Configuration Registers 14.2.62 XPREUT_HDR_CAP REUT PCIe* Header Capability. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x104 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description vseclength: 31:20 RO 0xc VSEC Length This field defines the length of the REUT ‘capability body’.
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Integrated I/O (IIO) Configuration Registers 14.2.64 ACSCAPHDR Access Control Services Extended Capability Header. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x110 Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description next_capability_offset: 31:20 RO_V 0x148 19:16 RO 0x1 This field points to the next Capability in extended configuration space. In PCIe* Mode, it points to the Advanced Error Capability.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: 14.2.66 CFG 0 0 0 0x114 PortID: Device: Device: Device: Bit Attr Default 1:1 RO_V (Device 2 and 3 Function 0) RO (Device 0 Function 0, Device 2 and 3 Function 1-3) 0x1 0:0 RO_V (Device 2 and 3 Function 0) RO (Device 0 Function 0, Device 2 and 3 Function 1-3) 0x1 N/A 0Function:0 (PCIe* mode) 2Function:0-3 3Function:0-3 Description b: Applies only to root ports.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x116 PortID: Device: Device: Device: Attr Default Description v: RW_L (Device 2 and 3 Function 0) 0:0 Applies only to root ports. When set, the component validates the Bus Number from the Requester ID of upstream Requests against the secondary subordinate Bus Numbers. 0x0 RW (Device 0 Function 0, Device 2 and 3 Function 1-3) 14.2.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x142 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description addr: Applies only to root ports. 11:1 RW 0x0 Bits 31:20 are assumed to be 0xFECh. Bits 8:0 are a don’t care for address decode. Address decoding to the APIC range is done as APICBASE.ADDR[31:8] <= A[31:8] <= APICLIMIT.ADDR[31:8].
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Integrated I/O (IIO) Configuration Registers 14.2.71 ERRCAPHDR PCI Express Enhanced Capability Header - Root Ports. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x148 Attr Default PortID: Device: Device: Device: N/A 0Function:0 (PCIe* Mode) 2Function:0-3 3Function:0-3 Description next_capability_offset: 31:20 RO 0x1d0 19:16 RO 0x1 This field points to the next Capability in extended configuration space or is 0 if it is that last capability.
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Integrated I/O (IIO) Configuration Registers 14.2.73 UNCERRMSK Uncorrectable Error Mask. This register masks uncorrectable errors from being signaled. Type: Bus: Bus: Bus: Offset: 14.2.74 CFG 0 0 0 0x150 PortID: Device: Device: Device: Bit Attr Default Description 31:22 RV - Reserved. N/A 0Function:0 2Function:0-3 3Function:0-3 21:21 RWS 0x0 acs_violation_mask: 20:20 RWS 0x0 unsupported_request_error_mask: 19:19 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: 254 CFG 0 0 0 0x154 PortID: Device: Device: Device: Bit Attr Default Description 12:12 RWS 0x0 poisoned_tlp_severity: N/A 0Function:0 2Function:0-3 3Function:0-3 11:6 RV - Reserved. 5:5 RWS 0x1 surprise_down_error_severity: 4:4 RWS 0x1 data_link_protocol_error_severity: 3:0 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers 14.2.75 CORERRSTS Correctable Error Status. This register identifies the status of the correctable errors that have been detected by the PCI Express port. Type: Bus: Bus: Bus: Offset: 14.2.76 CFG 0 0 0 0x158 PortID: Device: Device: Device: Bit Attr Default Description 31:14 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers 14.2.77 ERRCAP Advanced Error capabilities and Control Register. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x160 PortID: Device: Device: Device: Bit Attr Default Description 31:9 RV - Reserved. 8:8 RO 0x0 N/A 0Function:0 2Function:0-3 3Function:0-3 ecrc_check_enable: N/A for IIO. ecrc_check_capable: 7:7 RO 0x0 N/A for IIO. ecrc_generation_enable: 6:6 RO 0x0 N/A for IIO. ecrc_generation_capable: 5:5 RO 0x0 N/A for IIO.
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Integrated I/O (IIO) Configuration Registers This register controls behavior upon detection of errors. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x174 Bit Attr Default 31:3 RV - PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description Reserved. fatal_error_reporting_enable: 2:2 RW 0x0 Applies to root ports only. Enable MSI/INTx interrupt on fatal errors when set. non_fatal_error_reporting_enable: 1:1 RW 0x0 Applies to root ports only.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x178 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description non_fatal_error_messages_received: 5:5 RW1CS 0x0 4:4 RW1CS 0x0 Set when one or more nonFatal Uncorrectable error Messages have been received. first_uncorrectable_fatal: Set when bit 2 is set (from being clear) and the message causing bit 2 to be set is an ERR_FATAL message.
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Integrated I/O (IIO) Configuration Registers 14.2.82 PERFCTRLSTS_0 Performance Control and Status Register 0. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x180 PortID: Device: Device: Device: Bit Attr Default Description 31:21 RV - Reserved. N/A 0Function:0 2Function:0-3 3Function:0-3 20:16 RW 0x18 outstanding_requests_gen1: 15:14 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x180 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description nosnoopoprden: 2:2 14.2.
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Integrated I/O (IIO) Configuration Registers 14.2.84 MISCCTRLSTS_0 MISC Control and Status Register 0. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x188 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description disable_l0s_on_transmitter: 31:31 RW 0x0 30:30 RW_O 0x1 When set, IIO never puts its tx in L0s state, even if OS enables it via the Link Control register.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x188 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description maltlp_32baddr64bhdr_en: 20:20 RW 0x1 19:19 RV - When set, enables reporting a Malformed packet when the TLP is a 32 bit address in a 4DW header. PCI Express forbids using 4DW header sizes when the address is less than 4 GB, but some cards may use the 4DW header anyway.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x188 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description enable_system_error_only_for_aer: 4:4 14.2.85 RW Applies only to root ports. For Dev#0 in DMI mode, this bit is to be left at default value always.When this bit is set, the PCI Express errors do not trigger an MSI or Intx interrupt, regardless of the whether MSI or INTx is enabled or not.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x18c Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description override_socketid_in_cplid: 9:9 RW 0x0 8:7 RV - For TPH/DCA requests, the Completer ID can be returned with SocketID when this bit is set. Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x18c Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0-3 3Function:0-3 Description override_system_error_on_pcie_correctable_error_enable: 1:1 RW When set, correctable errors on PCI Express (that have been successfully propagated to the primary interface of the port) are sent to the IIO core error logic (for further escalation) regardless of the setting of the equivalent bit in the ROOTCT
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x190 Attr PortID: Device: Device: Device: Default N/A 0Function:0 2Function:0 3Function:0 Description iou_bifurcation_control: To select a IOU bifurcation, software sets this field and then either a) sets bit 3 in this register to initiate training OR b) resets the entire Intel Xeon processor E7-2800/4800/8800 v2 product family Product Family and on exit from that reset, CPU will bifurcate the ports per the settin
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x1a0 Attr Default PortID: Device: N/A 0Function:0 (DMI2 Mode) Description abort_inbound_requests: 0:0 RW 0x1 Setting this bit causes IIO to abort all inbound requests on the DMI port. This will be used during specific power state and reset transitions to prevent requests from PCH. This bit does not apply in PCI Express mode.
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Integrated I/O (IIO) Configuration Registers 14.2.90 ERRINJHDR PCI Express Error Injection Capability Header. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x1d4 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description vseclen: 31:20 RO 0xa Vendor Specific Capability Length Indicates the length of the capability structure, including header bytes.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x1d8 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description cause_rcverr: 1:1 RW 0x0 Cause a Receiver Error When this bit is written to transition from 0 to 1, one and only one error assertion pulse is produced on the error source signal for the given port.
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Integrated I/O (IIO) Configuration Registers the system software. Mask bits mask the reporting of an error and severity bit controls escalation to either fatal or nonfatal error to the internal core error logic. Note that internal errors detected in the PCI Express cluster are not dependent on any other control bits for error escalation other than the mask bit defined in these registers. All these registers are sticky.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x208 PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Bit Attr Default Description 4:4 RW1CS 0x0 sent_completion_with_unsupported_request: 3:3 RW1CS 0x0 sent_completion_with_completer_abort: Reserved2: 2:2 RV Reserved 1:1 RW1CS 0x0 outbound_switch_fifo_data_parity_error_detected: Reserved1: 0:0 RV Reserved. 14.2.96 XPUNCERRMSK XP Uncorrectable Error Mask.
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Integrated I/O (IIO) Configuration Registers 14.2.97 XPUNCERRSEV XP Uncorrectable Error Severity Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x210 PortID: Device: Device: Device: Bit Attr Default Description 31:10 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers This register masks PCIe* link related uncorrectable errors from causing the associated AER status bit to be set. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x218 PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Bit Attr Default Description 31:22 RV - Reserved. 21:21 RWS 0x0 acs_violation_detect_mask: 20:20 RWS 0x0 received_an_unsupported_request_detect_mask: 19:19 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers 14.2.101 RPEDMASK Root Port Error Detect Status Mask This register masks the associated error messages (received from PCIe* link and NOT the virtual ones generated internally), from causing the associated status bits in AER to be set. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x220 Attr PortID: Device: Device: Device: Default Description N/A 0Function:0 2Function:0-3 3Function:0-3 31:3 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers 14.2.103 XPCOREDMASK XP Correctable Error Detect Mask This register masks other correctable errors from causing the associated XPCORERRSTS status bit to be set. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x228 PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Bit Attr Default Description 31:1 RV - Reserved. 0:0 RWS 0x0 pci_link_bandwidth_changed_detect_mask: 14.2.
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Integrated I/O (IIO) Configuration Registers Check that the perfmon registers are per “cluster”. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x232 Bit Attr Default 15:3 RV - PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description Reserved. xp_cluster_global_first_error_pointer: 2:0 ROS_V 0x0 This field points to which of the 3 errors indicated in the XPGLBERRSTS register happened first.
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Integrated I/O (IIO) Configuration Registers 14.2.107 LNKCON3 Link Control 3 Register. Type: Bus: Bus: Offset: CFG 0 0 0x254 PortID: Device: Device: Bit Attr Default Description 31:2 RV - Reserved. N/A 2Function:0-3 3Function:0-3 lnkeqreqinten: 1:1 RW 0x0 Link Equalization Request Interrupt Enable. When Set, this bit enables the generation of interrupt to indicate that the Link Equalization Request bit has been set. perfeq: 0:0 RW 0x0 Performance Equalization.
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Integrated I/O (IIO) Configuration Registers 14.2.109 LN[0:3]EQ Lane 0 through Lane 3 Equalization Control Type: Bus: Bus: Offset: CFG PortID: 0 Device: 0 Device: 0x25c, 0x25e, 0x260, 0x262 Bit Attr Default Description 15:15 RV - Reserved. N/A 2Function:0-3 3Function:0-3 dnrxpreset: 14:12 RW_O 0x7 Downstream Component Receiver Preset Hint Receiver Preset Hint for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2’es.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Offset: Bit CFG PortID: 0 Device: 0 Device: 0x25c, 0x25e, 0x260, 0x262 Attr Default N/A 2Function:0-3 3Function:0-3 Description uprxpreset: 6:4 RO 0x7 Upstream Component Receiver Preset Hint Receiver Preset Hint for Upstream Component. The upstream component uses this hint for receiver equalization. The Root Ports are upstream components. The encodings are defined below.
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Integrated I/O (IIO) Configuration Registers 14.2.110 LN[4:7]EQ Lane 4 through Lane 7 Equalization Control This register is unused when the link is configured at x4 in the bifurcation register. Type: Bus: Bus: Offset: CFG PortID: 0 Device: 0 Device: 0x264, 0x266, 0x268, 0x26a Bit Attr Default Description 15:15 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Offset: Bit CFG PortID: 0 Device: 0 Device: 0x264, 0x266, 0x268, 0x26a Attr Default N/A 2Function:0, 2 3Function:0, 2 Description uprxpreset: 6:4 RO 0x7 Upstream Component Receiver Preset Hint Receiver Preset Hint for Upstream Component. The upstream component uses this hint for receiver equalization. The Root Ports are upstream components. The encodings are defined below.
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Integrated I/O (IIO) Configuration Registers 14.2.111 LN[8:15]EQ Lane 8 though Lane 15 Equalization Control This register is unused when the link is configured at x4 or x8 in the bifurcation register. Type: Bus: Bus: Offset: CFG PortID: N/A 0 Device: 2Function:0 0 Device: 3Function:0 0x26c, 0x26e, 0x270, 0x272, 0x274, 0x276, 0x278, 0x27a Bit Attr Default Description 15:15 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Offset: Bit CFG PortID: N/A 0 Device: 2Function:0 0 Device: 3Function:0 0x26c, 0x26e, 0x270, 0x272, 0x274, 0x276, 0x278, 0x27a Attr Default Description uprxpreset: 6:4 RO 0x7 Upstream Component Receiver Preset Hint Receiver Preset Hint for Upstream Component. The upstream component uses this hint for receiver equalization. The Root Ports are upstream components. The encodings are defined below.
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Integrated I/O (IIO) Configuration Registers 14.2.112 LER_CAP Live Error Recovery Capability. Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x280 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description nxtptr: 31:20 RO 0x0 19:16 RO 0x1 Next Capability Offset.This field points to the next Capability in extended configuration space. capver: Capability Version. Set to 1h for this version of the PCI Express logic.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x288 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description LER_Status: 31:31 RW1CS 0x0 Indicates that an error was detected that caused the PCIe* port to go into a live error recovery (LER) mode. While in LER mode, the link goes into a LinkDown “Disabled” state and all outbound transactions are aborted (including packets that may have caused the error).
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Integrated I/O (IIO) Configuration Registers 14.2.115 LER_UNCERRMSK Live Error Recovery Uncorrectable Error Mask This register masks uncorrectable errors from being signaled as LER events. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x28c Bit Attr Default 31:22 RV - PortID: Device: Device: Device: N/A 0Function:0 2Function:0-3 3Function:0-3 Description Reserved4: Reserved. acs_violation_mask: 21:21 RWS 0x0 ACS Violation Mask.
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Integrated I/O (IIO) Configuration Registers 14.2.116 LER_XPUNCERRMSK Live Error Recovery XP Uncorrectable Error Mask. Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x290 PortID: Device: Device: Device: Bit Attr Default Description 31:10 RV - Reserved. 9:9 RWS 0x0 8:7 RV - N/A 0Function:0 2Function:0-3 3Function:0-3 outbound_poisoned_data_mask: Masks signaling of stop and scream condition to the core error logic Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x480 Attr , 0x484 Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0 3Function:0 Description pm_data_counter_low_value: 31:0 288 RW_V 0x0 PM data counter low value Low order bits [31:0] for PM data counter[1:0].
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Integrated I/O (IIO) Configuration Registers 14.2.119 XPPMCL[0:1] XP PM Compare Low Bits The value of PMD is compared to the value of PMC. If PMD is greater than PMC, this status is reflected in the PERFCON register and/or on the GE[3:0] (TBD) as selected in the Event Status Output field of the PMR register.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x492 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0 3Function:0 Description high_nibble_pex_compare1_value: 11:8 RW_V 0xf 7:4 RV - 3:0 RW_V 0xf High Nibble PEX Compare1 value High order bits [35:32] of the 36-bit PM Compare1 register. Reserved. high_nibble_pex_compare0_value: High Nibble PEX Compare0 value High order bits [35:32] of the 36-bit PM Compare0 register. 14.2.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: CFG 0 0 0 0x494, 0x498 PortID: Device: Device: Device: Bit Attr Default Description 26:22 RV - Reserved 21:21 RW 0x0 N/A 0Function:0 2Function:0 3Function:0 local_dft_event_select: event_group_selection: 20:19 RW 0x0 Event Group Selection Selects which event register to use for performance monitoring.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x494, 0x498 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0 3Function:0 Description counter_enable_source: 13:11 RW 0x0 Counter enable source These bits identify which input enables the counter. Default value disables counting. 000: Disabled 001: Local Count Enabled (LCEN). This bit is always a logic 1.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x494, 0x498 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0 3Function:0 Description cto: 4:3 RW 0x0 PerfMon Trigger Output This field selects what the signal is communicated to the chip’s event logic structure. 00: No cluster trigger output from PerfMons or header match. 01: PM Status. 10: PM Event Detection.
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Integrated I/O (IIO) Configuration Registers IO_Cfg_Write_event = (REQCMP[0] & CMPR[1] & RDWR[1] & DATALEN & (TTYP[2] + (TTYP[1] & CFGTYP))) IO_Cfg_Read_event = (REQCMP[0] & CMPR[1] & RDWR[0] & DATALEN & (TTYP[2] + (FMTTYP[1] & CFGTYP))) Mem_Write_event = (REQCMP[0] & CMPR[0] & RDWR[1] & DATALEN & TTYP[3] & LOCK & EXTADDR & SNATTR) Note: An outbound memory write does not have a snoop attribute as an inbound memory write has.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x49c, 0x4a0 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0 3Function:0 Description request_packet_only: 23:22 RW 0x0 Completion Required x1: No completion required 1x: Completion required 11: Either lock_attribute_selection: 21:20 RW 0x0 Lock Attribute Selection x1: No lock 1x: Lock 11: Either extended_addressing_header: 19:18 RW 0x0 Extended Addressing Header x1: 32b addressi
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Bus: Offset: Bit CFG 0 0 0 0x49c, 0x4a0 Attr Default PortID: Device: Device: Device: N/A 0Function:0 2Function:0 3Function:0 Description for_completion_packet_or_message_encoding_for_request_packet: 3:0 296 RW 0x0 Completion Status.
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Integrated I/O (IIO) Configuration Registers 14.2.124 XPPMEVH[0:1] XP PM Events High Selections in this register correspond to fields within the PEX packet header. Each field selection is ANDed with all other fields in this register including the XPPMEVL except for the Global Event signals. These signals are OR’ed with any event in the XPPMEVL and enables for debug operations requiring the accumulation of specific debug signals.
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Integrated I/O (IIO) Configuration Registers 14.2.125 XPPMER[0:1] XP PM Resource Event. This register is used to select queuing structures for measurement. Use of this event register is mutually exclusive with the XPPMEV{L,H} registers. The Event Register Select field in the PMR register must select this register for to enable monitoring operations of the queues.
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Integrated I/O (IIO) Configuration Registers 14.3 Device 0 Function 0 Region DMIRCBAR DMI Root Complex Registers Block (RCRB). This block is mapped into memory space, using register DMIRCBAR [Device 0:Function 0, offset 0x50]. Register name 14.3.
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Integrated I/O (IIO) Configuration Registers 14.3.2 DMIVC0RCTL DMI VC0 Resource Control Controls the resources associated with PCI Express Virtual Channel 0. Type: Bus: Offset: Bit MEM 0 0x14 Attr Default PortID: Device: 8’h7e 0Function:0 Description vc0e: 31:31 RO 0x1 30:27 RV - Virtual Channel 0 Enable For VC0 this is hardwired to 1 and read only as VC0 can never be disabled. Reserved vc0id: 26:24 RO 0x0 23:8 RV - Virtual Channel 0 ID Assigns a VC ID to the VC resource.
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Integrated I/O (IIO) Configuration Registers 14.3.3 DMIVC0RSTS DMI VC0 Resource Status. Reports the Virtual Channel specific status. Type: Bus: Offset: MEM 0 0x1a PortID: Device: Bit Attr Default Description 15:2 RV - Reserved 8’h7e 0Function:0 vc0np: 14.3.4 1:1 RO_V 0x1 0:0 RV - Virtual Channel 0 Negotiation Pending 0: The VC negotiation is complete. 1: The VC resource is still in the process of negotiation (initialization or disabling).
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Integrated I/O (IIO) Configuration Registers 14.3.5 DMIVC1RCTL DMI VC1 Resource Control Controls the resources associated with PCI Express Virtual Channel 1. Type: Bus: Offset: Bit MEM 0 0x20 Attr Default PortID: Device: 8’h7e 0Function:0 Description vc1e: 31:31 RW_LB 0x0 30:27 RV - Virtual Channel 1 Enable 0: Virtual Channel is disabled. 1: Virtual Channel is enabled. See exceptions below. Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete.
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Integrated I/O (IIO) Configuration Registers 14.3.6 DMIVC1RSTS DMI VC1 Resource Status Reports the Virtual Channel specific status. Type: Bus: Offset: MEM 0 0x26 PortID: Device: Bit Attr Default Description 15:2 RV - Reserved 8’h7e 0Function:0 vc1np: 14.3.7 1:1 RO_V 0x1 0:0 RV - Virtual Channel 1 Negotiation Pending 0: The VC negotiation is complete.1: The VC resource is still in the process of negotiation (initialization or disabling).
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Integrated I/O (IIO) Configuration Registers 14.3.8 DMIVCPRCTL DMI VCP Resource Control Controls the resources associated with the DMI Private Channel (VCp). Type: Bus: Offset: Bit MEM 0 0x1a Attr Default PortID: Device: 8’h7e 0Function:0 Description vcpe: 31:31 RW_LB 0x0 30:27 RV - Virtual Channel Private Enable 0: Virtual Channel is disabled. 1: Virtual Channel is enabled. See exceptions below. Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete.
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Integrated I/O (IIO) Configuration Registers 14.3.9 DMIVCPRSTS DMI VCP Resource Status Reports the Virtual Channel specific status. Type: Bus: Offset: MEM 0 0x32 PortID: Device: Bit Attr Default Description 15:2 RV - Reserved 8’h7e 0Function:0 vcpnp: 14.3.10 1:1 RO_V 0x1 0:0 RV - Virtual Channel Private Negotiation Pending 0: The VC negotiation is complete. 1: The VC resource is still in the process of negotiation (initialization or disabling).
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Integrated I/O (IIO) Configuration Registers 14.3.11 DMIVCMRCTL DMI VCM Resource Control Controls the resources associated with PCI Express Virtual Channel 0. Type: Bus: Offset: Bit MEM 0 0x38 Attr Default PortID: Device: 8’h7e 0Function:0 Description vcme: 31:31 RW_LB 0x0 30:27 RV - Virtual Channel M Enable 0: Virtual Channel is disabled. 1: Virtual Channel is enabled. See exceptions below. Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x3e Attr Default PortID: Device: 8’h7e 0Function:0 Description vcmnp: 14.3.13 1:1 RO_V 0x1b 0:0 RV - Virtual Channel M Negotiation Pending 0: The VC negotiation is complete. 1: The VC resource is still in the process of negotiation (initialization or disabling). This bit indicates the status of the process of Flow Control initialization.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x64 Attr Default PortID: Device: 8’h7e 0Function:0 Description prd: 31:24 RWS 0x0 23:22 RV - 21:16 RWS 0x0 15:8 RWS 0x0 7:6 RV - Posted Request Data VCp Credit Withhold Number of VCp Posted Data credits to withhold from being reported or used. Reserved prh: Posted Request Header VCp Credit Withhold Number of VCp Posted Request credits to withhold from being reported or used.
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Integrated I/O (IIO) Configuration Registers 14.4 Device 4 Function 0-7 Intel® Quick Data DMA Registers.
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Integrated I/O (IIO) Configuration Registers 14.4.1 VID Type: Bus: Offset: CFG 0 0x0 PortID: Device: Bit Attr Default 15:0 RO 0x8086 N/A 4Function:0-7 Description vendor_identification_number: The value is assigned by PCI-SIG to Intel. 14.4.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x4 PortID: Device: Bit Attr Default 7:7 RO 0x0 N/A 4Function:0-7 Description idsel_stepping_wait_cycle_control: N/A perre: 6:6 RO 0x0 This bit has no impact on error reporting from Intel® Quick Data DMA. vga_palette_snoop_enable: 5:5 RO 0x0 Not applicable to internal IIO devices. Hardwired to 0. mwie: 4:4 RO 0x0 Not applicable to internal IIO devices. Hardwired to 0. sce: 3:3 RO 0x0 Not applicable to PCI Express.
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Integrated I/O (IIO) Configuration Registers 14.4.4 PCISTS Type: Bus: Offset: Bit CFG 0 0x6 Attr PortID: Device: Default N/A 4Function:0-7 Description dpe: 15:15 RW1C 0x0 14:14 RO 0x0 This bit is set by a device when it receives a packet on the primary side with an uncorrectable data error or an uncorrectable address/control parity error. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x6 Attr PortID: Device: Default N/A 4Function:0-7 Description intxsts: 14.4.5 3:3 RO_V 0x0 2:0 RV - Indicates that a legacy INTx interrupt condition is pending internally in the Intel® Quick Data DMA device. This bit has meaning only in the legacy interrupt mode. This bit is always 0 when MSI-X (see xref ) has been selected for DMA interrupts.
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Integrated I/O (IIO) Configuration Registers 14.4.7 CLSR Type: Bus: Offset: CFG 0 0xc PortID: Device: Bit Attr Default 7:0 RW 0x0 N/A 4Function:0-7 Description cacheline_size: 314 This register is set as RW for compatibility reasons only. Cacheline size is always 64B.
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Integrated I/O (IIO) Configuration Registers 14.4.8 HDR Type: Bus: Offset: CFG 0 0xe PortID: Device: Bit Attr Default 7:7 RO 0x1 N/A 4Function:0-7 Description multi_function_device: This bit defaults to 1b since all these devices are multifunction configuration_layout: 6:0 14.4.9 RO 0x0 This field identifies the format of the configuration header layout. It is Type 0 for all these devices. The default is 00h, indicating a “endpoint device”. CB_BAR Intel® Quick Data Base Address Register.
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Integrated I/O (IIO) Configuration Registers 14.4.10 SVID Type: Bus: Offset: CFG 0 0x2c Bit Attr Default 15:0 RW_O 0x8086 PortID: Device: N/A 4Function:0-7 Description vendor_identification_number: 14.4.11 The default value specifies Intel. Each byte of this register will be writeable once. Second and successive writes to a byte will have no effect.
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Integrated I/O (IIO) Configuration Registers 14.4.14 INTPIN Type: Bus: Offset: Bit 7:0 14.4.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x60 Attr PortID: Device: Default N/A 4Function:0 Description enable_no_snoop: 9:9 RWS 0x0 This bit is akin to the NoSnoop enable bit in the PCI Express capability register, only that this bit is controlled by bios rather than OS. When set, the no snoop optimization is enabled (provided the equivalent bit in the PCIExpress DEVCON register is set) on behalf of Intel® Quick Data DMA otherwise it is not.
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Integrated I/O (IIO) Configuration Registers 14.4.18 MSIXMSGCTL MSI-X Message Control.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x88 Attr Default PortID: Device: N/A 4Function:0-7 Description table_bir: 2:0 14.4.21 RO 0x0 Intel® Quick Data DMA BAR is at offset 10h in the DMA config space and hence this register is 0. CAPID The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x92 Attr PortID: Device: Default N/A 4Function:0-7 Description device_port_type: 7:4 RO 0x9 This field identifies the type of device. It is set to for the DMA to indicate root complex integrated endpoint device. capability_version: 3:0 14.4.24 RO 0x2 This field identifies the version of the PCI Express capability structure. Set to 2h for PCI Express and DMA devices for compliance with the extended base registers.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x94 PortID: Device: Bit Attr Default 4:3 RO 0x0 N/A 4Function:0-7 Description phantom_functions_supported: Intel® Quick Data DMA does not support phantom functions. max_payload_size: 2:0 RO 0x0 Intel® Quick Data DMA supports max 128B on writes to PCIExpress 14.4.25 DEVCON The PCI Express Device Control register controls PCI Express specific capabilities parameters associated with the device.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x98 Bit Attr Default 2:2 RO 0x0 PortID: Device: N/A 4Function:0-7 Description fatal_error_reporting_enable: N/A for Intel® Quick Data DMA non_fatal_error_reporting_enable: 1:1 RO 0x0 N/A for Intel® Quick Data DMA correctable_error_reporting_enable: 0:0 RO 0x0 N/A for Intel® Quick Data DMA 14.4.
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Integrated I/O (IIO) Configuration Registers 14.4.27 DEVCAP2 Type: Bus: Offset: CFG 0 0xb4 PortID: Device: N/A 4Function:0-7 Bit Attr Default Description 31:5 RV - Reserved. 4:4 RO 0x1 completion_timeout_disable_supported: 3:0 RO 0x0 completion_timeout_values_supported: Not Supported 14.4.28 DEVCON2 Type: Bus: Offset: Bit 324 CFG 0 0xb8 Attr Default PortID: Device: N/A 4Function:0-7 Description 15:5 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers 14.4.29 PMCAP Power Management Capability. The PM Capabilities Register defines the capability ID, next pointer and other power management related support. The following PM registers /capabilities are added for software compliance. Type: Bus: Offset: CFG 0 0xe0 PortID: Device: Bit Attr Default 31:27 RO 0x0 N/A 4Function:0-7 Description pme_support: Bits 31, 30 and 27 must be ‘0’. PME is not supported in this device/function.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0xe4 PortID: Device: Bit Attr Default 23:23 RO 0x0 N/A 4Function:0-7 Description bus_power_clock_control_enable: Not relevant for I/OxAPIC b2_b3_support: 22:22 RO 0x0 21:16 RV - 15:15 RO 0x0 Not relevant for I/OxAPIC Reserved.
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Integrated I/O (IIO) Configuration Registers 14.4.31 DMAUNCERRSTS DMA Cluster Uncorrectable Error Status. Type: Bus: Offset: CFG 0 0x148 PortID: Device: Bit Attr Default Description 31:13 RV - Reserved. 12:12 RW1CS 0x0 11:11 RV - N/A 4Function:0 syndrome: Multiple errors 14.4.32 Reserved. 10:10 RW1CS 0x0 read_address_decode_error_status: 9:8 RV - Reserved. 7:7 RW1CS 0x0 rd_cmpl_header_error_status: 6:4 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers This register controls severity of uncorrectable DMA unit errors between fatal and nonfatal. Type: Bus: Offset: CFG 0 0x150 Bit Attr Default 31:13 RV - PortID: Device: N/A 4Function:0 Description Reserved. syndrome: 12:12 RWS 0x0 Multiple errors 14.4.34 11:11 RV - Reserved. 10:10 RWS 0x0 read_address_decode_error_severity: 9:8 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x160 Attr Default PortID: Device: N/A 4Function:0 Description global_error_pointer: 3:0 14.4.36 ROS_V 0x0 Points to one of 8 possible sources of uncorrectable errors - DMA channels 07 and DMA core errors - as the source of the first error. The DMA channel errors are logged in CHANERRx_INT registers and DMA core errors are logged in the DMAUNCERRSTS register.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x180 Attr PortID: Device: Default N/A 4Function:0-7 Description cmp_addr_err: 12:12 RW1CS 0x0 Completion Address Error. The DMA channel sets this bit indicating that the completion address register was configured to an illegal address or has not been configured. desc_len_err: 11:11 RW1CS 0x0 Descriptor Length Error. The DMA channel sets this bit indicating that the current transfer has an illegal length field value.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x180 PortID: Device: Attr Default N/A 4Function:0-7 Description descriptor_error: 3:3 RW1CS The DMA channel sets this bit indicating that the current transfer has encountered an error (not otherwise covered under other error bits) when reading or executing a DMA descriptor. When this bit has been set and the channel returns to the Halted state, the address of the failed descriptor is in the Channel Status register.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x184 PortID: Device: Bit Attr Default Description 14:14 RV - Reserved. N/A 4Function:0-7 mask13_0: 13:0 14.4.38 RWS 0x0 This register is a bit for bit mask for the CHANERR_INT register 0: enable 1: disable CHANERRSEV_INT Internal DMA Channel Error Severity Registers. Type: Bus: Offset: CFG 0 0x188 PortID: Device: Bit Attr Default 31:19 RV - N/A 4Function:0-7 Description Reserved.
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Integrated I/O (IIO) Configuration Registers 14.4.39 CHANERRPTR DMA Channel Error Pointer. Type: Bus: Offset: CFG 0 0x18c PortID: Device: Bit Attr Default Description 7:5 RV - Reserved. N/A 4Function:0-7 dma_chan_err_pointer: 4:0 14.5 ROS_V 0x0 Points to the first uncorrectable, unmasked error logged in the CHANERR_INT register.
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Integrated I/O (IIO) Configuration Registers Register name Offset CHANERRMSK 0xac 32 DCACTRL 0xb0 32 DCA_VER 0x100 8 DCA_REQID_OFFSET 0x102 16 QPI_CAPABILITY 0x108 16 PCIE_CAPABILITY 0x10a 16 QPI_CAP_ENABLE 0x10c 16 PCIE_CAP_ENABLE 0x10e 16 APICID_TAG_MAP 0x110 64 DCA_REQID0 0x180 32 DCA_REQID1 14.5.1 Size 0x184 32 MSGADDR 0x2000 32 MSGUPADDR 0x2004 32 MSGDATA 0x2008 32 VECCTRL 0x200c 32 PENDINGBITS 0x3000 32 CHANCNT Channel Count.
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Integrated I/O (IIO) Configuration Registers 14.5.2 XFERCAP Transfer Capacity. The Transfer Capacity specifies the minimum of the maximum DMA transfer size supported on all channels. Type: Bus: Offset: MEM 0 0x1 PortID: Device: Bit Attr Default Description 7:5 RV - Reserved. 8’h7e 4Function:0-7 trans_size: 4:0 14.5.3 RO 0x14 Transfer size. This field specifies the number of bytes that may be specified in a DMA descriptor’s Transfer Size field.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x3 Attr Default PortID: Device: 8’h7e 4Function:0-7 Description intp_sts: 1:1 RO 0x0 Interrupt Status. This bit is set whenever the bit in the Attention Status register is set. This bit is not used by software in MSI-X mode and is a don’t care. mstr_intp_en: 0:0 14.5.5 RW 0x0 Master Interrupt Enable. Setting this bit enables the generation of an interrupt in legacy interrupt mode.
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Integrated I/O (IIO) Configuration Registers 14.5.7 INTRDELAY Interrupt Delay. Type: Bus: Offset: MEM 0 0xc PortID: Device: Bit Attr Default 15:15 RO 0x1 8’h7e 4Function:0-7 Description interrupt_coalescing_supported: The IIO does support interrupt coalescing by delaying interrupt generation. 14:14 RV - Reserved. interrupt_delay_time: 13:0 14.5.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x10 Attr PortID: Device: Default 8’h7e 4Function:0-7 Description xor_raid6: 9:9 RO_V (Function 0-1) RO (Function 2-7) 0x0 If set, specifies XOR with Galios Field Multiply Parity and Quotient opcodes for RAID5 and RAID6 are supported.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x10 Attr PortID: Device: Default 8’h7e 4Function:0-7 Description xor: If set, specifies XOR opcodes are supported. Opcodes are: 3:3 RO 0x0 0x85 - original XOR Generation 0x86 - original XOR Validate Notes: These opcodes have been deprecated in Intel® Quick Data DMA v3. The DMA engine will abort if it encounters a descriptor with these opcodes.
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Integrated I/O (IIO) Configuration Registers 14.5.11 CBPRIO Intel® Quick Data DMA Priority Register. Type: Bus: Offset: 14.5.12 MEM 0 0x40 PortID: Device: Bit Attr Default Description 7:0 RO 0x0 not_used: 8’h7e 4Function:0-7 CHANCTRL The Channel Control register controls the behavior of the DMA channel when specific events occur such as completion or errors. Type: Bus: Offset: MEM 0 0x80 PortID: Device: Bit Attr Default Description 15:10 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x80 Attr Default PortID: Device: 8’h7e 4Function:0-7 Description anyerr_abrt_en: 3:3 RW_L 0x0 Any Error Abort Enable. This bit enables an abort operation when any error is encountered during the DMA transfer. When the abort occurs, the DMA channel generates an interrupt and a completion update as per the Error Interrupt Enable and Error Completion Enable bits.
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Integrated I/O (IIO) Configuration Registers Setting more than one of these bits with the same write operation will result in an Fatal error affiliated. Type: Bus: Offset: MEM 0 0x84 Bit Attr Default 7:6 RV - PortID: Device: 8’h7e 4Function:0-7 Description Reserved. reset_dma: 5:5 RW_LV 0x0 4:3 RV - Set this bit to reset the DMA channel. Setting this bit is a last resort to recover the DMA channel from a programming error or other problem such as dead lock from cache coherency protocol.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x88 Attr Default PortID: Device: 8’h7e 4Function:0-7 Description cmpdscaddr: 31:6 RO 0x0 5:3 RV - This register stores the upper address bits (64B aligned) of the last descriptor processed. The DMA channel automatically updates this register when an error or successful completion occurs. For each completion, the DMA channel over-writes the previous value regardless of whether that value has been read. Reserved.
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Integrated I/O (IIO) Configuration Registers 14.5.17 CHANSTS_1 Channel Status 1 Register. The Channel Status Register records the address of the last descriptor completed by the DMA channel. Refer to Intel® Quick Data Architecture Specification for special hardware requirements when software reads this register. Type: Bus: Offset: Bit MEM 0 0x8c Attr Default PortID: Device: 8’h7e 4Function:0-7 Description cmpdscaddr: 31:0 14.5.
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Integrated I/O (IIO) Configuration Registers 14.5.20 CHANCMP_0 Channel Completion Address 0 Register. This register specifies the address where the DMA channel writes the completion status upon completion or an error condition that is, it writes the contents of the CHANSTS register to the destination as pointed by the CHANCMP register. Type: Bus: Offset: Bit MEM 0 0x98 Attr Default PortID: Device: 8’h7e 4Function:0-7 Description chcmpladdr_lo: 14.5.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: MEM 0 0xa8 Bit Attr 17:17 RW1CS (Function 0-1) RO (Function 2-7) PortID: Device: Default 8’h7e 4Function:0-7 Description xorqerr: 0x0 The hardware sets this bit when the Q validation part of the XOR with Galois Field Multiply Validate operation fails.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0xa8 Attr PortID: Device: Default 8’h7e 4Function:0-7 Description cdata_parerr: 6:6 RW1CS 0x0 Chipset Data Parity Error. The DMA channel sets this bit indicating that the current transfer has encountered a parity error reported by the chipset. When this bit has been set, the address of the failed descriptor is in the Channel Status register. chancmd_err: 5:5 RW1CS 0x0 CHANCMD Error.
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Integrated I/O (IIO) Configuration Registers 14.5.23 CHANERRMSK Channel Error Mask Register. Type: Bus: Offset: MEM 0 0xac PortID: Device: 8’h7e 4Function:0-7 Bit Attr Default Description 31:19 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: 14.5.26 MEM 0 0x100 PortID: Device: Bit Attr Default Description 3:0 RO 0x0 minor_revision: 8’h7e 4Function:0-7 DCA_REQID_OFFSET DCA Requester ID Offset. Type: Bus: Offset: MEM 0 0x102 Bit Attr Default 15:0 RO 0x180 PortID: Device: 8’h7e 4Function:0-7 Description dca_reqid_regs: registers are at offset 180h 14.5.27 QPI_CAPABILITY Intel® QPI Compatibility Register.
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Integrated I/O (IIO) Configuration Registers 14.5.29 QPI_CAP_ENABLE Intel® QPI Capability Enable Register. Type: Bus: Offset: MEM 0 0x10c PortID: Device: Bit Attr Default Description 15:1 RV - Reserved. 8’h7e 4Function:0-7 enable_prefetch_hint: 0:0 14.5.30 RW 0x0 When set in function 0, DCA on Intel® QPI is enabled, else disabled. IIO hardware does not use this bit from functions 1-7.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x110 Attr Default PortID: Device: 8’h7e 4Function:0-7 Description tag_map_4: This field is used by the Intel® Quick Data DMA engine to populate Tag field bit 4 of the memory write transaction it issues with either 1, 0, or a selected APICID bit.
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Integrated I/O (IIO) Configuration Registers 14.5.32 DCA_REQID[0:1] Global DCA Requester ID Table Registers. Type: Bus: Offset: Bit MEM 0 0x180 Attr , 0x184 Default PortID: Device: 8’h7e 4Function:0-7 Description last: 31:31 RO 0x0 30:30 RV - This bit is set only in the last RequesterID register for this port. Thus, it identifies that this is the last DCA RequesterID register for this port. Reserved.
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Integrated I/O (IIO) Configuration Registers 14.5.34 MSGUPADDR MSI-X Upper Address Registers. Type: Bus: Offset: Bit MEM 0 0x2004 Attr Default PortID: Device: 8’h7e 4Function:0-7 Description chmsgupaddr_const: 31:0 14.5.35 RW_V 0x0 Reserved to 0 because does not apply to IA. This field is RW for compatibility reason only. MSGDATA MSI-X Data Registers. Type: Bus: Offset: Bit MEM 0 0x2008 Attr Default PortID: Device: 8’h7e 4Function:0-7 Description chmsgdata: 31:0 14.5.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: MEM 0 0x3000 Bit Attr Default 31:1 RO 0x0 PortID: Device: 8’h7e 4Function:0-7 Description chmsipendcnst: unused chmsipend: 0:0 14.6 RW_V 0x0 Pending Bit (when set) indicates that the DMA engine has a pending MSI-X message for the DMA Channel. This bit is cleared by hardware as soon as it issues the MSI-X message.
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Integrated I/O (IIO) Configuration Registers Register name Offset Size GENPROTRANGE1_BASE 0xb0 64 GENPROTRANGE1_LIMIT 0xb8 64 GENPROTRANGE2_BASE 0xc0 64 GENPROTRANGE2_LIMIT 0xc8 64 TOLM 0xd0 32 TOHM 0xd4 64 NCMEM_BASE 0xe0 64 NCMEM_LIMIT 0xe8 64 MENCMEM_BASE 0xf0 64 MENCMEM_LIMIT 0xf8 64 CPUBUSNO 0x108 32 LMMIOL_BASE 0x10c 16 LMMIOL_LIMIT 0x10e 16 LMMIOH_BASE 0x110 64 LMMIOH_LIMIT 0x118 64 GENPROTRANGE0_BASE 0x120 64 GENPROTRANGE0_LIMIT 0x128 64 CIPCTRL
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Integrated I/O (IIO) Configuration Registers 14.6.1 Register name Offset Size IRPEGCREDITS 0x840 64 IRP_MISC_DFX2 0x850 32 IRP_MISC_DFX3 0x854 32 VID Type: Bus: Offset: CFG 0 0x0 PortID: Device: Bit Attr Default 15:0 RO 0x8086 N/A 5Function:0 Description vendor_identification_number: The value is assigned by PCI-SIG to Intel. 14.6.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x4 PortID: Device: Bit Attr Default 5:5 RO 0x0 N/A 5Function:0 Description vga_palette_snoop_enable: Not applicable to internal devices. Hardwired to 0. memory_write_and_invalidate_enable: 4:4 RO 0x0 Not applicable to internal devices. Hardwired to 0. special_cycle_enable: 3:3 RO 0x0 Not applicable. Hardwired to 0.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x6 PortID: Device: Bit Attr Default 8:8 RO 0x0 N/A 5Function:0 Description master_data_parity_error: Hardwired to 0 fast_back_to_back: 7:7 RO 0x0 6:6 RV - 5:5 RO 0x0 Not applicable to PCI Express. Hardwired to 0. Reserved. pci66mhz_capable: Not applicable to PCI Express. Hardwired to 0.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x9 PortID: Device: Bit Attr Default 15:8 RO_V 0x80 N/A 5Function:0 Description sub_class: Generic Device register_level_programming_interface: 7:0 RO_V 0x0 Set to 00h for all non-APIC devices. 14.6.7 CLSR Type: Bus: Offset: Bit CFG 0 0xc Attr PortID: Device: Default N/A 5Function:0 Description cacheline_size: 7:0 14.6.8 RW 0x0 This register is set as RW for compatibility reasons only.
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Integrated I/O (IIO) Configuration Registers 14.6.10 SDID Type: Bus: Offset: CFG 0 0x2e Bit Attr Default 15:0 RW_O 0x0 PortID: Device: N/A 5Function:0 Description subsystem_device_identification_number: Assigned by the subsystem vendor to uniquely identify the subsystem 14.6.11 CAPPTR Type: Bus: Offset: CFG 0 0x34 Bit Attr Default 7:0 RO 0x40 PortID: Device: N/A 5Function:0 Description capability_pointer: Points to the first capability structure for the device. 14.6.
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Integrated I/O (IIO) Configuration Registers 14.6.14 PXPCAPID Type: Bus: Offset: CFG 0 0x40 Bit Attr Default 7:0 RO 0x10 PortID: Device: N/A 5Function:0 Description capability_id: Provides the PCI Express capability ID assigned by PCI-SIG. 14.6.15 PXPNXTPTR Type: Bus: Offset: CFG 0 0x41 Bit Attr Default 7:0 RO 0x0 PortID: Device: N/A 5Function:0 Description next_ptr: This field is set to the PCI PM capability. 14.6.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x80 Attr PortID: Device: Default N/A 5Function:0 Description clr_hdrmfd: When set, function#0 with in the indicated device shows a value of 0 for bit 7 of the HDR register, indicating a single function device. BIOS sets this bit, when only function#0 is visible within the device, either because SKU reasons or BIOS has hidden all functions but function#0 within the device via the DEVHIDE register.
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Integrated I/O (IIO) Configuration Registers 14.6.20 TSEG Type: Bus: Offset: Bit CFG 0 0xa8 Attr PortID: Device: Default N/A 5Function:0 Description limit: 63:52 RW_LB Indicates the limit address which is aligned to a 1MB boundary. Any access to falls within TSEG.BASE[31:20] <= Addr[31:20] <= TSEG.LIMIT[31:20] is considered to target the Tseg region and IIO aborts it. 0x0 Note that address bits 19:0 are ignored and not compared.
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Integrated I/O (IIO) Configuration Registers 14.6.22 GENPROTRANGE[1:0]_LIMIT Generic Protected Memory Range X Limit Address. (X = 1, 0) Type: Bus: Offset: CFG 0 0xb8 , 0x128 PortID: Device: Bit Attr Default Description 63:51 RV - rsvd: N/A 5Function:0 limit_address: 14.6.23 50:16 RW_LB 0x0 15:0 RV 0x0 [50:16] of generic memory address range that needs to be protected from inbound dma accesses. The protected memory range can be anywhere in the memory space addressable by the processor.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0xc8 PortID: Device: Bit Attr Default Description 63:51 RV - Reserved: N/A 5Function:0 limit_address: 14.6.25 50:16 RW_LB 0x0 15:0 RV - [50:16] of generic memory address range that needs to be protected from inbound dma accesses. The protected memory range can be anywhere in the memory space addressable by the processor. Addresses that fall in this range that is, GenProtRange.
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Integrated I/O (IIO) Configuration Registers 14.6.27 NCMEM_BASE Noncoherent Memory Base Address. Type: Bus: Offset: Bit CFG 0 0xe0 Attr PortID: Device: Default N/A 5Function:0 Description addr: 14.6.28 63:26 RW_LB 0x3ffffffff 25:0 RV - Noncoherent memory base address. Describes the base address of a 64MB aligned dram memory region on Intel® QPI that is not coherent. Address bits [63:26] of an inbound address if it satisfies ’NcMem.Base[63:26] <= A[63:26] <= NcMem.
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Integrated I/O (IIO) Configuration Registers 14.6.29 MENCMEM_BASE Intel® Management Engine (Intel® ME) noncoherent memory base address. Type: Bus: Offset: Bit CFG 0 0xf0 Attr PortID: Device: Default N/A 5Function:0 Description addr: 14.6.30 63:19 RW_LB 0x1fffffffffff Intel® Management Engine (Intel® ME) UMA Base Address. Indicates the base address which is aligned to a 1MB boundary. Bits [63:19] corresponds to A[63:19] address bits. 18:0 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x108 Attr Default PortID: Device: N/A 5Function:0 Description bus1: 15:8 RW_LB 0x0 Is the internal bus# of rest of uncore. All devices are claimed by UBOX on behalf of this component. Devices that do not exist within this component on this bus number are master aborted by the UBOX. bus0: 7:0 14.6.32 RW_LB 0x0 Is the internal bus# of IIO and also PCH.
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Integrated I/O (IIO) Configuration Registers 14.6.34 LMMIOH_BASE Local MMIO High Base. Type: Bus: Offset: CFG 0 0x110 PortID: Device: Bit Attr Default Description 63:51 RV - Reserved. N/A 5Function:0 base: 50:26 RW_LB 0x0 Corresponds to A[50:26] of MMIOH base. An inbound memory address that satisfies local MMIOH base [50:26] <= A[63:26] <= local MMIOH limit [50:26] is treated as a local peer-to-peer transaction that does not cross the coherent interface. Notes: Setting LMMIOH.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x140 Attr Default PortID: Device: N/A 5Function:0 Description flushpendwr: 31:31 RW 0x0 30:30 RW 0x0 29:29 RV - Whenever this bit is written to 1 (regardless what the current value of this bit is), IRP block first clears bit 0 in CIPSTS register and takes a snapshot of the currently pending write transactions to dram in Write Cache, wait for them to complete fully (that is, deallocate the corresponding Write Cache/RRB
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x140 Attr Default PortID: Device: N/A 5Function:0 Description rrbsize: Specifies the number of entries used in each half of the write cache. The default is to use all entries.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x140 Attr Default PortID: Device: N/A 5Function:0 Description pcirdcurr_drduc_sel: 0:0 14.6.37 RW 0x0 On Inbound Coherent Reads selection of RdCur or DRd is done based on this configuration bit. 0: PCIRdCurrent 1: DRd.UC CIPSTS Coherent Interface Protocol Status. Type: Bus: Offset: CFG 0 0x144 PortID: Device: Bit Attr Default Description 31:3 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x148 Attr Default PortID: Device: N/A 5Function:0 Description dcalt6: 28:26 RW 0x0 25:23 RW 0x0 For a TPH/DCA request, specifies the target NodeID[2:0] when the inverted Tag[2:0] is 6 dcalt5: For a TPH/DCA request, specifies the target NodeID[2:0] when the inverted Tag[2:0] is 5 dcalt4: 22:20 RW 0x0 19:17 RW 0x0 For a TPH/DCA request, specifies the target NodeID[2:0] when the inverted Tag[2:0] is 4 dcalt3: For a T
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x14c Attr Default PortID: Device: N/A 5Function:0 Description dis_intx_route2ich: 25:25 RW 0x0 24:19 RV - When this bit is set. Local INTx messages received from the Intel® Quick Data DMA/PCI Express ports are not routed to legacy PCH - they are either converted into MSI via the integrated I/OxAPIC (if the I/OxAPIC mask bit is clear in the appropriate entries) or cause no further action (when mask bit is set) Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x154 Attr Default PortID: Device: N/A 5Function:0 Description nmi: 30:30 RW1CS 0x0 This is set whenever IIO forwards a VLW from PCH that had the NMI bit asserted 29:7 RV - Reserved. 6:6 RO_V 0x0 nmi_ras_evt_pending: 5:5 RO_V 0x0 smi_ras_evt_pending: 4:4 RO_V 0x0 intr_evt_pending: 3:2 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x184 PortID: Device: Bit Attr Default Description 14:8 RV - Reserved. N/A 5Function:0 hpa_limit: Represents the host processor addressing limit 7:4 RW_LB 0xa 0000: 2^36 (that is, bits 35:0) 0001: 2^37 (that is, bits 36:0) ...
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x18c Attr Default PortID: Device: N/A 5Function:0 Description lt: Controls the rate at which the LRU buckets should degrade. 10:7 RW_LB 0x7 If we are in “Cycles” mode (LRUCTRL = 0), then we will degrade LRU after 256 * N requests where N is the value of this field. If we are in “Request” mode (LRUCTRL = 1), then we will degrade LRU after 16 * N cycles where N is the value of this field.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x194 PortID: Device: N/A 5Function:0 Bit Attr Default Description 24:23 RW 0x0 rangesel_iou23_upper_x2: 22:15 RV - Reserved. 14:13 RW 0x0 rangesel_me: 12:11 RW 0x0 rangesel_cb: 10:9 RW 0x0 rangesel_intr: 8:1 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers 14.6.45 VTUNCERRSTS Intel® VT-d Uncorrectable Error Status. Type: Bus: Offset: Bit CFG 0 0x1a8 Attr Default PortID: Device: N/A 5Function:0 Description vtderr: 31:31 RW1CS 0x0 30:9 RV - When set, this bit is set when a Intel® VT-d spec defined error has been detected (and logged in the Intel® VT-d fault registers) Reserved1: Reserved.
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Integrated I/O (IIO) Configuration Registers 14.6.46 VTUNCERRMSK Intel® VT-d Uncorrectable Error Mask. Mask out error reporting to IIO. Bit 31 should always be set to 1. We recommend that the other bits be left as zero so these internal errors are reported out. Setting bits will not prevent any error collecting INSIDE of Intel® VT-d in the Intel® VT-d Fault Recording Registers.
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Integrated I/O (IIO) Configuration Registers 14.6.47 VTUNCERRSEV Intel® VT-d Uncorrectable Error Severity. Type: Bus: Offset: Bit CFG 0 0x1b0 Attr Default PortID: Device: N/A 5Function:0 Description vtderr_sev: 31:31 RWS 0x0 When set, this bit escalates reporting of Intel® VT-d spec defined errors, as FATAL errors. When clear, those errors are escalated as Nonfatal errors. Setting this bit to a 1 can allow a guest VM to trigger an unrecoverable FATAL error at the platform.
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Integrated I/O (IIO) Configuration Registers 14.6.48 VTUNCERRPTR Intel® VT-d Uncorrectable Error Pointer. Type: Bus: Offset: CFG 0 0x1b4 Bit Attr Default 7:5 RV - PortID: Device: N/A 5Function:0 Description Reserved1: Reserved. vt_uncferr_ptr: 4:0 ROS_V 0x0 This field points to which of the unmasked uncorrectable errors happened first.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x1c0 Attr Default PortID: Device: N/A 5Function:0 Description en_poismsg_spec_behavior: A received poison packet is treated as a Fatal error if its severity bit is set, but treated as a correctable if the severity bit is cleared and logged in both the UNCERRSTS register and the Advisory Non-Fatal Error bit in the CORERRSTS register.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x1c0 Attr Default PortID: Device: N/A 5Function:0 Description showportid: A Port Identifier that identifies which PCI Express port a transaction comes from will be placed in the AD Ring TNID[2:0] field of the request packet, when enabled. This field is normally used for DCAHint and is not used for normal demand read. Since there are up to 11 specific ports, then Port ID is encoded in 4 bits.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x1c0 Attr Default PortID: Device: N/A 5Function:0 Description disable_all_allocating_flows: When this bit is set, IIO will no more issue any new inbound IDI command that can allocate into LLC. Instead, all the writes will use one of the nonallocating commands - PCIWiL/PCIWiLF/PCINSWr/PCINSWrF. Software should set this bit only when no requests are being actively issued on IDI.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x1c0 Attr Default PortID: Device: N/A 5Function:0 Description dmi_vc1_vt_d_fetch_ordering: 15:15 RW 0x0 This mode is to allow VC1 Intel® VT-d conflicts with outstanding VC0 Intel® VT-d reads on IDI to be pipelined. This can occur when Intel® VT-d tables are shared between Intel® VT (VC1) and other devices. To ensure QoS the Intel® VT-d reads from VC1 need to be issued in parallel with nonIsoc accesses to the same cacheline.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x1c0 Attr Default PortID: Device: N/A 5Function:0 Description legacy_port: Sockets where the NodeID = 0 are generally identified as having the legacy DMI port. But there is still a possibility that another socket also has a NodeID = 0. The system is configured by software to route legacy transactions to the correct socket.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x1c0 Attr Default PortID: Device: N/A 5Function:0 Description enable_isa_hole: 0:0 RW_LB 0x0 When this bit is set, inbound DMA accesses to the ISA Hole region are aborted by IIO. If clear, inbound DMA accesses to the ISA hole region are forwarded to dram. Refer to the Address Map chapter for more details.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x290 Attr Default PortID: Device: N/A 5Function:0 Description commandbit: 2:2 RW_L 0x0 Writing a '1' to this bit will enable protection. Writing a '0' to this bit will disable protection. protregsts: 1:1 RO 0x0 0:0 RW_O 0x0 IIO sets this bit when the protection has been enabled in hardware and for all practical purposes this should be immediate. When protection is disabled, then this bit is clear lock: 14.6.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x800 Bit Attr Default 24:24 RW_L 0x1 PortID: Device: N/A 5Function:0 Description enable_vtd_reuse: disregards the reuse hint from vtd. results in a fetch to CBO every time aging_timer_rollover: 23:22 RW_L 0x0 0: 1: 2: 3: disabled 32us 128us 512us There is an error of abt + 100%.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x804 PortID: Device: Bit Attr Default Description 31:14 RV - Reserved: N/A 5Function:0 13:13 RW_L 0x1 use_bgf_cdt_for_bgf_empty: 12:12 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers 14.6.54 IRP[0:1]DBGRING0 Type: Bus: Offset: 14.6.55 CFG 0 0x818, 0x820 Bit Attr Default Description 63:0 RO 0x0 dbg_ring_sig: N/A 5Function:0 IRP[0:1]DBGRING1 Type: Bus: Offset: 14.6.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x830, 0x834 Attr Default PortID: Device: N/A 5Function:0 Description orng_ln_8_sel: Select the source of data to be driven to the next cluster on lane 8.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x830, 0x834 Attr Default PortID: Device: N/A 5Function:0 Description orng_ln_3_sel: Select the source of data to be driven to the next cluster on lane 3.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x840 PortID: Device: Bit Attr Default Description 63:34 RV - Reserved. N/A 5Function:0 fifo_cdt_threshold: 33:30 RW_L 0x8 The IRP has a FIFO on the inbound path feeding the R2PCIe. This is only a staging FIFO to assist in the flow of inbound traffic. This field specifies the number of FIFO entries to use in this IRP staging FIFO.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x840 PortID: Device: Bit Attr Default Description 5:3 RW_L 0x6 cbo_ndr_cdt_threshold: N/A 5Function:0 qpi_ndr_cdt_threshold: These are the total credits allocated for NDR packets. 2:0 RW_L 0x4 NDR to Intel® QPI requests If more than one credit is used, a credit from the vc0_rd_cdt_threshold pool will be used. A credit from this pool will be used.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x850 Attr Default PortID: Device: N/A 5Function:0 Description ctagentry_avail_mask: This feature will mask out write cache entries in strides of 8.
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Integrated I/O (IIO) Configuration Registers 14.6.60 IRP_MISC_DFX3 Type: Bus: Offset: CFG 0 0x854 Bit Attr Default 31:31 RW_L 0x0 PortID: Device: N/A 5Function:0 Description dbg_entry_num_sel_bit6: Notes: Locked by DBGBUSLCK disable_wr_merge_flush_hang_fix: 30:29 RW_L 0x0 Performance optimization to induce a flush when a write merged entry has P F allocated to a different entry. Normally aging timer rollover would have to trigger the flush.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x854 Attr Default PortID: Device: N/A 5Function:0 Description disable_trigger_pf_ack2_fix: Defeature mode to disable fix related to issuing second PF ack for a write merged entry. This is only for IRP1. 12:12 RW_L 0x0 0: Enable changes 1: Disable changes Locked by DBGBUSLCK 11:11 RV - 10:10 RW_L 0x0 9:0 RV - Reserved: lterr_log_dis: Disable error logging for LT transactions. 14.
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Integrated I/O (IIO) Configuration Registers Register name Size NONISOCH_INV_CMP_EVTCTRL 0xa0 32 NONISOCH_INVEVTDATA 0xa4 32 VTD0_INV_COMP_EVT_ADDR 0xa8 32 VTD0_INV_COMP_EVT_UPRADDR 0xac 32 VTD0_INTR_REMAP_TABLE_BASE 400 Offset 0xb8 64 VTD0_FLTREC0_GPA 0x100 64 VTD0_FLTREC0_SRC 0x108 64 VTD0_FLTREC1_GPA 0x110 64 VTD0_FLTREC1_SRC 0x118 64 VTD0_FLTREC2_GPA 0x120 64 VTD0_FLTREC2_SRC 0x128 64 VTD0_FLTREC3_GPA 0x130 64 VTD0_FLTREC3_SRC 0x138 64 VTD0_FLTREC4_GPA 0x140
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Integrated I/O (IIO) Configuration Registers Register name 14.7.1 Offset Size VTD1_INV_COMP_EVT_UPRADDR 0x10ac 32 VTD1_INTR_REMAP_TABLE_BASE 0x10b8 64 VTD1_FLTREC0_GPA 0x1100 64 VTD1_FLTREC0_SRC 0x1108 64 VTD1_INVADDRREG 0x1200 64 VTD1_IOTLBINV 0x1208 64 VTD[0:1]_VERSION Intel® VT-d Version Number. Type: Bus: Offset: 14.7.2 MEM 0 0x0 , 0x1000 PortID: Device: Bit Attr Default Description 31:8 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: MEM 0 0x8, 0x1008 Bit Attr Default 33:24 RO 0x10 PortID: Device: 8’h7e 5Function:0 Description fault_recording_register_offset: Fault registers are at offset 100h 23:23 RO 0x0 spatial_separation: zlr: 22:22 RO 0x1 Zero-length DMA requests to write-only pages supported. mgaw: 21:16 RO_V 0x2f This register is set by the processor-based on the setting of the GPA_LIMIT register.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x10 Attr PortID: Device: , 0x1010 Default 8’h7e 5Function:0 Description maximum_handle_mask_value: 23:20 RO 0xf 19:18 RV - IIO supports all 16 bits of handle being masked. Note IIO always performs global interrupt entry invalidation on any interrupt cache invalidation command and h/w never really looks at the mask value. Reserved.
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Integrated I/O (IIO) Configuration Registers 14.7.4 VTD[0:1]_GLBCMD Intel® VT-d Global Command. Type: Bus: Offset: Bit MEM 0 0x18, 0x1018 Attr Default PortID: Device: 8’h7e 5Function:0 Description translation_enable: 31:31 RW 0x0 Software writes to this field to request hardware to enable/disable DMAremapping hardware.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x18, 0x1018 Attr Default PortID: Device: 8’h7e 5Function:0 Description queued_invalidation_enable: 26:26 RW 0x0 Software writes to this field to enable queued invalidations.0: Disable queued invalidations. In this case, invalidations must be performed through the Context Command and IOTLB Invalidation Unit registers. 1: Enable use of queued invalidations.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x18, 0x1018 Attr Default PortID: Device: 8’h7e 5Function:0 Description cfi: 14.7.5 23:23 RW 0x0 22:0 RV - Compatibility Format Interrupt Software writes to this field to enable or disable Compatibility Format interrupts on Intel® 64 platforms. The value in this field is effective only when interrupt-remapping is enabled and Legacy Interrupt Mode is active. 0: Block Compatibility format interrupts.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x1c, 0x101c Attr Default PortID: Device: 8’h7e 5Function:0 Description interrupt_remapping_table_pointer_status: 24:24 RO_V 0x0 This field indicates the status of the interrupt remapping table pointer in hardware. This field is cleared by hardware when software sets the SIRTP field in the Global Command register.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x28 Attr , 0x1028 Default PortID: Device: 8’h7e 5Function:0 Description icc: 63:63 RW_V 0x0 Invalidate Context Entry Cache Software requests invalidation of context-cache by setting this field. Software must also set the requested invalidation granularity by programming the CIRG field. Software must read back and check the ICC field to be clear to confirm the invalidation is complete.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x28 Attr , 0x1028 Default PortID: Device: 8’h7e 5Function:0 Description domain_id: 15:0 14.7.8 RW Indicates the id of the domain whose context-entries needs to be selectively invalidated. S/W needs to program this for both domain and device selective invalidates. The processor ignores bits 15:8 since it supports only a 8 bit Domain ID. 0x0 VTD[0:1]_FLTSTS Intel® VT-d Fault Status.
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Integrated I/O (IIO) Configuration Registers 14.7.9 NONISOCH_FLTEVTCTRL Fault Event Control. Type: Bus: Offset: Bit MEM 0 0x38 Attr PortID: Device: Default 8’h7e 5Function:0 Description fault_nonisoch_msgmsk: 31:31 RW 0x1 1: Hardware is prohibited from issuing interrupt message requests. 0: Software has cleared this bit to indicate interrupt service is available.
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Integrated I/O (IIO) Configuration Registers 14.7.11 VTD[0:1]_FLTEVTADDR Intel® VT-d Fault Event Address. Type: Bus: Offset: Bit MEM 0 0x40, 0x1040 Attr Default PortID: Device: 8’h7e 5Function:0 Description interrupt_address: 31:2 RW 0x0 1:0 RV - The interrupt address is interpreted as the address of any other interrupt from a PCI Express port. Reserved (Rsvd): Reserved. 14.7.12 VTD[0:1]_FLTEVTUPRADDR Type: Bus: Offset: 14.7.
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Integrated I/O (IIO) Configuration Registers 14.7.14 VTD[0:1]_PROT_LOW_MEM_BASE Intel® VT-d Protected Memory Low Base. Type: Bus: Offset: Bit MEM 0 0x68 Attr , 0x1068 Default PortID: Device: 8’h7e 5Function:0 Description addr: 14.7.
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Integrated I/O (IIO) Configuration Registers 14.7.17 VTD[0:1]_PROT_HIGH_MEM_LIMIT Intel® VT-d Protected Memory High Limit. Type: Bus: Offset: Bit MEM 0 0x78 Attr , 0x1078 Default PortID: Device: 8’h7e 5Function:0 Description addr: 14.7.
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Integrated I/O (IIO) Configuration Registers 14.7.20 VTD[0:1]_INV_QUEUE_ADD Intel® VT-d Invalidation Queue Address. Type: Bus: Offset: MEM 0 0x90 , 0x1090 Bit Attr Default 63:12 RW 0x0 PortID: Device: 8’h7e 5Function:0 Description invreq_queue_base_address: This field points to the base of size-aligned invalidation request queue. 11:3 RV - Reserved. queue_size: 2:0 14.7.21 RW 0x0 This field specifies the length of the invalidation request queue.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0xa0 Attr PortID: Device: Default 8’h7e 5Function:0 Description inval_nonisoch_msi_pend: 14.7.23 30:30 RO_V 0x0 29:0 RO 0x0 Hardware sets the IP field whenever it detects an interrupt condition. Interrupt condition is defined as:- An Invalidation Wait Descriptor with Interrupt Flag (IF) field set completed, setting the IWC field in the Fault Status register.
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Integrated I/O (IIO) Configuration Registers 14.7.26 VTD[0:1]_INTR_REMAP_TABLE_BASE Intel® VT-d Interrupt Remapping Table Based Address. Type: Bus: Offset: Bit MEM 0 0xb8, 0x10b8 Attr Default PortID: Device: 8’h7e 5Function:0 Description intr_remap_base: 63:12 RW 0x0 This field points to the base of page-aligned interrupt remapping table. If the Interrupt Remapping Table is larger than 4 KB in size, it must be sizealigned.Reads of this field returns value that was last programmed to it.
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Integrated I/O (IIO) Configuration Registers 14.7.28 VTD0_FLTREC[0:7]_SRC, VTD1_FLTREC0_SRC Intel® VT-d Fault Record. Type: Bus: Offset: Bit MEM PortID: 8’h7e 0 Device: 5Function:0 VTD0: 0x108, 0x118, 0x128, 0x138, 0x148, 0x158, 0x168, 0x178 VTD1: 0x1108 Attr Default Description f: 63:63 RW1CS Fault. Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR, SID, FR and T fields.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x200 Attr , 0x1200 Default PortID: Device: 8’h7e 5Function:0 Description ih: 6:6 RW 0x0 5:0 RW 0x0 Invalidation Hint. The field provides hint to hardware to preserve or flush the respective nonleaf page-table entries that may be cached in hardware.0: Software may have modified both leaf and non-leaf page-table entries corresponding to mappings specified in the ADDR and AM fields.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM 0 0x208 Attr , 0x1208 Default PortID: Device: 8’h7e 5Function:0 Description iirg: 61:60 RW 0x0 59:59 RV - IOTLB Invalidation Request Granularity When requesting hardware to invalidate the I/OTLB (by setting the Intel® VT field), software writes the requested invalidation granularity through this IIRG field. Following are the encoding for the 2-bit IIRG field. 00: Reserved.
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Integrated I/O (IIO) Configuration Registers 14.8 Device 5 Function 2 Global System Control and Error Registers.
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Integrated I/O (IIO) Configuration Registers Register name Offset Size GFFERRST 0x1dc 32 GFNERRST 0x1e8 32 GNFERRST 0x1ec 32 GNNERRST 0x1f8 32 IRPP0ERRST 0x230 32 IRPP0ERRCTL 0x234 32 IRPP0FFERRST 0x238 32 IRPP0FNERRST 0x23c 32 IRPP0FFERRHD0 0x240 32 IRPP0FFERRHD1 0x244 32 IRPP0FFERRHD2 0x248 32 IRPP0FFERRHD3 0x24c 32 IRPP0NFERRST 0x250 32 IRPP0NNERRST 0x254 32 IRPP0NFERRHD0 0x258 32 IRPP0NFERRHD1 0x25c 32 IRPP0NFERRHD2 0x260 32 IRPP0NFERRHD3 0x264 32
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Integrated I/O (IIO) Configuration Registers Register name 14.8.
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Integrated I/O (IIO) Configuration Registers 14.8.2 DID Type: Bus: Offset: CFG 0 0x2 PortID: Device: Bit Attr Default 15:0 RO 0xe2a N/A 5Function:2 Description device_identification_number: Device ID values vary from function to function. Bits 15:8 are equal to 0x0E. 14.8.3 PCICMD Type: Bus: Offset: CFG 0 0x4 PortID: Device: Bit Attr Default 15:11 RV - N/A 5Function:2 Description Reserved.
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Integrated I/O (IIO) Configuration Registers 14.8.4 PCISTS Type: Bus: Offset: Bit CFG 0 0x6 Attr PortID: Device: Default N/A 5Function:2 Description detected_parity_error: 15:15 RO 0x0 14:14 RO 0x0 This bit is set when the device receives a packet on the primary side with an uncorrectable data error (including a packet with poison bit set) or an uncorrectable address/control parity error. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register.
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Integrated I/O (IIO) Configuration Registers 14.8.5 RID Type: Bus: Offset: Bit CFG 0 0x8 Attr PortID: Device: Default N/A 5Function:2 Description revision_id: 7:0 RO_V 0x0 Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in any Intel Xeon processor E7-2800/4800/8800 v2 product family Product Family function.
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Integrated I/O (IIO) Configuration Registers 14.8.8 HDR Type: Bus: Offset: CFG 0 0xe PortID: Device: Bit Attr Default 7:7 RO 0x1 N/A 5Function:2 Description multi_function_device: This bit defaults to 1b since all these devices are multifunction configuration_layout: 6:0 14.8.9 RO 0x0 This field identifies the format of the configuration header layout. It is Type 0 for all these devices. The default is 00h, indicating a “endpoint device”.
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Integrated I/O (IIO) Configuration Registers 14.8.12 INTL Type: Bus: Offset: CFG 0 0x3c PortID: Device: Bit Attr Default 7:0 RO 0x0 N/A 5Function:2 Description interrupt_line: N/A for these devices 14.8.13 INTPIN Type: Bus: Offset: CFG 0 0x3d PortID: Device: Bit Attr Default 7:0 RO 0x0 N/A 5 Function: 2 Description interrupt_pin: N/A since these devices do not generate any interrupt on their own 14.8.
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Integrated I/O (IIO) Configuration Registers 14.8.16 PXPCAP Type: Bus: Offset: Bit CFG 0 0x42 Attr PortID: Device: Default N/A 5 Function: 2 Description 15:14 RV - Reserved. 13:9 RO 0x0 interrupt_message_number_n_a: 8:8 RO 0x0 slot_implemented_n_a: device_port_type: 7:4 RO 0x9 This field identifies the type of device. It is set to for the DMA to indicate root complex integrated endpoint device. capability_version: 3:0 14.8.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x80 Attr PortID: Device: Default N/A 5 Function: 2 Description csr_acc_32b_unaligned: (C3) 9:8 RWS 00: Error Severity Level 0 (Correctable) 01: Error Severity Level 1 (Recoverable) 10: Error Severity Level 2 (Fatal) 11: Reserved Note: Inband misaligned to or sideband/PECI misaligned to configuration registers won’t be logged by this registers.
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Integrated I/O (IIO) Configuration Registers Type: CFG Bus: 0 Offset: PortID: Device: 0x8c N/A 5 Bit Attr Default 11:10 RV - Function:2 Description Reserved2: Reserved c4_master_abort_address_error: 9:8 RWS_L 00: 01: 10: 11: 0x1 Error Severity Level 0 (Correctable) Error Severity Level 1 (Recoverable) Error Severity Level 2 (Fatal) Reserved Notes: Locked by RSPLCK Reserved1: 7:0 RV Reserved. 14.8.19 MIERRSV Miscellaneous Error Severity.
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Integrated I/O (IIO) Configuration Registers This register allows remapping of the PCIe* errors to the IIO error severity. Type: Bus: Offset: CFG 0 0x94 PortID: Device: Bit Attr Default 31:6 RV - N/A 5 Function: 2 Description Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x9c Attr PortID: Device: Default N/A 5 Function: 2 Description sev0_map: 2:0 14.8.22 RWS 0x0 010: Generate NMI 001: Generate SMI/PMI 000: No inband message Others: Reserved VIRAL This register provides the option to generate viral alert upon the detection of fatal error. Note: • Bit 0 and Bit 2 must be set to b’1 to enable viral. • Bit 1 must be set to b’1 IF and ONLY IF BIOS also enables IOMCA in Viral mode.
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Integrated I/O (IIO) Configuration Registers 14.8.23 ERRPINCTL This register provides the option to configure an error pin to either as a special purpose error pin which is asserted based on the detected error severity, or as a general purpose output which is asserted based on the value in the ERRPINDAT. The assertion of the error pins can also be completely disabled by this register. Type: Bus: Offset: CFG 0 0xa4 PortID: Device: Bit Attr Default 31:6 RV - N/A 5Function:2 Description Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0xa8 Attr PortID: Device: Default N/A 5 Function: 2 Description pin0: 0:0 14.8.25 RW1CS 0x0 This bit is set upon the transition of deassertion to assertion of the Error pin. Software write 1 to clear the status. Hardware will only set this bit when the corresponding ERRPINCTL field is set to 10b. ERRPINDAT This register provides the data value when the error pin is configured as a general purpose output.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0xac Attr PortID: Device: Default N/A 5 Function: 2 Description pin0: This bit acts as the general purpose output for the Error[0] pin. Software sets/clears this bit to assert/deassert Error[0] pin. This bit applies only when ERRPINCTL[1:0] = 01; otherwise it is reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0xb0 Attr PortID: Device: Default N/A 5 Function: 2 Description vpp_enaddr: 43:0 14.8.27 RWS Assigns the VPP address of the device on the VPP interface and assigns the port address for the ports within the VPP device. There are more address bits then root ports so assignment must be spread across VPP ports.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0xbc Attr PortID: Device: Default N/A 5 Function: 2 Description vpp_tsu_thd: 11:0 14.8.29 RWS 0x9c4 Represents the high time and low time of the SCL pin. It should be set to 5uS for a 100 kHz SCL clock 5uS high time and 5uS low time. The default value represents 5 uS with an internal clock of 500 MHz.
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Integrated I/O (IIO) Configuration Registers 14.8.30 GNERRMASK Global Non-Fatal Error Mask. This register masks the reporting of non-fatal errors detected by the IIO local interfaces. An individual error control bit that is set masks error signaling of the particular local interface; software may set or clear the mask bit. Note that bit fields in this register can become reserved depending on the port configuration.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x19c Bit Attr Default 1:1 RW1CS 0x0 PortID: Device: N/A 5Function:2 Description irp1_err_msk: IRP1 Coherent Interface Error Mask irp0_err_msk: 0:0 RW1CS 0x0 IRP0 Coherent Interface Error Mask 14.8.31 GFERRMASK Global Fatal Error Mask. This register masks the reporting of fatal errors detected by the IIO local interfaces.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x1a0 Attr Default PortID: Device: N/A 5Function:2 Description pcie_err_msk: 15:5 RW1CS 0x0 4:2 RV - PCIe* Error Mask Mask bit for associated PCIe* logical ports: Bit 5: Port 0 Bit 6: n/a Bit 7: n/a Bit 8: Port 2a Bit 9: Port 2b Bit 10: Port 2c Bit 11: Port 2d Bit 12: Port 3a Bit 13: Port 3b Bit 14: Port 3c Bit 15: Port 3d Reserved1: Reserved irp1_err_msk: 1:1 RW1CS 0x0 IRP1 Coherent Interface Error Mask irp0_err_msk:
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x1a4 Bit Attr Default 25:25 RW1CS 0x0 PortID: Device: N/A 5Function:2 Description vtd_err_msk: Intel® VT-d Error Mask mi_err_msk: 24:24 RW1CS 0x0 Miscellaneous Error Mask iio_err_msk: 23:23 RW1CS 0x0 IIO Core Error Mask Reserved3: 22:21 RV Reserved dmi_err_msk: 20:20 RW1CS 0x0 DMI Error Mask Reserved2: 19:16 RV Reserved pcie_err_msk: 15:5 RW1CS 0x0 4:2 RV - PCIe* Error Mask Mask bit for associated PCIe* l
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Integrated I/O (IIO) Configuration Registers 14.8.33 GCERRST Global Corrected Error Status. This register indicates the corrected error reported to the IIO global error logic. An individual error status bit that is set indicates that a particular local interface has detected an error. Type: Bus: Offset: CFG 0 0x1a8 PortID: Device: Bit Attr Default 31:27 RV - N/A 5 Function: 2 Description Reserved4: Reserved. mc: 26:26 RW1CS 0x0 Memory Controller Error Status.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x1a8 Attr PortID: Device: Default N/A 5 Function: 2 Description pcie: 15:5 RW1CS 0x0 4:2 RV - PCIe* Error Status Associated PCIe* logical port has detected an error.
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Integrated I/O (IIO) Configuration Registers 14.8.35 GNERRST Global Nonfatal Error Status. This register indicates the non-fatal error reported to the IIO global error logic. An individual error status bit that is set indicates that a particular local interface has detected an error. Type: Bus: Offset: CFG 0 0x1c0 Bit Attr Default 31:26 RV - PortID: Device: N/A 5Function:2 Description Reserved4: Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x1c0 Bit Attr Default 1:1 RW1CS 0x0 PortID: Device: N/A 5Function:2 Description irp1_err: IRP1 Coherent Interface Error irp0_err: 0:0 RW1CS 0x0 IRP0 Coherent Interface Error 14.8.36 GFERRST Global Fatal Error Status. This register indicates the fatal error reported to the IIO global error logic. An individual error status bit that is set indicates that a particular local interface has detected an error.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x1c4 Attr Default PortID: Device: N/A 5Function:2 Description pcie: 15:5 RW1CS 0x0 4:2 RV - PCIe* Error Status Associated PCIe* logical port has detected an error.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x1c8 Attr Default PortID: Device: N/A 5Function:2 Description mc_err_msk: 26:26 RW 0x0 25:25 RW 0x0 Memory Controller Error Mask. Note: This bit is only available for Intel Xeon processor E7-2800/4800/8800 v2 product family Product Family processor B0 stepping in Global Corrected Error type (refer to the corresponding status registers GC**ERRST). For A0 and other (Fatal and Non-Fatal) error type, the bit is Reserved.
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Integrated I/O (IIO) Configuration Registers 14.8.38 GSYSST Global System Event Status. This register indicates the error severity signaled by the IIO global error logic. Setting of an individual error status bit indicates that the corresponding error severity has been detected by the IIO. Type: Bus: Offset: CFG 0 0x1cc Bit Attr Default 31:3 RV - PortID: Device: N/A 5Function:2 Description Reserved1: Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x1dc , 0x1e8 Bit Attr Default 31:26 RV - PortID: Device: N/A 5Function:2 Description Reserved1: Reserved log: 25:0 14.8.41 ROS_V 0x0 This field logs the global error status register content when the first fatal error is reported. This has the same format as the global fatal error status register (GFERRST).
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x230, 0x2b0 Attr Default PortID: Device: N/A 5Function:2 Description protocol_rcvd_unexprsp: (D7) 10:10 RW1CS 0x0 9:5 RV - A completion has been received from the Coherent Interface that was unexpected. Reserved2: Reserved csr_acc_32b_unaligned: (C3): 4:4 RW1CS 0x0 CSR access crossing 32-bit boundary. wrcache_uncecc_error: (C2) 3:3 RW1CS 0x0 A double bit ECC error was detected within the Write Cache.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x234, 0x2b4 Attr Default PortID: Device: N/A 5Function:2 Description protocol_rcvd_unexprsp: (D7) 10:10 RWS 0x0 9:5 RV - 0: Disable error status logging for this error 1: Enable Error status logging for this error Reserved2: Reserved csr_acc_32b_unaligned: (C3) 4:4 RWS 0x0 3:3 RWS 0x0 2:2 RWS 0x0 1:1 RWS 0x0 0:0 RV - 0: Disable error status logging for this error 1: Enable Error status logging for this er
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG PortID: 0 Device: IRP0: 0x238, 0x23c IRP1: 0x2b8, 0x2bc Bit Attr Default 12:11 RV - N/A 5Function:2 Description Reserved3: Reserved protocol_rcvd_unexprsp: (D7) 10:10 ROS_V 0x0 9:5 RV - A completion has been received from the Coherent Interface that was unexpected.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Attr Default PortID: N/A Device: 5Function:2 Size: 128 bits Description MsgFields[63:32]: 127:96 ROS_V 0x0 Message-Related Fields. This field is valid for messages only. These bits contain several message related fields as defined in the PCIe* specification. MsgFields[31:0]: 95:64 ROS_V 0x0 Message-Related Fields. This field is valid for messages only.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Attr Default PortID: N/A Device: 5Function:2 Size: 128 bits Description SwRID[6:5]: 27:26 ROS_V 0x0 Switch Routing ID. This field is concatenated with SwRID[4:0] to form SwRID[6:0]. SwRID[6:0] is not part of the PCIe* specification (that is, these bit positions are reserved in the PCIe* spec.).This field facilitates routing of completions through the switch.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Attr Default PortID: N/A Device: 5Function:2 Size: 128 bits Description Fmt[1:0]: 6:5 ROS_V 0x0 Format. This field combined with the Type field specifies the transaction type.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Bit Attr Default 95:66 ROS_V 0x0 PortID: N/A Device: 5Function:2 Size: 128 bits Description Addr[31:2]: 32-bit Address. 65:64 RV - Reserved. Last_DW_BE[3:0]: 63:60 ROS_V 0x0 Last DW Byte Enables. This field is valid for memory, I/O, and configuration requests only. The value in this field is set to all 0’s for I/O and configuration requests.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Attr Default PortID: N/A Device: 5Function:2 Size: 128 bits Description SwRID[6:5]: 27:26 ROS_V 0x0 Switch Routing ID. This field is concatenated with SwRID[4:0] to form SwRID[6:0]. SwRID[6:0] is not part of the PCIe* specification (that is, these bit positions are reserved in the PCIe* spec.).This field facilitates routing of completions through the switch.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Attr Default PortID: N/A Device: 5Function:2 Size: 128 bits Description Fmt[1:0]: 6:5 ROS_V 0x0 Format. This field combined with the Type field specifies the transaction type.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Attr Default PortID: N/A Device: 5Function:2 Size: 128 bits Description Reg[5:0]: 95:90 ROS_V 0x0 89:84 RV - 83:80 ROS_V 0x0 Register Number. This field is valid for configuration requests only. Reserved. ExtReg[3:0]: Extended Register Number. This field is valid for configuration requests only. RouteID[15:0]: 79:64 ROS_V 0x0 ID Routing Fields.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Attr Default PortID: N/A Device: 5Function:2 Size: 128 bits Description Attr[1:0]: 29:28 ROS_V 0x0 Attributes. These provide hints as to how the packet should be handled: Bit 1 set to “1” indicates Relaxed Ordering. Bit 0 set to “1” indicates No Snoop. This field must be set to all 0’s for configuration requests, I/O requests, message requests, and message signaled interrupts.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Attr Default PortID: N/A Device: 5Function:2 Size: 128 bits Description Fmt[1:0]: 6:5 ROS_V 0x0 Format. This field combined with the Type field specifies the transaction type.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Attr Default PortID: N/A Device: 5Function:2 Size: 128 bits Description Lower_Address[6:0]: 94:88 ROS_V 0x0 Lower Address. This field is valid for completions only. For memory read completions, this is the byte address for the first enabled byte of data returned. For all other completions, this field is set to all 0’s. Tag[7:0]: 87:80 ROS_V 0x0 Tag. This field is valid for completions only.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Attr Default PortID: N/A Device: 5Function:2 Size: 128 bits Description TD: 31:31 ROS_V 0x0 TLP Digest. A value of “1” in this field indicates the presence of a single DW TLP digest at the end of the packet for use in ECRC protection as defined by the PCIe* specification.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 IRPP0: 0x240, IRPP1: 0x2c0 Attr Default PortID: N/A Device: 5Function:2 Size: 128 bits Description SwRID[4:0]: 11:7 ROS_V 0x0 Switch Routing ID. This field is concatenated with SwRID[6:5] to form SwRID[6:0]. See description for SwRID[6:5]. Fmt[1:0]: 6:5 ROS_V 0x0 Format. This field combined with the Type field specifies the transaction type.
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Integrated I/O (IIO) Configuration Registers 14.8.46 IRPP[0:1]NFERRST, IRPP[0:1]NNERRST IRP Protocol Non-Fatal FERR and NERR Status. The error status log indicates which error is causing the report of the first non-fatal error event.
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Integrated I/O (IIO) Configuration Registers 14.8.47 IRPP[0:1]NFERRHD[0:3] IRP Protocol Non-Fatal FERR Header Log. Type: Bus: Offset: CFG PortID: N/A 0 Device: 5 Function: 2 IRPP0NFERRHD: 0x258, 0x25c, 0x260, 0x264 IRPP1NFERRHD: 0x2d8, 0x2dc, 0x2e0, 0x2e4 Bit Attr Default 31:0 ROS_V 0x0 Description hdr: Logs the first DWORD of the header on an error condition 14.8.48 IRPP[0:1]ERRCNTSEL IRP Protocol Error Counter Select.
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Integrated I/O (IIO) Configuration Registers 14.8.50 IIOERRST IIO Core Error Status. This register indicates the IIO internal core errors detected by the IIO error logic. An individual error status bit that is set indicates that a particular error occurred; software may clear an error status by writing a 1 to the respective bit. This register is sticky and can only be reset by PWRGOOD. Clearing of the IIO**ERRST is done by clearing the corresponding IIOERRST bits.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x304 Attr PortID: Device: Default N/A 5 Function: 2 Description c4_inbound_ler_disable: 8:8 RWS_L 0x0 Disables logging C4 error due to the PCIe* port being down due to being in LER mode. when set to one. Notes: Locked by RSPLCK c4_outbound_ler_disable: 7:7 RWS_L 0x0 Disables logging C4 error due to the PCIe* being down due to being in LER mode when set to one.
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Integrated I/O (IIO) Configuration Registers 14.8.53 IIOFFERRHD_[0:3] IIO Core Fatal FERR Header. Header log stores the IIO data path header information of the associated IIO core error. The header indicates where the error is originating from and the address of the cycle. The IIO Core Fatal FERR Header totally has 128 bits. Refer to the below table for the mapping between Header and IIOFFERRHD_[0:3] registers.
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Integrated I/O (IIO) Configuration Registers 14.8.55 IIONFERRHD_[0:3] IIO Core Non-Fatal FERR Header. Header log stores the IIO data path header information of the associated IIO core error. The header indicates where the error is originating from and the address of the cycle. The IIO Core Non-Fatal FERR Header totally has 128 bits. Refer to the below table for the mapping between Header and IIONFERRHD_[0:3] registers.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0x33c PortID: Device: Bit Attr Default 3:0 RV - N/A 5 Function: 2 Function: 2 Description Reserved1: Reserved 14.8.57 IIOERRCNT IIO Core Error Counter. Type: Bus: Offset: CFG 0 0x340 PortID: Device: Bit Attr Default 31:8 RV - N/A 5 Description Reserved1: Reserved errovf: 7:7 RW1CS 0x0 0: No overflow occurred 1: Error overflow. The error count may not be valid.
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Integrated I/O (IIO) Configuration Registers 14.8.59 MIERRCTL Miscellaneous Error Control. Type: Bus: Offset: CFG 0 0x384 PortID: Device: Bit Attr Default 31:4 RV - N/A 5 Function: 2 Description Reserved2: Reserved. vpp_err_sts: 3:3 RWS 0x0 VPP Error Status Enable. Reserved1: 2:0 RV Reserved. 14.8.60 MIFFERRST, MIFNERRST Miscellaneous Fatal FERR and NERR Status. Type: Bus: Offset: 14.8.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x38c Attr PortID: Device: Default N/A 5 Function: 2 Size: 128 bits Description vpp_en: 94:87 ROS_V 0x0 When set, the VPP function for the corresponding root port is enabled. Enable Root Port [39] reserved. [38] reserved. [37] reserved. [36] reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x38c Attr PortID: Device: Default N/A 5 Function: 2 Size: 128 bits Description vpp_enaddr: 43:0 14.8.62 ROS_V Assigns the VPP address of the device on the VPP interface and assigns the port address for the ports within the VPP device. There are more address bits then root ports so assignment must be spread across VPP ports.
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Integrated I/O (IIO) Configuration Registers 14.8.64 MIERRCNTSEL Miscellaneous Error Count Select. Type: Bus: Offset: CFG 0 0x3bc PortID: Device: Bit Attr Default 31:4 RV - N/A 5 Function: 2 Description Reserved2: Reserved. vpp_err_sts: 3:3 RW 0x0 VPP Error Status Count Select. Reserved1: 2:0 RV Reserved. 14.8.65 MIERRCNT Miscellaneous Error Count.
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Integrated I/O (IIO) Configuration Registers Register name Offset HDR 0xe 8 0x10 32 SVID 0x2c 16 SID 0x2e 16 CAPPTR 0x34 8 INTLIN 0x3c 8 MBAR 14.9.
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Integrated I/O (IIO) Configuration Registers 14.9.3 PCICMD Type: Bus: Offset: CFG 0 0x4 PortID: Device: Bit Attr Default Description 15:11 RV - Reserved. 10:10 RO 0x0 N/A 5Function:4 intxdisable: N/A for these devices. fb2be: 9:9 RO 0x0 Not applicable to PCI Express and is hardwired to 0. serre: 8:8 RO 0x0 This bit has no impact on error reporting from I/OxAPIC. idsel: 7:7 RO 0x0 Not applicable to internal device. Hardwired to 0.
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Integrated I/O (IIO) Configuration Registers 14.9.4 PCISTS Type: Bus: Offset: Bit CFG 0 0x6 Attr PortID: Device: Default N/A 5Function:4 Description dpe: 15:15 RO_V 0x0 14:14 RO 0x0 This bit is set when the device receives a packet on the primary side with an uncorrectable data error (including a packet with poison bit set) or an uncorrectable address/control parity error. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register.
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Integrated I/O (IIO) Configuration Registers 14.9.5 RID Type: Bus: Offset: Bit CFG 0 0x8 Attr PortID: Device: Default N/A 5Function:4 Description revision_id: 7:0 RO_V 0x0 Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in any Intel Xeon processor E7-2800/4800/8800 v2 product family Product Family function.
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Integrated I/O (IIO) Configuration Registers 14.9.8 HDR Type: Bus: Offset: CFG 0 0xe PortID: Device: Bit Attr Default 7:7 RO 0x1 N/A 5Function:4 Description multi_function_device: This bit defaults to 1b since all these devices are multifunction configuration_layout: 6:0 14.9.9 RO 0x0 This field identifies the format of the configuration header layout. It is Type 0 for all these devices. The default is 00h, indicating a “endpoint device”. MBAR I/OxAPIC Based Address.
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Integrated I/O (IIO) Configuration Registers 14.9.11 SID This value is used to identify a particular subsystem. Type: Bus: Offset: CFG 0 0x2e Bit Attr Default 15:0 RW_O 0x0 PortID: Device: N/A 5Function:4 Description sid_reg: Assigned by the subsystem vendor to uniquely identify the subsytem. 14.9.12 CAPPTR Type: Bus: Offset: CFG 0 0x34 Bit Attr Default 7:0 RO 0x44 PortID: Device: N/A 5Function:4 Description capability_pointer: Points to the first capability structure for the device.
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Integrated I/O (IIO) Configuration Registers 14.9.15 ABAR I/OxAPIC Alternate BAR. Type: Bus: Offset: Bit CFG 0 0x40 Attr Default PortID: Device: N/A 5Function:4 Description abar_enable: 15:15 RW 0x0 14:12 RV - When set, the range FECX_YZ00 to FECX_YZFF is enabled as an alternate access method to the I/OxAPIC registers and these addresses are claimed by the IIO’s internal I/OxAPIC regardless of the setting the MSE bit in the I/OxAPIC config space. Bits “XYZ” are defined below.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit CFG 0 0x44 Attr Default PortID: Device: N/A 5Function:4 Description capability_version: PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec. 19:16 RO 0x1 Note: This capability structure is not compliant with Versions beyond 1.0, since they require additional capability registers to be reserved. The only purpose for this capability structure is to make enhanced configuration space available.
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Integrated I/O (IIO) Configuration Registers 14.9.19 IOAPICTETPC Type: Bus: Offset: CFG 0 0xa0 Bit Attr Default 31:17 RV - PortID: Device: N/A 5Function:4 Description Reserved. cbdma0_inta: 16:16 RW 0x0 0: src/int is connected to IOAPIC table entry 7 1: src/int is connected to IOAPIC table entry 23 Notes: This bit should never be set due to a sighting. 15:13 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers 14.9.20 PMCAP Power Management Capabilities. Type: Bus: Offset: CFG 0 0xe0 PortID: Device: Bit Attr Default 31:27 RO 0x0 N/A 5Function:4 Description pme_support: Bits 31, 30 and 27 must be ‘0’. PME is not supported in this device/function.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: CFG 0 0xe4 PortID: Device: Bit Attr Default 15:15 RO 0x0 N/A 5Function:4 Description pmests: Not relevant for I/OxAPIC dscl: 14:13 RO 0x0 Not relevant for I/OxAPIC dsel: 12:9 RO 0x0 Not relevant for I/OxAPIC pmeen: 8:8 RO 0x0 7:4 RV - 3:3 RO 0x1 2:2 RV - Not relevant for I/OxAPIC Reserved. rstd3hotd0: Indicates I/OxAPIC does not reset its registers when transitioning from D3hot to D0. Reserved.
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Integrated I/O (IIO) Configuration Registers 14.9.23 IOADSELS1 I/OxAPIC DSELS Register 1. Type: Bus: Offset: CFG 0 0x28c PortID: Device: Bit Attr Default Description 31:18 RV - Reserved. 17:0 RWS 0x0 N/A 5Function:4 gttcfg2SIpcIOADels1: gttcfg2SIpcIOADels1[17:0] 14.9.24 IOINTSRC0 I/O Interrupt Source Register 0.
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Integrated I/O (IIO) Configuration Registers 14.9.25 IOINTSRC1 I/O Interrupt Source Register 1. Type: Bus: Offset: CFG 0 0x2a4 PortID: Device: Bit Attr Default Description 31:21 RV - Reserved. N/A 5Function:4 int_src1: 20:0 14.9.
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Integrated I/O (IIO) Configuration Registers 14.9.27 IOREMGPECNT Remote I/O GPE Count. Type: Bus: Offset: CFG 0 0x2ac PortID: Device: Bit Attr Default Description 31:24 RV - Reserved. 23:16 RW_V 0x0 N/A 5Function:4 hpgpe_cnt: Number of remote HPGPEs received. pmgpe_cnt: 15:8 RW_V 0x0 Number of remote PMGPEs received. gpe_cnt: 7:0 RW_V 0x0 Number of remote GPEs received. 14.9.
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Integrated I/O (IIO) Configuration Registers 14.10.1 INDEX The Index Register will select which indirect register appears in the window register to be manipulated by software. Software will program this register to select the desired APIC internal register. Type: Bus: Offset: MEM 0 0x0 PortID: Device: Bit Attr Default 7:0 RW_L 0x0 8’h7e 5Function:4 Description idx: Indirect register to access. 14.10.
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Integrated I/O (IIO) Configuration Registers Register name Offset Size BCFG__WINDOW 0x3 32 RTL0__WINDOW 0x10 32 RTH0__WINDOW 0x11 32 RTL1__WINDOW 0x12 32 RTH1__WINDOW 0x13 32 RTL2__WINDOW 0x14 32 RTH2__WINDOW 0x15 32 RTL3__WINDOW 0x16 32 RTH3__WINDOW 0x17 32 RTL4__WINDOW 0x18 32 RTH4__WINDOW 0x19 32 RTL5__WINDOW 0x1a 32 RTH5__WINDOW 0x1b 32 RTL6__WINDOW 0x1c 32 RTH6__WINDOW 0x1d 32 RTL7__WINDOW 0x1e 32 RTH7__WINDOW 0x1f 32 RTL8__WINDOW 0x20 32 RTH8__
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Integrated I/O (IIO) Configuration Registers Register name 14.10.4.1 Offset Size RTL21__WINDOW 0x3a 32 RTH21__WINDOW 0x3b 32 RTL22__WINDOW 0x3c 32 RTH22__WINDOW 0x3d 32 RTL23__WINDOW 0x3e 32 RTH23__WINDOW 0x3f 32 APICID__WINDOW This register uniquely identifies an APIC in the system. This register is not used by OS’es anymore and is still implemented in hardware because of FUD. Type: Bus: Offset: MEM 0 0x0 PortID: Device: Bit Attr Default Description 31:28 RV - Reserved.
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Integrated I/O (IIO) Configuration Registers 14.10.4.3 ARBID__WINDOW This is a legacy register carried over from days of serial bus interrupt delivery. This register has no meaning in IIO. It just tracks the APICID register for compatibility reasons. Type: Bus: Offset: MEM 0 0x2 PortID: Device: Bit Attr Default Description 31:28 RV - Reserved. 27:24 RO 0x0 23:0 RV - N/A 5Function:4 arbitration_id: Just tracks the APICID register. 14.10.4.4 Reserved.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM PortID: N/A 0 Device: 5Function:4 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e Attr Default Description msk: 16:16 RW 0x1 When cleared, an edge assertion or level (depending on bit 15 in this register) on the corresponding interrupt input results in delivery of an MSI interrupt using the contents of the corresponding redirection ta
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Integrated I/O (IIO) Configuration Registers Type: Bus: Offset: Bit MEM PortID: N/A 0 Device: 5Function:4 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e Attr Default Description delm: 10:8 RW 0x0 7:0 RW 0x0 This field specifies how the APICs listed in the destination field should act upon reception of the interrupt.
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Integrated I/O (IIO) Configuration Registers 14.
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Integrated I/O (IIO) Configuration Registers 14.11.2 DID Type: Bus: Bus: Offset: Bit 15:0 CFG 0 0 0x2 Attr RO PortID: Device: Device: Default Description Device 6: 0xe10 (Function 0) 0xe13 (Function 3) device_identification_number: Device 7: 0xe18 (Function 0) 14.11.3 N/A 6Function:0,3 7Function:0 Device ID values vary from function to function. Bits 15:8 are equal to 0x0E.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Offset: CFG 0 0 0x4 PortID: Device: Device: Bit Attr Default 0:0 RO 0x0 N/A 6Function:0,3 7Function:0 Description iose: Not applicable to DFx and is hardwired to 0 14.11.
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Integrated I/O (IIO) Configuration Registers 14.11.5 RID Type: Bus: Bus: Offset: Bit CFG 0 0 0x8 Attr PortID: Device: Device: Default N/A 6Function:0,3 7Function:0 Description revision_id: 7:0 RO_V 0x0 Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in any Intel Xeon processor E7-2800/4800/8800 v2 product family Product Family function.
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Integrated I/O (IIO) Configuration Registers 14.11.8 PLAT Type: Bus: Bus: Offset: CFG 0 0 0xd PortID: Device: Device: Bit Attr Default 7:0 RO 0x0 N/A 6Function:0,3 7Function:0 Description primary_latency_timer: Not applicable to PCI Express*. Hardwired to 00h. 14.11.
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Integrated I/O (IIO) Configuration Registers 14.11.12 SDID Type: Bus: Bus: Offset: CFG 0 0 0x2e Bit Attr Default 15:0 RW_O 0x0 PortID: Device: Device: N/A 6Function:0,3 7Function:0 Description subsystem_device_identification_number: Assigned by the subsystem vendor to uniquely identify the subsystem 14.11.
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Integrated I/O (IIO) Configuration Registers 14.11.16 MINGNT Type: Bus: Bus: Offset: CFG 0 0 0x3e Bit Attr Default 7:0 RO 0x0 PortID: Device: Device: N/A 6Function:0,3 7Function:0 Description mgv: Not applicable and hardwired to 0. 14.11.17 MAXLAT Type: Bus: Bus: Offset: CFG 0 0 0x3f PortID: Device: Device: Bit Attr Default 7:0 RO 0x0 N/A 6Function:0,3 7Function:0 Description mlv: Not applicable and hardwired to 0. 14.11.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: Offset: Bit CFG 0 0 0x40 Attr PortID: Device: Device: Default N/A 6Function:0,3 7Function:0 Description next_ptr: 15:8 RO 0x80 7:0 RO 0x10 Pointer to the next capability. If set to 0 to indicate there are no more capability structures. capability_id: Provides the PCI Express capability ID assigned by PCI-SIG. 14.11.
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Integrated I/O (IIO) Configuration Registers Type: Bus: Bus: CFG 0 0 PortID: Device: Device: Offset: 0x698 Bit Attr Default Description 31:28 RWS_L 0xd bndl7: 27:24 RWS_L 0xd bndl6: 23:20 RWS_L 0xd bndl5: 19:16 RWS_L 0xd bndl4: 15:12 RWS_L 0xd bndl3: 11:8 RWS_L 0xd bndl2: 7:4 RWS_L 0xd bndl1: 3:0 RWS_L 0xd bndl0: N/A 6Function:3 7Function:0 § 504 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet Volume Two: Functional Description, February 2014