Datasheet

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Document Number: 318463-001

Intel

3200 and 3210 Chipset

Datasheet

— For the Intel

3200 and 3210 Chipset Memory Controller Hub (MCH)

November 2007

Summary of content (326 pages)

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Intel® 3200 and 3210 Chipset Datasheet — For the Intel® 3200 and 3210 Chipset Memory Controller Hub (MCH) November 2007 Document Number: 318463-001
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents 1 Introduction ............................................................................................................ 15 1.1 Terminology ..................................................................................................... 17 1.2 MCH Overview .................................................................................................. 20 1.2.1 Host Interface........................................................................................ 20 1.2.
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3.8 3.9 3.7.7 SMM Access Through TLB.........................................................................51 Memory Shadowing............................................................................................52 I/O Address Space .............................................................................................52 3.9.1 PCI Express* I/O Address Mapping............................................................53 4 MCH Register Description.............................................
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.2 Datasheet 5.1.34 ERRSTS—Error Status ............................................................................. 91 5.1.35 ERRCMD—Error Command....................................................................... 93 5.1.36 SMICMD—SMI Command......................................................................... 94 5.1.37 SKPD—Scratchpad Data .......................................................................... 94 5.1.38 CAPID0—Capability Identifier ..........................................
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5.3 5.2.50 TIS—Thermal Interrupt Status................................................................ 137 5.2.51 TSMICMD—Thermal SMI Command ......................................................... 139 5.2.52 PMSTS—Power Management Status......................................................... 140 EPBAR............................................................................................................ 141 5.3.1 EPESD—EP Element Self Description...................................................
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6.43 6.44 6.45 6.46 6.47 6.48 6.49 6.50 6.51 6.52 6.53 6.54 6.55 6.56 6.57 6.58 7 SLOTSTS—Slot Status...................................................................................... 182 RCTL—Root Control ......................................................................................... 183 RSTS—Root Status .......................................................................................... 184 PELC—PCI Express Legacy Control................................................................
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7.2.12 KTSCR—KT Scratch .............................................................................. 212 8 Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) ......................................................................................... 213 8.1 VID1—Vendor Identification .............................................................................. 215 8.2 DID1—Device Identification............................................................................... 216 8.
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8.52 8.53 8.54 8.55 8.56 8.57 VC0RCTL—VC0 Resource Control ....................................................................... 254 VC0RSTS—VC0 Resource Status........................................................................ 255 RCLDECH—Root Complex Link Declaration Enhanced............................................ 255 ESD—Element Self Description .......................................................................... 256 LE1D—Link Entry 1 Description .......................................
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13 10 Testability.............................................................................................................. 315 13.1 XOR Test Mode Initialization.............................................................................. 315 13.2 XOR Chain Definition ........................................................................................ 316 13.3 XOR Chains..................................................................................................... 317 13.4 XOR Chains.......
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Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Intel® 3210 Chipset System Diagram Example............................................................. 16 Intel® 3200 Chipset System Diagram Example............................................................. 17 System Address Ranges............................................................................................ 37 DOS Legacy Address Range.......................................................................................
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34 35 36 37 38 39 40 41 42 43 44 45 46 12 XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR Chain Chain Chain Chain Chain Chain Chain Chain Chain Chain Chain Chain Chain 2 .......................................................................................................... 319 3 .......................................................................................................... 319 4 ..........................................................................................................
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Revision History Revision Number -001 Datasheet Description • Initial release Revision Date November 2007 13
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Intel® 3200 and 3210 Chipset MCH Features • • • Processor/Host Interface (FSB) — Dual-Core Intel® Xeon® Processor 3000 Series — Quad-Core Intel® Xeon® Processor 3200 Series — 800/1067/1333 MT/s (200/266/333 MHz) FSB — Hyper-Threading Technology (HT Technology) — FSB Dynamic Bus Inversion (DBI) — 36-bit host bus addressing — 12-deep In-Order Queue — 1-deep Defer Queue — GTL+ bus driver with integrated GTL termination resistors — Supports cache Line Size of 64 bytes System Memory Interface — One or two cha
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Introduction 1 Introduction The Intel® 3200 and 3210 Chipsets are designed for use with the Dual-Core Intel® Xeon® Processor 3000 Series and Quad-Core Intel® Xeon® Processor 3200 Series in server platforms. The chipset contains two components: 3210/3100 MCH for the host bridge and I/O Controller Hub 9 (ICH9) for the I/O subsystem. The ICH9 is the ninth generation I/O Controller Hub and provides a multitude of I/O related functions.
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Introduction Figure 1. Intel® 3210 Chipset System Diagram Example Processor System Memory Intel® 3210 supports two PCI Express x8 (as shown) or one PCI Express x16 PCI Express PCI Express x8 CH A DDR2/3 DDR2 CH B DDR2/3 DDR2 Intel® 3210 MCH PCI Express PCI Express x8 DMI C Link – Still connect on nonAMT system Power Management USB2. 0 12 Ports Clock Generation GPIO SATA 6 Ports SMBus2.
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Introduction Figure 2. Intel® 3200 Chipset System Diagram Example Processor System Memory CH A DDR2/3 DDR2 CH B DDR2/3 DDR2 Intel® 3200 MCH PCI Express PCI Express x8 DMI C Link – Still connect on nonAMT system Power Management USB2. 0 12 Ports Clock Generation GPIO SATA 6 Ports SMBus2.0 / I2 C Intel® ICH 9 SST/PECI (Fan Speed Control) SPI Flash Firmware SPI Gb LAN WLAN 6 PCIe x1 Slots LPC PCIe Bus 4 PCI Masters PCI Bus SIO 1.
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Introduction Term 18 Description DMI Direct Media Interface is a proprietary chip-to-chip connection between the MCH and ICH. This interface is based on the standard PCI Express* specification. Domain A collection of physical, logical or virtual resources that are allocated to work together. Domain is used as a generic term for virtual machines, partitions, etc. EP PCI Express Egress Port FSB Front Side Bus.
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Introduction Table 1. Intel Specification Document Name Datasheet Location Intel® 3200 and 3210 Chipset Specification Update http://www.intel.com/design/ chipsets/specupdt/318464.htm Intel® 3200 and 3210 Chipset Thermal and Mechanical Design Guide http://www.intel.com/design/ chipsets/designex/318465.htm Dual-Core Intel® Xeon Processor 3000 series Thermal and Mechanical Design Guidelines http://www.intel.com/design/ intarch/designgd/314917.
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Introduction 1.2 MCH Overview The role of a MCH in a system is to manage the flow of information between its four interfaces: the processor interface, the system memory interface, the PCI Express interface, and the I/O Controller through DMI interface. This includes arbitrating between the four interfaces when each initiates transactions. It supports one or two channels of DDR2 SDRAM. It also supports the PCI Express based external device attach.
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Introduction • Supports maximum memory bandwidth of 6.4 GB/s in single-channel mode or 12.8 GB/s in dual-channel mode assuming DDR2 800 MHz. • Supports 512-Mb and 1-Gb DDR2 DRAM technologies for x8 and x16 devices. • Using 512 Mb device technologies, the smallest memory capacity possible is 256 MB, assuming Single Channel Mode with a single x16 single sided un-buffered non-ECC DIMM memory configuration.
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Introduction 1.2.4 PCI Express* Interface The 3210 MCH supports either two PCI Express* 8-lane (x8) ports or one PCI Express 16-lane (x16) port. Figure 1 shows two PCI Express 8-lane (x8) ports (support of one PCI Express 16-lane (x16) port is not shown in figure). The 3200 MCH supports one 8lane (x8) PCI Express port (see Figure 2). The 3200/3210 MCHs do not support PCI Express graphics. The PCI Express ports are intended for external device attach.
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Introduction 1.2.5 MCH Clocking • Differential host clock of 200/266/333 MHz. Supports FSB transfer rates of 800/1066/1333 MT/s. • Differential memory clocks of 333/400/533 MHz. Supports memory transfer rates of DDR2-667 and DDR2-800. • The PCI Express* PLL of 100 MHz Serial Reference Clock generates the PCI Express core clock of 250 MHz. • All of the above clocks are capable of tolerating Spread Spectrum clocking. • Host, memory, and PCI Express PLLs are disabled until PWROK is asserted. 1.2.
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Introduction 24 Datasheet
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Signal Description 2 Signal Description This chapter provides a detailed description of MCH signals. The signals are arranged in functional groups according to their associated interface. The following notations are used to describe the signal type. Signal Type Datasheet Description PCI Express* PCI Express interface signals. These signals are compatible with PCI Express 1.1 Signaling Environment AC Specifications and are AC coupled. The buffers are not 3.3 V tolerant.
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Signal Description 2.1 Host Interface Signals Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination voltage of the Host Bus (VTT).
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Signal Description Signal Name FSB_AB_[35:3] FSB_ADSTBB_[1:0] FSB_DB_[63:0] Type I/O GTL+ 2x I/O GTL+ 2x I/O GTL+ 4x Description Host Address Bus: FSB_AB_[35:3] connect to the processor address bus. During processor cycles, the FSB_AB_[35:3] are inputs. The MCH drives FSB_AB_[35:3] during snoop cycles on behalf of DMI and PCI Express initiators. FSB_AB_[35:3] are transferred at 2x rate. Note that the address is inverted on the processor bus.
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Signal Description Signal Name FSB_TRDYB Type Description O Host Target Ready: Indicates that the target of the processor transaction is able to enter the data transfer phase.
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Signal Description 2.2 System Memory (DDR2) Interface Signals 2.2.1 System Memory Channel A Interface Signals Signal Name DDR_A_CK DDR_A_CKB DDR_A_CSB_[3:0] DDR_A_CKE_[3:0] DDR_A_ODT_[3:0] DDR_A_MA_[14:0] DDR_A_BS_[2:0] DDR_A_RASB DDR_A_CASB DDR_A_WEB DDR_A_DQ_[63:0] DDR_A_CB_[7:0] DDR_A_DM_[7:0] DDR_A_DQS_[8:0] DDR_A_DQSB_[8:0] Datasheet Type O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 I/O SSTL-1.8 I/O SSTL-1.8 O SSTL-1.
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Signal Description 2.2.2 System Memory Channel B Interface Signals Signal Name DDR_B_CK DDR_B_CKB DDR_B_CSB_[3:0] DDR_B_CKE_[3:0] DDR_B_ODT_[3:0] DDR_B_MA_[14:0] DDR_B_BS_[2:0] DDR_B_RASB DDR_B_CASB DDR_B_WEB DDR_B_DQ_[63:0] DDR_B_CB_[7:0] DDR_B_DM_[7:0] DDR_B_DQS_[8:0] DDR_B_DQSB_[8:0] 30 Type O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 O SSTL-1.8 I/O SSTL-1.8 I/O SSTL-1.8 O SSTL-1.8 I/O SSTL-1.8 I/O SSTL-1.
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Signal Description 2.2.3 System Memory Miscellaneous Signals Signal Name Type I/O DDR_RCOMPXPD A I/O DDR_RCOMPXPU A I/O DDR_RCOMPYPD A I/O DDR_RCOMPYPU A I DDR_VREF A I DDR_RCOMPVOH A I DDR_RCOMPVOL 2.
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Signal Description Signal Name EXP_COMPI 2.4 Description I Primary PCI Express Input Current Compensation A EXP2_COMPO I Secondary PCI Express Output Current Compensation (3210 MCH only) A This signal is a No Connect for the 3200 MCH. EXP2_COMPI I Secondary PCI Express Input Current Compensation (3210 MCH only) A This signal is a No Connect for the 3200 MCH. Controller Link Interface Signals Signal Name CL_DATA CL_CLK CL_VREF CL_RST# 2.
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Signal Description Signal Name CL_PWROK EXP_SLR Type Description CL Power OK: When asserted, CL_PWROK is an indication to the MCH that core power (VCC_CL) has been stable for at least 10 us. I/O SSTL I CMOS PCI Express* Static Lane Reversal/Form Factor Selection: MCH’s PCI Express lane numbers are reversed to differentiate BTX and ATX form factors 0 = MCH PCI Express lane numbers are reversed (BTX) 1 = Normal operation (ATX) BSEL[2:0] PWROK ICH_SYNCB ALLZTEST XORTEST TEST[3:0] 2.
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Signal Description 2.7 Power and Grounds Name Voltage VCC 1.25 V VTT Description Core Power 1.1 V/1.2 V Processor System Bus Power VCC_EXP 1.25 V PCI Express* and DMI Power VCC_DDR 1.8 V DDR2 System Memory Power VCC_CKDDR 1.8V DDR2 System Clock Memory Power 3.3 V 3.3 V CMOS Power VCC3_3 VCCAPLL_EXP 1.25 V Primary PCI Express PLL Analog Power VCCAPLL_EXP2 1.25 V Secondary PCI Express PLL Analog Power VCCA_hplL 1.25 V Host PLL Analog Power VCCA_mpl 1.
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System Address Map 3 System Address Map The MCH supports 64 GB (36 bit) of host address space and 64 KB+3 of addressable I/O space. There is a programmable memory address space under the 1 MB region which is divided into regions which can be individually controlled with programmable attributes such as Disable, Read/Write, Write Only, or Read Only. Attribute programming is described in the Register Description section.
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System Address Map • Device 3 — ME Control • Device 6, Function 0 (Intel 3210 MCH only) — MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window. — PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window. — PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access window — IOBASE1/IOLIMIT1 – PCI Express port I/O access window. The rules for the above programmable ranges are: 1. ALL of these ranges MUST be unique and NON-OVERLAPPING.
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Datasheet MCHBAR (GFXVTBAR, DMIVC1BAR, VTMEBAR, VTDPVC0BAR) Device6 Bars (MBASE1/ MLIMIT1, PMBASE1/ PMLIMIT1) Device1 Bars (MBASE1/ MLIMIT1, PMBASE1/ PMLIMIT1) Independently Programmable Non-Overlapping Windows Device3 (EPHECIBAR, EPHECI2BAR , EPKTBAR) Device0 (Stolen Memory) Device0 Bars (PXPEPBAR, MCHBAR, PCIEXBAR, DMIBAR) 0 1MB 64MB aligned TOLUD BASE 64MB aligned RECLAIM BASE 64MB aligned TOUUD BASE RECLAIM LIMIT= RECLAIM BASE+ x Device1 Bars (PMUBASE1/ PMULIMIT1) Legacy Address Range Ma
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System Address Map 3.1 Legacy Address Range This area is divided into the following address regions: • 0 - 640 KB – DOS Area • 640 - 768 KB – Legacy Video Buffer Area • 768 - 896 KB in 16 KB sections (total of 8 sections) – Expansion Area • 896 -960 KB in 16 KB sections (total of 4 sections) – Extended System BIOS Area • 960 KB - 1 MB Memory – System BIOS Area Figure 4.
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System Address Map 3.1.2 Expansion Area (C_0000h-D_FFFFh) This 128 KB ISA Expansion region (000C_0000h – 000D_FFFFh) is divided into eight 16 KB segments. Each segment can be assigned one of four Read/Write states: readonly, write-only, read/write, or disabled. Typically, these blocks are mapped through MCH and are subtractive decoded to ISA space. Memory that is disabled is not remapped. Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM. Table 2.
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System Address Map 3.1.4 System BIOS Area (F_0000h–F_FFFFh) This area is a single 64 KB segment (000F_0000h – 000F_FFFFh). This segment can be assigned read and write attributes. It is by default (after reset) Read/Write disabled and cycles are forwarded to DMI Interface. By manipulating the Read/Write attributes, the MCH can “shadow” BIOS into the main DRAM. When disabled, this segment is not remapped. Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM. Table 4.
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System Address Map Figure 5. Main Memory Address Range 8 GB Main Memory . . . . . FFFF_FFFFh 4 GB FLASH APIC LT PCI Memory Range TSEG (1MB/2MB/8MB, optional) Main Memory 0100_0000h ISA Hole (optional) 00F0_0000h Main Memory 0010_0000h DOS Compatibility Memory 0h 3.2.1 ISA Hole (15 MB –16 MB) A hole can be created at 15 MB–16 MB as controlled by the fixed hole enable in Device 0 space. Accesses within this hole are forwarded to the DMI Interface.
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System Address Map 3.2.2 TSEG TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below stolen memory, which is at the top of Low Usable physical memory (TOLUD). SMM-mode processor accesses to enabled TSEG access the physical DRAM at the same address. Non-processor originated accesses are not allowed to SMM space. PCI Express, and DMI originated cycles to enabled SMM space are handled as invalid cycle type with reads and writes to location 0 and byte enables turned off for writes.
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System Address Map 3.3 PCI Memory Address Range (TOLUD – 4 GB) This address range, from the top of low usable DRAM (TOLUD) to 4 GB is normally mapped to the DMI Interface.
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System Address Map Figure 7.
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System Address Map 3.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in the ICH portion of the chipset. The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be populated in the system. Since it is difficult to relocate an interrupt controller using plug-and-play software, fixed address decode regions have been allocated for them.
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System Address Map 3.4 Main Memory Address Space (4 GB to TOUUD) The MCH supports 36 bit addressing. The maximum main memory size supported is 8 GB total DRAM memory. A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger. As a result, TOM, and TOUUD registers and RECLAIMBASE/RECLAIMLIMIT registers become relevant. The new reclaim configuration registers exist to reclaim lost main memory space. The greater than 32 bit reclaim handling will be handled similar to other MCHs.
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System Address Map 3.4.1 Memory Re-claim Background The following are examples of Memory Mapped IO devices are typically located below 4 GB: • High BIOS • HSEG • TSEG • XAPIC • Local APIC • FSB Interrupts • Mbase/Mlimit • Memory Mapped IO space that supports only 32 B addressing The MCH provides the capability to re-claim the physical memory overlapped by the Memory Mapped I/O logical address space.
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System Address Map 3.6 PCI Express* Address Space The MCH can be programmed to direct memory accesses to the PCI Express interface when addresses are within either of two ranges specified via registers in MCH’s Device 1 configuration space. • The first range is controlled via the Memory Base Register (MBASE) and Memory Limit Register (MLIMIT) registers. • The second range is controlled via the Pre-fetchable Memory Base (PMBASE) and Pre-fetchable Memory Limit (PMLIMIT) registers.
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System Address Map 3.7 System Management Mode (SMM) System Management Mode uses main memory for System Management RAM (SMM RAM). The MCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment (TSEG). System Management RAM space provides a memory area that is available for the SMI handlers and code and data storage. This memory resource is normally hidden from the system OS so that the processor has immediate access to this memory space upon entry to SMM.
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System Address Map 3.7.2 SMM Space Restrictions If any of the following conditions are violated, the results of SMM accesses are unpredictable and may cause the system to hang: 1. The Compatible SMM space must not be set-up as cacheable. 2. High or TSEG SMM transaction address space must not overlap address space assigned to system DRAM, or to any “PCI” devices (including DMI Interface and PCI-Express). This is a BIOS responsibility. 3. Both D_OPEN and D_CLOSE must not be set to 1 at the same time. 4.
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System Address Map 3.7.4 SMM Control Combinations The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows software to write to the SMM ranges without being in SMM mode. BIOS software can use this bit to initialize SMM code at powerup. The D_LCK bit limits the SMM range access to only SMM mode accesses. The D_CLS bit causes SMM (both CSEG and TSEG) data accesses to be forwarded to the DMI Interface or PCI Express.
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System Address Map PCI Express and DMI Interface read accesses to the GMADR range are not supported therefore will have no address translation concerns. PCI Express and DMI Interface reads to GMADR will be remapped to address 000C_0000h. The read will complete with UR (unsupported request) completion status. Fetches are always decoded (at fetch time) to ensure not in SMM (actually, anything above base of TSEG or 640 K–1 M).
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System Address Map 3.9.1 PCI Express* I/O Address Mapping The MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express bus interface when processor initiated I/O cycle addresses are within the PCI Express I/ O address range. This range is controlled via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in MCH Device 1 configuration space. Address decoding for this range is based on the following concept.
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System Address Map 54 Datasheet
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MCH Register Description 4 MCH Register Description The MCH contains two sets of software accessible registers, accessed via the Host processor I/O address space: Control registers and internal configuration registers. • Control registers are I/O mapped into the processor I/O space, which control access to PCI and PCI Express configuration space (see Chapter 6).
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MCH Register Description 4.1 Register Terminology The following table shows the register-related terminology that is used. Item RO Read Only bit(s). Writes to these bits have no effect. RO/S Read Only / Sticky. Writes to these bits have no effect. These are status bits only. Bits are not returned to their default values by “warm” reset, but will be reset with a cold/ complete reset (for PCI Express related bits, a cold reset is “Power Good Reset” as defined in the PCI Express specification).
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MCH Register Description 4.2 Configuration Process and Registers 4.2.1 Platform Configuration Structure The DMI physically connects the MCH and the Intel ICH9; thus, from a configuration standpoint, the DMI is logically PCI bus 0. As a result, all devices internal to the MCH and the ICH appear to be on PCI bus 0. Note: The ICH9 internal LAN controller does not appear on bus 0 – it appears on the external PCI bus and this number is configurable.
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MCH Register Description The MCH contains four PCI devices within a single physical component. The configuration registers for the four devices are mapped as devices residing on PCI bus 0. • Device 0: Host Bridge/DRAM Controller. Logically this appears as a PCI device residing on PCI bus 0. Device 0 contains the standard PCI header registers, PCI Express base address register, DRAM control (including thermal/throttling control), and configuration for the DMI and other MCH specific registers.
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MCH Register Description The MCH is responsible for translating and routing the processor’s I/O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration registers, DMI or PCI Express. 4.3.2 PCI Express Enhanced Configuration Mechanism PCI Express extends the configuration space to 4096 bytes per device/function as compared to 256 bytes allowed by PCI Specification Revision 2.3. PCI Express configuration space is divided into a PCI 2.
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MCH Register Description Figure 9.
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MCH Register Description Figure 10.
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MCH Register Description 4.4.
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MCH Register Description Subordinate Bus Number registers of its PCI-to-PCI bridges to determine if the configuration access is meant for Primary PCI, or some other downstream PCI bus or PCI Express link. Configuration accesses that are forwarded to the ICH9, but remain unclaimed by any device or bridge will result in a master abort. 4.
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MCH Register Description Bit 15:11 Access & Default Description Device Number: This field selects one agent on the PCI bus selected by the Bus Number. When the Bus Number field is “00” the MCH decodes the Device Number field. The MCH is always Device Number 0 for the Host bridge entity, Device Number 1 for the Host-PCI Express entity. Therefore, when the Bus Number =0 and the Device Number equals 0, 1, or 2 the internal MCH devices are selected.
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DRAM Controller Registers (D0:F0) 5 DRAM Controller Registers (D0:F0) The DRAM Controller registers are in Device 0 (D0), Function 0 (F0). Warning: Address locations that are not listed are considered Intel Reserved registers locations. Reads to Reserved registers may return non-zero values. Writes to reserved locations may cause system failures. All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in this component are simply not included in this document.
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DRAM Controller Registers (D0:F0) Table 8.
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DRAM Controller Registers (D0:F0) 5.1 Configuration Register Details 5.1.1 VID—Vendor Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 0–1h 8086h RO 16 bits This register combined with the Device Identification register uniquely identifies any PCI device. Bit Access Default Value 15:0 RO 8086h 5.1.2 Description Vendor Identification Number (VID): PCI standard identification for Intel.
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DRAM Controller Registers (D0:F0) 5.1.3 PCICMD—PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 4–5h 0006h RO, RW 16 bits Since MCH Device 0 does not physically reside on PCI_A many of the bits are not implemented. Bit Access Default Value 15:9 RO 00h Description Reserved SERR Enable (SERRE): This bit is a global enable bit for Device 0 (and Device 6 for the 3210 MCH) SERR messaging. The MCH does not have an SERR signal.
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DRAM Controller Registers (D0:F0) 5.1.4 PCISTS—PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 6–7h 0090h RO, RWC 16 bits This status register reports the occurrence of error events on Device 0's PCI interface. Since the MCH Device 0 does not physically reside on PCI_A many of the bits are not implemented. Bit Access Default Value 15 RWC 0b Detected Parity Error (DPE): This bit is set when this Device receives a Poisoned TLP.
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DRAM Controller Registers (D0:F0) 5.1.5 RID—Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 8h See table below RO 8 bits This register contains the revision number of the MCH Device 0. These bits are read only and writes to this register have no effect. Bit 7:0 5.1.6 Access Default Value RO See description Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the MCH Device 0.
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DRAM Controller Registers (D0:F0) 5.1.8 HDR—Header Type B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI Eh 00h RO 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit Access Default Value 7:0 RO 00h 5.1.9 Description PCI Header (HDR): This field always returns 0 to indicate that the MCH is a single function device with standard header layout. Reads and writes to this location have no effect.
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DRAM Controller Registers (D0:F0) 5.1.11 CAPPTR—Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 34h E0h RO 8 bits The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Bit Access Default Value Description 7:0 RO E0h Capabilities Pointer (CAPPTR): Pointer to the offset of the first capability ID register block.
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DRAM Controller Registers (D0:F0) 5.1.13 MCHBAR—MCH Memory Mapped Register Range Base B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 48–4Fh 0000000000000000h RO, RW/L 64 bits This is the base address for the MCH Memory Mapped Configuration space. There is no physical memory within this 16KB window that can be addressed. The 16 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space.
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DRAM Controller Registers (D0:F0) 5.1.14 DEVEN—Device Enable B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 54–57h 000023DBh RO, RW/L 32 bits Allows for enabling/disabling of PCI devices and functions that are within the MCH. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register. All the bits in this register are Intel TXT Lockable.
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DRAM Controller Registers (D0:F0) Bit Access Default Value 5:2 RO 0s Description Reserved PCI Express Port (D1EN): 1 RW/L 1b 0 = Bus 0, Device 1, Function 0 is disabled and hidden. Bus 0, Device 1, Function 0 is enabled and visible. 0 5.1.15 RO 1b Host Bridge (D0EN): Bus 0, Device 0, Function 0 may not be disabled and is therefore hardwired to 1.
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DRAM Controller Registers (D0:F0) Bit Access Default Value 63:36 RO 0000000h Description Reserved PCI Express Base Address (PCIEXBAR): This field corresponds to bits [35:28] of the base address for PCI Express enhanced configuration space. BIOS will program this register resulting in a base address for a contiguous memory address space; size is defined by bits [2:1] of this register.
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DRAM Controller Registers (D0:F0) 5.1.16 DMIBAR—Root Complex Register Range Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 68–6Fh 0000000000000000h RO, RW/L 64 bits This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the MCH. There is no physical memory within this 4 KB window that can be addressed.
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DRAM Controller Registers (D0:F0) 5.1.17 PAM0—Programmable Attribute Map 0 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 90h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS area from 0F0000h–0FFFFFh. The MCH allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers are used to support these features.
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DRAM Controller Registers (D0:F0) 5.1.18 PAM1—Programmable Attribute Map 1 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 91h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0C0000h – 0C7FFFh. Bit Access Default Value 7:6 RO 00b Description Reserved 0C4000h–0C7FFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0C4000h to 0C7FFFh.
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DRAM Controller Registers (D0:F0) 5.1.19 PAM2—Programmable Attribute Map 2 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 92h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0C8000h– 0CFFFFh. Bit Access Default Value 7:6 RO 00b Description Reserved 0CC000h–0CFFFFh Attribute (HIENABLE): 00 = DRAM Disabled: Accesses are directed to DMI. 5:4 RW/L 00b 01 = Read Only: All reads are serviced by DRAM.
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DRAM Controller Registers (D0:F0) 5.1.20 PAM3—Programmable Attribute Map 3 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 93h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h – 0D7FFFh. Bit Access Default Value 7:6 RO 00b Description Reserved 0D4000h–0D7FFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0D4000h to 0D7FFFh.
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DRAM Controller Registers (D0:F0) 5.1.21 PAM4—Programmable Attribute Map 4 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 94h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h – 0DFFFFh. Bit Access Default Value 7:6 RO 00b Description Reserved 0DC000h–0DFFFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0DC000h to 0DFFFFh.
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DRAM Controller Registers (D0:F0) 5.1.22 PAM5—Programmable Attribute Map 5 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 95h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h – 0E7FFFh. Bit Access Default Value 7:6 RO 00b Description Reserved 0E4000h–0E7FFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0E4000 to 0E7FFF.
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DRAM Controller Registers (D0:F0) 5.1.23 PAM6—Programmable Attribute Map 6 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 96h 00h RO, RW/L 8 bits This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h–0EFFFFh. Bit Access Default Value 7:6 RO 00b Description Reserved 0EC000h–0EFFFFh Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.
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DRAM Controller Registers (D0:F0) 5.1.25 REMAPBASE—Remap Base Address Register B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 15:10 RO 000000b 9:0 RW/L 3FFh 0/0/0/PCI 98–99h 03FFh RO, RW/L 16 bits Description Reserved Remap Base Address [35:26] (REMAPBASE): The value in this register defines the lower boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[25:0] of the Remap Base Address are assumed to be 0s.
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DRAM Controller Registers (D0:F0) 5.1.27 SMRAM—System Management RAM Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 9Dh 02h RO, RW/L, RW, RW/L/K 8 bits The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
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DRAM Controller Registers (D0:F0) 5.1.28 ESMRAMC—Extended System Management RAM Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI 9Eh 38h RW/L, RWC, RO 8 bits The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MB. Bit Access Default Value Description 7 RW/L 0b Enable High SMRAM (H_SMRAME): This bit controls the SMM memory space location (i.e.
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DRAM Controller Registers (D0:F0) 5.1.29 TOM—Top of Memory B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI A0–A1h 0001h RO, RW/L 16 bits This Register contains the size of physical memory. BIOS determines the memory size reported to the OS using this Register. Bit Access Default Value 15:10 RO 00h 9:0 5.1.30 RW/L 001h Description Reserved Top of Memory (TOM): This register reflects the total amount of populated physical memory.
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DRAM Controller Registers (D0:F0) 5.1.31 BSM—Base of Stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI A4–A7h 00000000h RW/L, RO 32 bits This register contains the base address of stolen DRAM memory. BIOS determines the base of stolen memory by subtracting the stolen memory size (PCI Device 0 offset 52 bits [6:4]) from TOLUD (PCI Device 0 offset B0 bits [15:04]). Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set.
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DRAM Controller Registers (D0:F0) 5.1.33 TOLUD—Top of Low Usable DRAM B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI B0–B1h 0010h RW/L, RO 16 bits This 16 bit register defines the Top of Low Usable DRAM. TSEG, and Stolen Memory are within the DRAM space defined. From the top, MCH optionally claims 1, 2 MB of DRAM for Stolen Memory and 1, 2, or 8 MB of DRAM for TSEG if enabled.
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DRAM Controller Registers (D0:F0) 5.1.34 ERRSTS—Error Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI C8–C9h 0000h RWC/S, RO 16 bits This register is used to report various error conditions via the SERR DMI messaging mechanism. An SERR DMI message is generated on a zero to one transition of any of these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is enabled and generated.
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DRAM Controller Registers (D0:F0) Bit 1 0 92 Access RWC/S RWC/S Default Value Description 0b Multiple-bit DRAM ECC Error Flag (DMERR): If this bit is set to 1, a memory read data transfer had an uncorrectable multiple-bit error. When this bit is set, the address, channel number, and device number that caused the error are logged in the register. Once this bit is set, the fields are locked until the processor clears this bit by writing a 1.
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DRAM Controller Registers (D0:F0) 5.1.35 ERRCMD—Error Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI CA–CBh 0000h RW, RO 16 bits This register controls the MCH responses to various system errors. Since the MCH does not have an SERRB signal, SERR messages are passed from the MCH to the ICH over DMI. When a bit in this register is set, a SERR message will be generated on DMI whenever the corresponding flag is set in the ERRSTS register.
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DRAM Controller Registers (D0:F0) 5.1.36 SMICMD—SMI Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI CC–CDh 0000h RO, RW 16 bits This register enables various errors to generate an SMI DMI special cycle. When an error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers, respectively. Note that one and only one message type can be enabled.
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DRAM Controller Registers (D0:F0) 5.1.38 CAPID0—Capability Identifier B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/0/0/PCI E0–EBh 00000001C1064000010C0009h RO 96 bits 0h This register provides control of bits in this register are only required for customer visible component differentiation.
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DRAM Controller Registers (D0:F0) Bit Access Default Value 46 RO 1b Description Reserved Primary PCI Express Port x16 Disable (PEX16D): 0 = Capable of x16 PCI Express Port. 45 RO 0b 1 = Not Capable of x16 PCI Express port; instead PCI Express is limited to x8 and below. This causes PCI Express port to enable and train logical lanes [7:0] only. Logical lanes [15:8] are powered down, and the Max Link Width field of the Link Capability register reports x8 instead of x16.
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DRAM Controller Registers (D0:F0) Bit 31:30 Access RO Default Value 00b Description DDR Frequency Capability (DDRFC): This field controls which values may be written to the Memory Frequency Select field [6:4] of the Clocking Configuration registers (MCHBAR Offset C00h). Any attempt to write an unsupported value will be ignored.
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DRAM Controller Registers (D0:F0) 5.2 MCHBAR Table 9.
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DRAM Controller Registers (D0:F0) Table 9.
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DRAM Controller Registers (D0:F0) 5.2.1 CHDECMISC—Channel Decode Misc B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 111h 00h RW/L 8 bits This register provides miscellaneous CHDEC/MAGEN configuration bits.
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DRAM Controller Registers (D0:F0) 5.2.2 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 200–201h 0000h RO, RW/L 16 bits The DRAM Rank Boundary Registers define the upper boundary address of each DRAM rank with a granularity of 64MB. Each rank has its own single-word DRB register. These registers are used to determine which chip select will be active for a given address.
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DRAM Controller Registers (D0:F0) C1DRB1 = C0DRB3 + Total memory in ch1 rank0 + ch1 rank1 (in 64MB increments) (rank 1 is the topmost populated rank) C1DRB2 = C1DRB1 C1DRB3 = C1DRB1 C1DRB3: C1DRB3 = C0DRB3 + Total memory in Channel 1.
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DRAM Controller Registers (D0:F0) 5.2.4 C0DRB2—Channel 0 DRAM Rank Boundary Address 2 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 204–205h 0000h RW/L, RO 16 bits See C0DRB0 register.
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DRAM Controller Registers (D0:F0) 5.2.6 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 208–209h 0000h RW/L 16 bits The DRAM Rank Attribute Registers define the page sizes/number of banks to be used when accessing different ranks. These registers should be left with their default value (all zeros) for any rank that is unpopulated, as determined by the corresponding CxDRB registers.
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DRAM Controller Registers (D0:F0) 5.2.7 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 20A–20Bh 0000h RW/L 16 bits See C0DRA01 register. Bit 15:8 Access RW/L Default Value 00h Description Channel 0 DRAM Rank-3 Attributes (C0DRA3): This register defines DRAM pagesize/number-of-banks for rank3 for given channel. See table in register description for programming. This register is locked by ME stolen Memory lock.
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DRAM Controller Registers (D0:F0) 5.2.9 C0CYCTRKACT—Channel 0 CYCTRK ACT B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 252–255h 00000000h RW, RO 32 bits Channel 0 CYCTRK Activate registers. Bit Access Default Value 31:28 RO 0h Description Reserved ACT Window Count (C0sd_cr_act_windowcnt): This field indicates the window duration (in DRAM clocks) during which the controller counts the # of activate commands which are launched to a particular rank.
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DRAM Controller Registers (D0:F0) 5.2.10 C0CYCTRKWR—Channel 0 CYCTRK WR B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 256–257h 0000h RW 16 bits Channel 0 CYCTRK WR registers. Bit Access Default Value Description 15:12 RW 0h ACT To Write Delay (C0sd_cr_act_wr): This field indicates the minimum allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the same rank-bank. This field corresponds to tRCD_wr in the DDR Specificaiton.
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DRAM Controller Registers (D0:F0) 5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 258–25Ah 000000h RO, RW 24 bits Channel 0 CYCTRK RD registers. Bit Access Default Value 23:21 RO 000b 20:17 RW Description Reserved 0h Min ACT To READ Delayed (C0sd_cr_act_rd): This field indicates the minimum allowed spacing (in DRAM clocks) between the ACT and READ commands to the same rank-bank.
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DRAM Controller Registers (D0:F0) 5.2.13 C0CKECTRL—Channel 0 CKE Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 260–263h 00000800h RW, RW/L, RO 32 bits This register provides CKE controls for Channel 0.
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DRAM Controller Registers (D0:F0) 5.2.14 C0REFRCTRL—Channel 0 DRAM Refresh Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 269–26Eh 021830000C30h RW, RO 48 bits This register provides the settings to configure the DRAM refresh controller.
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DRAM Controller Registers (D0:F0) Bit Access Default Value Description DRAM Refresh High Watermark (REFHIGHWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_high flag is set. 17:16 RW 00b 00 = 3 01 = 4 10 = 5 11 = 6 DRAM Refresh Low Watermark (REFLOWWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_low flag is set.
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DRAM Controller Registers (D0:F0) 5.2.15 C0ECCERRLOG—Channel 0 ECC Error Log B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 280–287h 0000000000000000h RO/P, RO 64 bits This register is used to store the error status information in ECC enabled configurations, along with the error syndrome and the rank/bank/row/column address information of the address block of main memory of which an error (single bit or multibit error) has occurred.
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DRAM Controller Registers (D0:F0) 5.2.16 C0ODTCTRL—Channel 0 ODT Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 29C–29Fh 00000000h RO, RW 32 bits This register provides ODT controls. Bit Access Default Value 31:12 RO 00000h 11:8 RW 0h DRAM ODT for Read Commands (sd0_cr_odt_duration_rd): Specifies the duration in MDCLKs to assert DRAM ODT for Read Commands. The Async value should be used when the Dynamic Powerdown bit is set. Else use the Sync value.
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DRAM Controller Registers (D0:F0) 5.2.18 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 602–603h 0000h RO, RW/L 16 bits The operation of this register is detailed in the description for the C0DRB0 register. Bit Access 15:10 RO Default Value Description 000000b Reserved Channel 1 DRAM Rank Boundary Address 1 (C1DRBA1): See C0DRB1 register.
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DRAM Controller Registers (D0:F0) 5.2.20 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 606–607h 0000h RW/L, RO 16 bits The operation of this register is detailed in the description for C0DRB0 register. Bit Access 15:10 RO 9:0 RW/L Default Value Description 000000b Reserved 000h Channel 1 DRAM Rank Boundary Address 3 (C1DRBA3): See C0DRB3 register. In stacked mode, this will be cumulative of Ch0 DRB3.
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DRAM Controller Registers (D0:F0) 5.2.23 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 650–651h 0000h RW, RO 16 bits Channel 1 CYCTRK Precharge registers. Bit Access Default Value 15:11 RO 00000b Reserved 10:6 RW 00000b Write To PRE Delayed (C1sd_cr_wr_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the same rank-bank. This field corresponds to tWR in the DDR Specification.
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DRAM Controller Registers (D0:F0) 5.2.24 C1CYCTRKACT—Channel 1 CYCTRK ACT B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 652–655h 00000000h RO, RW 32 bits Channel 1 CYCTRK ACT registers. Bit Access Default Value 31:28 RO 0h Description Reserved ACT Window Count (C1sd_cr_act_windowcnt): This field indicates the window duration (in DRAM clocks) during which the controller counts the # of activate commands which are launched to a particular rank.
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DRAM Controller Registers (D0:F0) 5.2.25 C1CYCTRKWR—Channel 1 CYCTRK WR B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 656–657h 0000h RW 16 bits Channel 1 CYCTRK WR registers. Bit Access Default Value Description 15:12 RW 0h ACT To Write Delay (C1sd_cr_act_wr): This field indicates the minimum allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the same rank-bank. This field corresponds to tRCD_wr in the DDR Specification.
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DRAM Controller Registers (D0:F0) 5.2.27 C1CKECTRL—Channel 1 CKE Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 660–663h 00000800h RO, RW/L, RW 32 bits Channel 1 CKE Control registers.
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DRAM Controller Registers (D0:F0) 5.2.28 C1REFRCTRL—Channel 1 DRAM Refresh Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 669–66Eh 021830000C30h RW, RO 48 bits This register provides the settings to configure the DRAM refresh controller.
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DRAM Controller Registers (D0:F0) Bit Access Default Value Description DRAM Refresh High Watermark (REFHIGHWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_high flag is set. 17:16 RW 00b 00 = 3 01 = 4 10 = 5 11 = 6 DRAM Refresh Low Watermark (REFLOWWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_low flag is set.
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DRAM Controller Registers (D0:F0) Bit Access Default Value Description Error Rank Address (ERRRANK): Rank address of the address block of main memory of which an error (single bit or multi-bit error) has occurred. 28:27 RO/P 00b 00 = rank 0 (DIMM0) 01 = rank 1 (DIMM0) 10 = rank 2 (DIMM1) 11 = rank 3 (DIMM1) 26:24 RO 0h 23:16 RO/P 00h 15:2 RO 0h Reserved 0b Multiple Bit Error Status (MERRSTS): This bit is set when an uncorrectable multiple-bit error occurs on a memory read data transfer.
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DRAM Controller Registers (D0:F0) 5.2.31 EPC0DRB0—EP Channel 0 DRAM Rank Boundary Address 0 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:10 RO 9:0 RW 5.2.32 0/0/0/MCHBAR A00–A01h 0000h RW, RO 16 bits Default Value Description 000000b Reserved 000h Channel 0 Dram Rank Boundary Address 0 (C0DRBA0): EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR A02–A03h 0000h RW, RO 16 bits See C0DRB0 register.
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DRAM Controller Registers (D0:F0) 5.2.34 EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR A06–A07h 0000h RW, RO 16 bits See C0DRB0 register. Bit Access 15:10 RO 9:0 RW 5.2.
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DRAM Controller Registers (D0:F0) 5.2.36 EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR A0A–A0Bh 0000h RW 16 bits See C0DRA01 register. Bit Access Default Value 15:8 RW 00h Channel 0 DRAM Rank-3 Attributes (C0DRA3): This register defines DRAM pagesize/number-of-banks for rank3 for given channel.
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DRAM Controller Registers (D0:F0) 5.2.38 EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR A1C–A1Fh 00000000h RO, RW 32 bits EPD CYCTRK WRT ACT Status registers. Bit Access Default Value 31:21 RO 000h 20:17 RW 0000b ACT to ACT Delayed (C0sd_cr_act_act[): This configuration register indicates the minimum allowed spacing (in DRAM clocks) between two ACT commands to the same rank.
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DRAM Controller Registers (D0:F0) 5.2.40 EPDCYCTRKWRTREF—EPD CYCTRK WRT REF B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/0/0/MCHBAR A22–A23h 0000h RO, RW 16 bits 0h EPD CYCTRK WRT ACT Status registers. Bit Access Default Value 15:9 RO 0s 8:0 RW 5.2.
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DRAM Controller Registers (D0:F0) 5.2.42 EPDCKECONFIGREG—EPD CKE Related Configuration B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/0/0/MCHBAR A28–A2Ch 00E0000000h RW 40 bits 0h CKE related configuration registers For EPD. Bit Access Default Value 39:35 RW 00000b 34:32 RW 000b 31:29 RW 111b Description EPDunit TXPDLL Count (EPDTXPDLL): Specifies the delay from precharge power down exit to a command that requires the DRAM DLL to be operational.
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DRAM Controller Registers (D0:F0) Bit Access Default Value Description 0 RW 0b Indicates Only 1 Rank Enabled (sd0_cr_singledimmpop): This field indicates the that only 1 rank is enabled. This bit needs to be set if there is one active rank and no odt ranks, or if there is one active rank and one ODT rank and they are the same rank. 5.2.
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DRAM Controller Registers (D0:F0) Bit Access Default Value Description DRAM Refresh High Watermark (REFHIGHWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_high flag is set. 21:18 RW 0000b 0000 = 0 0001 = 1 ....... 1000 = 8 DRAM Refresh Low Watermark (REFLOWWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_low flag is set. 17:14 RW 0000b 0000 = 0 0001 = 1 .......
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DRAM Controller Registers (D0:F0) 5.2.44 TSC1—Thermal Sensor Control 1 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CD8h 00h RW/L, RW, RS/WC 8 bits This register controls the operation of the thermal sensor. Bits 7:1 of this register are reset to their defaults by MPWROK. Bit 0 is reset to it's default by PLTRST#. Bit 7 Access RW/L Default Value 0b Description Thermal Sensor Enable (TSE): This bit enables power to the thermal sensor. Lockable via TCO bit [7].
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DRAM Controller Registers (D0:F0) Bit Access Default Value Description In Use (IU): Software semaphore bit. After a full MCH RESET, a read to this bit returns a 0. After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next read value to 0. Writing a 0 to this bit has no effect. 0 RS/WC 0b Software can poll this bit until it reads a 0, and will then own the usage of the thermal sensor.
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DRAM Controller Registers (D0:F0) Bit Access Default Value Description Thermometer Mode Enable and Rate (TE): If analog thermal sensor mode is not enabled by setting these bits to 0000b, these bits enable the thermometer mode functions and set the Thermometer controller rate. When the Thermometer mode is disabled and TSC1[TSE] =enabled, the analog sensor mode should be fully functional.
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DRAM Controller Registers (D0:F0) 5.2.46 TSS—Thermal Sensor Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CDAh 00h RO 8 bits This read only register provides trip point and other status of the thermal sensor. All bits in this register are reset to their defaults by MPWROK. Bit Access Default Value 7 RO 0b Catastrophic Trip Indicator (CTI): A 1 indicates that the internal thermal sensor temperature is above the catastrophic setting.
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DRAM Controller Registers (D0:F0) 5.2.47 TSTTP—Thermal Sensor Temperature Trip Point B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CDC–CDFh 00000000h RO, RW, RW/L 32 bits This register provides the following: • Sets the target values for the trip points in thermometer mode. See also TST[Direct DAC Connect Test Enable]. • Reports the relative thermal sensor temperature. All bits in this register are reset to their defaults by MPWROK.
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DRAM Controller Registers (D0:F0) 5.2.
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DRAM Controller Registers (D0:F0) 5.2.49 THERM1—Thermal Hardware Protection B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CE4h 00h RW/L, RO, RW/L/K 8 bits All bits in this register are reset to their defaults by PLTRST#. Bit Access Default Value 7:4 RO 0b Description Reserved Halt on Catastrophic (HOC): 3 RW/L 0b 2:1 RO 00b 0 RW/L/K 0b 0 = Continue to toggle clocks when the catastrophic sensor trips. 1 = All clocks are disabled when the catastrophic sensor trips.
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DRAM Controller Registers (D0:F0) Bit Access Default Value 15:10 RO 00h Description Reserved Was Catastrophic Thermal Sensor Interrupt Event (WCTSIE): 9 RWC 0b 1 = Indicates that a Catastrophic Thermal Sensor trip based on a higher to lower temperature transition thru the trip point. 0 = No trip for this event Was Hot Thermal Sensor Interrupt Event (WHTSIE): 8 RWC 0b 1 = Indicates that a Hot Thermal Sensor trip based on a higher to lower temperature transition thru the trip point.
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DRAM Controller Registers (D0:F0) 5.2.51 TSMICMD—Thermal SMI Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR CF1h 00h RO, RW 8 bits This register selects specific errors to generate a SMI DMI special cycle, as enabled by the Device 0 SMI Error Command Register [SMI on MCH Thermal Sensor Trip]. The SMI must not be enabled at the same time as the SERR/SCI for the thermal sensor event. All bits in this register are reset to their defaults by PLTRST#.
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DRAM Controller Registers (D0:F0) 5.2.52 PMSTS—Power Management Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR F14–F17h 00000000h RWC/S, RO 32 bits This register is Reset by PWROK only. Bit Access 31:9 RO Default Value Description 000000h Reserved Warm Reset Occurred (WRO): Set by the PMunit whenever a Warm Reset is received, and cleared by PWROK=0. 0 = No Warm Reset occurred. 8 RWC/S 0b 1 = Warm Reset occurred.
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DRAM Controller Registers (D0:F0) 5.3 EPBAR Table 11. EPBAR Address Map 5.3.
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DRAM Controller Registers (D0:F0) 5.3.2 EPLE1D—EP Link Entry 1 Description B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PXPEPBAR 50–53h 01000000h RO, RWO 32 bits This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element. Bit 31:24 Access RO Default Value 01h Description Target Port Number (TPN): Specifies the port number associated with the element targeted by this link entry (DMI).
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DRAM Controller Registers (D0:F0) 5.3.4 EPLE2D—EP Link Entry 2 Description B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PXPEPBAR 60–63h 02000002h RO, RWO 32 bits This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element. Bit 31:24 23:16 Access RO RWO Default Value Description 02h Target Port Number (TPN): Specifies the port number associated with the element targeted by this link entry (PCI Express).
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DRAM Controller Registers (D0:F0) 5.3.6 EPLE3D—EP Link Entry 3 Description B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PXPEPBAR 70–73h 03000002h RO, RWO 32 bits This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element. Bit 31:24 23:16 Access RO RWO Default Value Description 03h Target Port Number (TPN): Specifies the port number associated with the element targeted by this link entry (PCI Express).
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DRAM Controller Registers (D0:F0) 5.3.7 EPLE3A—EP Link Entry 3 Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PXPEPBAR 78–7Fh 0000000000008000h RO 64 bits This register provides the second part of a Link Entry which declares an internal link to another Root Complex Element. Default Value Bit Access 63:28 RO 27:20 RO 00h 19:15 RO 00001b Description 0000000 Reserved 00h Bus Number (BUSN): Device Number (DEVN): Target for this link is PCI Express port (Device6).
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DRAM Controller Registers (D0:F0) 146 Datasheet
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6 Host-Primary PCI Express* Bridge Registers (D1:F0) Device 1 contains the controls associated with the PCI Express root port that is the intended attach point for external devices. In addition, it also functions as the virtual PCI-to-PCI bridge. The table below provides an address map of the D1:F0 registers listed by address offset in ascending order. This chapter provides a detailed bit description of the registers.
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Host-Primary PCI Express* Bridge Registers (D1:F0) Table 12.
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Host-Primary PCI Express* Bridge Registers (D1:F0) Table 12. 6.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.2 DID1—Device Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 2–3h 29F1h RO 16 bits This register combined with the Vendor Identification register uniquely identifies any PCI device. Bit Access Default Value 15:8 RO 29h Device Identification Number (DID1(UB)): Identifier assigned to the MCH device 1 (virtual PCI-to-PCI bridge, PCI Express port).
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Host-Primary PCI Express* Bridge Registers (D1:F0) Bit Access Default Value 8 RW 0b 7 RO 0b 6 RW 0b 5:3 RO 0b Description SERR# Message Enable (SERRE1): Controls Device 1 SERR# messaging. The MCH communicates the SERR# condition by sending an SERR message to the ICH. This bit, when set, enables reporting of non-fatal and fatal errors detected by the device to the Root Complex.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.4 PCISTS1—PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 6–7h 0010h RO, RWC 16 bits This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express bridge embedded within the MCH. Bit Access Default Value Description 15 RO 0b Detected Parity Error (DPE): Not Applicable or Implemented. Hardwired to 0.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.5 RID1—Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 8h see table below RO 8 bits This register contains the revision number of the MCH device 1. These bits are read only and writes to this register have no effect. Bit Access 7:0 RO 6.6 Default Value Description Revision Identification Number (RID1): This is an 8-bit value that indicates the revision identification number for the MCH Device 0.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.7 CL1—Cache Line Size B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 7:0 RW 00h 6.8 0/1/0/PCI Ch 00h RW 8 bits Description Cache Line Size (Scratch pad): Implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no impact on any PCI Express device functionality.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.10 SBUSN1—Secondary Bus Number B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 19h 00h RW 8 bits This register identifies the bus number assigned to the second bus side of the "virtual" bridge. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express. Bit Access Default Value 7:0 RW 00h 6.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.12 IOBASE1—I/O Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 1Ch F0h RO, RW 8 bits This register controls the processor to PCI Express I/O access routing based on the following formula: IO_BASE ≤address ≤IO_LIMIT Only upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be aligned to a 4 KB boundary.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.14 SSTS1—Secondary Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 1E–1Fh 0000h RO, RWC 16 bits SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side of the "virtual" PCI-PCI bridge embedded within MCH.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.15 MBASE1—Memory Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 20–21h FFF0h RW, RO 16 bits This register controls the processor to PCI Express non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤address ≤MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.16 MLIMIT1—Memory Limit Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 22–23h 0000h RW, RO 16 bits This register controls the processor to PCI Express non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤address ≤MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.19 PMBASEU1—Prefetchable Memory Base Address Upper B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 28–2Bh 00000000h RW 32 bits The functionality associated with this register is present in the PCI Express design implementation.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.20 PMLIMITU1—Prefetchable Memory Limit Address Upper B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 2C–2Fh 00000000h RW 32 bits The functionality associated with this register is present in the PCI Express design implementation.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.22 INTRLINE1—Interrupt Line B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 3Ch 00h RW 8 bits This register contains interrupt line routing information. The device itself does not use this value, rather it is used by device drivers and operating systems to determine priority and vector information.
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Host-Primary PCI Express* Bridge Registers (D1:F0) Bit Access Default Value 9 RO 0b Secondary Discard Timer (SDT): Not Applicable or Implemented. Hardwired to 0. 8 RO 0b Primary Discard Timer (PDT): Not Applicable or Implemented. Hardwired to 0. 7 RO 0b Fast Back-to-Back Enable (FB2BEN): Not Applicable or Implemented. Hardwired to 0. 6 RW 0b Secondary Bus Reset (SRESET): Setting this bit triggers a hot reset on the corresponding PCI Express Port.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.25 PM_CAPID1—Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 0/1/0/PCI 80–83h C8039001h RO 32 bits Default Value Description PME Support (PMES): This field indicates the power states in which this device may indicate PME wake via PCI Express messaging. D0, D3hot & D3cold. This device is not required to do anything to support D3hot & D3cold, it simply must report that those states are supported.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.26 PM_CS1—Power Management Control/Status B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 31:16 RO 0000h 15 RO 0b 14:13 RO 00b 12:9 RO 0h 0/1/0/PCI 84–87h 00000008h RO, RW, RW/P 32 bits Description Reserved PME Status (PMESTS): This bit indicates that this device does not support PMEB generation from D3cold.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 88–8Bh 0000800Dh RO 32 bits This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. However, it is necessary because Microsoft will test for its presence.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.29 MSI_CAPID—Message Signaled Interrupts Capability ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI 90–91h A005h RO 16 bits When a device supports MSI, it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.31 MA—Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:2 RW 1:0 RO 6.32 Default Value Description Message Address (MA): Used by system software to assign an MSI address to 0000000 the device. The device handles an MSI by writing the padded contents of the MD 0h register to this address.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.34 PE_CAP—PCI Express* Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI A2–A3h 0142h RO, RWO 16 bits This register indicates PCI Express device capabilities. Bit Access Default Value 15:14 RO 00b Reserved 13:9 RO 00h Interrupt Message Number (IMN): Not Applicable or Implemented. Hardwired to 0.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.36 DCTL—Device Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI A8–A9h 0000h RW, RO 16 bits This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.37 DSTS—Device Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI AA–ABh 0000h RO, RWC 16 bits This register provides the reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this device, not errors messages received across the link.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.38 LCAP—Link Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI AC–AFh 02214D01h RO, RWO 32 bits This register indicates PCI Express device specific capabilities. Bit Access Default Value 31:24 RO 02h 23:22 RO 000b 21 RO 1b Description Port Number (PN): This field indicates the PCI Express port number for the given PCI Express link. Matches the value in Element Self Description[31:24].
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Host-Primary PCI Express* Bridge Registers (D1:F0) Bit Access Default Value Description L0s Exit Latency (L0SELAT): Indicates the length of time this Port requires to complete the transition from L0s to L0.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.39 LCTL—Link Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI B0–B1h 0000h RO, RW, RW/SC 16 bits This register allows control of PCI Express link. Bit Access Default Value 15:12 RO 0000b Description Reserved Link Autonomous Bandwidth Interrupt Enable: When set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set.
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Host-Primary PCI Express* Bridge Registers (D1:F0) Bit Access Default Value Description Common Clock Configuration (CCC): 6 RW 0b 0 = Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock. 1 = Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.40 LSTS—Link Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI B2–B3h 1000h RWC, RO 16 bits This register indicates PCI Express link status.
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Host-Primary PCI Express* Bridge Registers (D1:F0) Bit 9:4 Access RO Default Value 00h Description Negotiated Link Width (NLW): Indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed). 01h = x1 10h = x16 All other encodings are reserved. Current Link Speed (CLS): This field indicates the negotiated Link speed of the given PCI Express Link. 3:0 RO 0h 0001b = 2.
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Host-Primary PCI Express* Bridge Registers (D1:F0) Bit Access Default Value 2 RO 0b MRL Sensor Present (MSP): When set to 1b, this bit indicates that an MRL Sensor is implemented on the chassis for this slot. 1 RO 0b Power Controller Present (PCP): When set to 1b, this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor).
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Host-Primary PCI Express* Bridge Registers (D1:F0) Bit Access Default Value Description Power Indicator Control (PIC): If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.43 SLOTSTS—Slot Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI BA–BBh 0000h RO, RWC 16 bits PCI Express Slot related registers.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.44 RCTL—Root Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI BC–BDh 0000h RO, RW 16 bits This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.45 RSTS—Root Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/PCI C0–C3h 00000000h RO, RWC 32 bits This register provides information about PCI Express Root Complex specific parameters. Bit Access Default Value 31:18 RO 0000h Description Reserved 17 RO 0b PME Pending (PMEP): Indicates that another PME is pending when the PME Status bit is set.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.47 VCECH—Virtual Channel Enhanced Capability Header B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 100–103h 14010002h RO 32 bits This register indicates PCI Express device Virtual Channel capabilities. Extended capability structures for PCI Express devices are located in PCI Express extended configuration space and have different field definitions than standard PCI capability structures.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.49 PVCCAP2—Port VC Capability Register 2 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 108–10Bh 00000000h RO 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit Access Default Value 31:24 RO 00h 23:0 RO 0000h 6.50 Description VC Arbitration Table Offset (VCATO): Indicates the location of the VC Arbitration Table.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.51 VC0RCAP—VC0 Resource Capability B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 31:16 RO 0000h 0/1/0/MMR 110–113h 00000001h RO 32 bits Description Reserved Reject Snoop Transactions (RSNPT): 15 RO 0b 14:8 RO 0000h 0 = Transactions with or without the No Snoop bit set within the Transaction Layer Packet header are allowed on this VC.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.52 VC0RCTL—VC0 Resource Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 114–117h 800000FFh RO, RW 32 bits This register controls the resources associated with PCI Express Virtual Channel 0. Bit Access Default Value 31 RO 1b VC0 Enable (VC0E): For VC0, this is hardwired to 1 and read only as VC0 can never be disabled.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.53 VC0RSTS—VC0 Resource Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 11A–11Bh 0002h RO 16 bits This register reports the Virtual Channel specific status. Bit Access Default Value 15:2 RO 0000h Description Reserved VC0 Negotiation Pending (VC0NP): 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.55 ESD—Element Self Description B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 144–147h 02000100h RO, RWO 32 bits This register provides information about the root complex element containing this Link Declaration Capability. Bit Access Default Value 31:24 RO 02h Port Number (PN): Specifies the port number associated with this element with respect to the component that contains this element.
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Host-Primary PCI Express* Bridge Registers (D1:F0) 6.57 LE1A—Link Entry 1 Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/1/0/MMR 158-15Fh 0000000000000000h RO, RWO 64 bits This register provides the second part of a Link Entry which declares an internal link to another Root Complex Element. Default Value Bit Access 63:32 RO 31:12 RWO 00000h 11:0 RO 000h 6.
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Host-Primary PCI Express* Bridge Registers (D1:F0) §§ 192 Datasheet
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7 Intel Manageability Engine Subsystem PCI (D3:F0,F3) This chapter provides the registers for Device 3 (D3), Functions 0 (F0) and 3 (F3). 7.1 HECI Function in ME Subsystem (D3:F0) Device 3 contains registers for the Intel Manageability Engine. The table below lists the PCI configuration registers in order of ascending offset address. Note: The following sections describe Device 3 configuration registers only. Table 13.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.1.1 ID—Identifiers B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 0–3h 29F48086h RO 32 bits Bit Access Default Value 31:16 RO 29F4h Device ID (DID): Device ID (DID): This field indicates what device number assigned by Intel. 15:0 RO 8086h Vendor ID (VID): Vendor ID (VID): This field indicates Intel is the vendor, assigned by the PCI SIG. 7.1.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.1.3 STS—Device Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/0/PCI 6–7h 0010h RO 16 bits Bit Access Default Value 15:5 RO 0h Reserved Description 4 RO 1b Capabilities List (CL): Indicates the presence of a capabilities list, hardwired to 1. 3 RO 0b Interrupt Status (IS): Indicates the interrupt status of the device 1 = Asserted 2:0 RO 000b 7.1.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.1.6 CLS—Cache Line Size B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 7:0 RO 00h 7.1.7 Description Cache Line Size (CLS): Not implemented, hardwired to 0. MLT—Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 7:0 RO 00h 7.1.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.1.9 HECI_MBAR—HECI MMIO Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: Default Value Bit Access 63:4 RW 3 RO 0b 2:1 RO 10b 0 RO 0b 7.1.10 0/3/0/PCI 10–17h 0000000000000004h RO, RW 64 bits Description 0000000 0000000 Base Address (BA): Base address of register memory space.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.1.11 CAP—Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 7:0 RO 50h 7.1.12 Description Capability Pointer (CP): Indicates the first capability pointer offset. It points to the PCI power management capability offset.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.1.14 MLAT—Maximum Latency B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 7:0 RO 00h 7.1.15 Description Latency (LAT): Not implemented, hardwired to 0. HFS—Host Firmware Status B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:0 RO 7.1.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.1.17 PC—PCI Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 15:11 RO 11001b 10 RO 0b 9 RO 0b 0/3/0/PCI 52–53h C803h RO 16 bits Description PME_Support (PSUP): Indicates the states that can generate PME#. HECI can assert PME# from any D-state except D1 or D2 which are not supported by HECI. D2_Support (D2S): The D2 state is not supported for the HECI host controller.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) Bit Access Default Value Description 3 RO 1b No_Soft_Reset (NSR): This bit indicates that when the HECI host controller is transitioning from D3hot to D0 due to power state command, it does not perform an internal reset. 2 RO 0b Reserved Power State (PS): This field is used both to determine the current power state of the HECI host controller and to set a new power state.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.1.21 MA—Message Signaled Interrupt Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:2 RW 1:0 RO 7.1.22 Default Value Description 0000000 Address (ADDR): Lower 32 bits of the system specified message address, 0h always DW aligned. 00b Reserved MUA—Message Signaled Interrupt Upper Address (Optional) B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:0 RW 7.1.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.1.24 HIDM—HECI Interrupt Delivery Mode B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/3/0/PCI A0h 00h RW 8 bits 00h This register is used to select interrupt delivery mechanism for HECI to Host processor interrupts.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.2 KT IO/ Memory Mapped Device Specific Registers [D3:F3] Table 14. KT IO/Memory Mapped Register Address Map 7.2.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.2.2 KTTHR—KT Transmit Holding B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/KT MM/IO 0h 00h WO 8 bits This implements the KT Transmit Data register. Host access to this address, depends on the state of the DLAB bit {KTLCR[7]). It must be 0 to access the KTTHR. THR: When host wants to transmit data in the non-FIFO mode, it writes to this register.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.2.4 KTIER—KT Interrupt Enable B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/KT MM/IO 1h 00h RW/V, RO/V 8 bits This implements the KT Interrupt Enable register. Host access to this address, depends on the state of the DLAB bit {KTLCR[7]). It must be "0" to access this register. The bits enable specific events to interrupt the Host. See bit specific definition. Note: Reset: Host System Reset or D3 -> D0 transition.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.2.6 KTIIR—KT Interrupt Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/KT MM/IO 2h 01h RO 8 bits The KT IIR register prioritizes the interrupts from the function into 4 levels and records them in the IIR_STAT field of the register. When Host accesses the IIR, hardware freezes all interrupts and provides the priority to the Host.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.2.7 KTFCR—KT FIFO Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/KT MM/IO 2h 00h WO 8 bits When Host writes to this address, it writes to the KTFCR. The FIFO control Register of the serial interface is used to enable the FIFO's, set the receiver FIFO trigger level and clear FIFO's under the direction of the Host. When Host reads from this address, it reads the KTIIR. Note: Bit Reset: Host System Reset or D3->D0 transition.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.2.8 KTLCR—KT Line Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/KT MM/IO 3h 03h RW 8 bits The line control register specifies the format of the asynchronous data communications exchange and sets the DLAB bit. Most bits in this register have no affect on hardware and are only used by the FW. Note: Reset: Host System Reset or D3->D0 transition.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.2.9 KTMCR—KT Modem Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/KT MM/IO 4h 00h RO, RW 8 bits The Modem Control Register controls the interface with the modem. Since the FW emulates the modem, the Host communicates to the FW via this register. Register has impact on hardware when the Loopback mode is on. Note: Reset: Host system Reset or D3->D0 transition.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.2.10 KTLSR—KT Line Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/KT MM/IO 5h 00h RO, RO/CR 8 bits This register provides status information of the data transfer to the Host. Error indication, etc., are provided by the hardware(HW)/firmware(FW) to the host via this register. Note: Reset: Host system reset or D3->D0 transition.
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Intel Manageability Engine Subsystem PCI (D3:F0,F3) 7.2.11 KTMSR—KT Modem Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/3/3/KT MM/IO 6h 00h RO, RO/CR 8 bits The functionality of the Modem is emulated by the FW. This register provides the status of the current state of the control lines from the modem. Note: Reset: Host system Reset or D3->D0 transition.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8 Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) Note: The Device 6 register descriptions provided in this chapter applies only to the 3210 MCH in dual x8 mode. Device 6 contains the controls associated with the PCI Express root port that is the intended attach point for external devices. In addition, it also functions as the virtual PCI-to-PCI bridge.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) Table 15.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) Table 15. 8.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.2 DID1—Device Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 2–3h 29F9h RO 16 bits This register combined with the Vendor Identification register uniquely identifies any PCI device. Bit Access Default Value 15:8 RO 29h Device Identification Number (DID1(UB)): Identifier assigned to the MCH device #6 (virtual PCI-to-PCI bridge, PCI Express port).
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) Bit Access Default Value 8 RW 0b 7 RO 0b 6 RW 0b 5:3 RO 0b Description SERR# Message Enable (SERRE1): This bit controls Device 6 SERR# messaging. The MCH communicates the SERR# condition by sending a SERR message to the ICH. This bit, when set, enables reporting of non-fatal and fatal errors detected by the device to the Root Complex.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.4 PCISTS1—PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 6–7h 0010h RO, RWC 16 bits This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express bridge embedded within the MCH. Bit Access Default Value Description 15 RO 0b Detected Parity Error (DPE): Not Applicable or Implemented. Hardwired to 0.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.5 RID1—Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 8h see table below RO 8 bits This register contains the revision number of the MCH device 6. These bits are read only and writes to this register have no effect. Bit Access 7:0 RO 8.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.7 CL1—Cache Line Size B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 7:0 RW 00h 8.8 0/6/0/PCI Ch 00h RW 8 bits Description Cache Line Size (Scratch pad): Implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no impact on any PCI Express device functionality.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.10 SBUSN1—Secondary Bus Number B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 19h 00h RW 8 bits This register identifies the bus number assigned to the second bus side of the "virtual" bridge. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express. Bit Access Default Value 7:0 RW 00h 8.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.12 IOBASE1—I/O Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 1Ch F0h RO, RW 8 bits This register controls the processor to PCI Express I/O access routing based on the following formula: IO_BASE ≤address ≤IO_LIMIT Only upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are treated as 0.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.14 SSTS1—Secondary Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 1E–1Fh 0000h RO, RWC 16 bits SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side of the "virtual" PCI-PCI bridge embedded within MCH.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.15 MBASE1—Memory Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 20–21h FFF0h RW, RO 16 bits This register controls the processor to PCI Express non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤address ≤MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.16 MLIMIT1—Memory Limit Address B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 22–23h 0000h RW, RO 16 bits This register controls the processor to PCI Express non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤address ≤MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.19 PMBASEU1—Prefetchable Memory Base Address Upper B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 28–2Bh 00000000h RW 32 bits The functionality associated with this register is present in the PCI Express design implementation.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.20 PMLIMITU1—Prefetchable Memory Limit Address Upper B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 2C–2Fh 00000000h RW 32 bits The functionality associated with this register is present in the PCI Express design implementation.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.21 CAPPTR1—Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 34h 88h RO 8 bits The capabilities pointer provides the address offset to the location of the first entry in this device's linked list of capabilities. Bit Access Default Value Description 7:0 RO 88h First Capability (CAPPTR1): The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability. 8.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.24 BCTRL1—Bridge Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 3E–3Fh 0000h RO, RW 16 bits This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The BCTRL provides additional control for the secondary interface as well as some bits that affect the overall behavior of the "virtual" Host-PCI Express bridge embedded within MCH.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) Bit Access Default Value Description SERR Enable (SERREN): 1 0 RW RW 0b 0b 0 = No forwarding of error messages from secondary side to primary side that could result in an SERR. 1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.26 PM_CS1—Power Management Control/Status B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 31:16 RO 0000h 15 RO 0b 14:13 RO 00b 12:9 RO 0h 0/6/0/PCI 84–87h 00000008h RO, RW, RW/P 32 bits Description Reserved PME Status (PMESTS): Indicates that this device does not support PMEB generation from D3cold.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 88–8Bh 0000800Dh RO 32 bits This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.29 MSI_CAPID—Message Signaled Interrupts Capability ID B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 90–91h A005h RO 16 bits When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.31 MA—Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:2 RW 1:0 RO 8.32 Default Value Description Message Address (MA): Used by system software to assign an MSI address to 0000000 the device. The device handles an MSI by writing the padded contents of the MD 0h register to this address.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.34 PE_CAP—PCI Express* Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI A2–A3h 0142h RO, RWO 16 bits This register indicates PCI Express device capabilities. Bit Access Default Value 15:14 RO 00b Reserved 13:9 RO 00h Interrupt Message Number (IMN): Not Applicable or Implemented. Hardwired to 0.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.36 DCTL—Device Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI A8–A9h 0000h RW, RO 16 bits This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.37 DSTS—Device Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI AA–ABh 0000h RO, RWC 16 bits This register reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this device, not errors messages received across the link.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.38 LCAP—Link Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI AC–AFh 03214D01h RO, RWO 32 bits This register indicates PCI Express device specific capabilities. Bit Access Default Value 31:24 RO 03h 23:22 RO 000b 21 RO 1b Description Port Number (PN): This field indicates the PCI Express port number for the given PCI Express link. Matches the value in Element Self Description[31:24].
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) Bit Access Default Value Description L0s Exit Latency (L0SELAT): Indicates the length of time this Port requires to complete the transition from L0s to L0.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.39 LCTL—Link Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI B0–B1h 0000h RO, RW, RW/SC 16 bits This register allows control of PCI Express link. Bit Access 15:12 RO Default Value Description 0000000b Reserved Link Autonomous Bandwidth Interrupt Enable: When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) Bit Access Default Value Description Common Clock Configuration (CCC): 6 RW 0b 0 = Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock. 1 = Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.40 LSTS—Link Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI B2–B3h 1000h RWC, RO 16 bits This register indicates PCI Express link status.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) Bit 9:4 Access RO Default Value 00h Description Negotiated Link Width (NLW): Indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed). 01h = x1 10h = x16 All other encodings are reserved. Current Link Speed (CLS): This field indicates the negotiated Link speed of the given PCI Express Link.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) Bit Access Default Value Description 3 RO 0b Attention Indicator Present (AIP): When set to 1b, this bit indicates that an Attention Indicator is electrically controlled by the chassis. 2 RO 0b MRL Sensor Present (MSP): When set to 1b, this bit indicates that an MRL Sensor is implemented on the chassis for this slot.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) Bit Access Default Value Description Power Indicator Control (PIC): If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.43 SLOTSTS—Slot Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI BA–BBh 0000h RO, RWC 16 bits PCI Express Slot related registers.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.44 RCTL—Root Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI BC–BDh 0000h RO, RW 16 bits This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.45 RSTS—Root Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI C0–C3h 00000000h RO, RWC 32 bits This register provides information about PCI Express Root Complex specific parameters. Bit Access Default Value 31:18 RO 0000h Description Reserved 17 RO 0b PME Pending (PMEP): Indicates that another PME is pending when the PME Status bit is set.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.47 VCECH—Virtual Channel Enhanced Capability Header B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/MMR 100–103h 14010002h RO 32 bits This register indicates PCI Express device Virtual Channel capabilities. Extended capability structures for PCI Express devices are located in PCI Express extended configuration space and have different field definitions than standard PCI capability structures.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.49 PVCCAP2—Port VC Capability Register 2 B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/MMR 108–10Bh 00000000h RO 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit Access Default Value 31:24 RO 00h 23:0 RO 0000h 8.50 Description VC Arbitration Table Offset (VCATO): This field indicates the location of the VC Arbitration Table.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.51 VC0RCAP—VC0 Resource Capability B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 31:16 RO 0000h 0/6/0/MMR 110–113h 00000001h RO 32 bits Description Reserved Reject Snoop Transactions (RSNPT): 15 RO 0b 14:8 RO 0000h 0 = Transactions with or without the No Snoop bit set within the Transaction Layer Packet header are allowed on this VC.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.52 VC0RCTL—VC0 Resource Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/MMR 114–117h 800000FFh RO, RW 32 bits This register controls the resources associated with PCI Express Virtual Channel 0. Bit Access Default Value 31 RO 1b VC0 Enable (VC0E): For VC0, this is hardwired to 1 and read only as VC0 can never be disabled.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.53 VC0RSTS—VC0 Resource Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/MMR 11A–11Bh 0002h RO 16 bits This register reports the Virtual Channel specific status. Bit Access Default Value 15:2 RO 0000h Description Reserved VC0 Negotiation Pending (VC0NP): 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.55 ESD—Element Self Description B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/MMR 144–147h 03000100h RO, RWO 32 bits This register provides information about the root complex element containing this Link Declaration Capability.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 8.56 LE1D—Link Entry 1 Description B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/MMR 150–153h 00000000h RO, RWO 32 bits This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element.
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Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel® 3210 MCH only) 258 Datasheet
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Direct Media Interface (DMI) RCRB 9 Direct Media Interface (DMI) RCRB This Root Complex Register Block (RCRB) controls the MCH-ICH9 serial interconnect. The base address of this space is programmed in DMIBAR in D0:F0 configuration space. Table 16 provides an address map of the DMI registers listed by address offset in ascending order. Note: IMPORTANT: All RCRB register space needs to remain organized as shown here. Table 16.
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Direct Media Interface (DMI) RCRB 9.1 DMIVCECH—DMI Virtual Channel Enhanced Capability B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 0–3h 04010002h RO 32 bits This register indicates DMI Virtual Channel capabilities. Bit Access Default Value Description 31:20 RO 040h Pointer to Next Capability (PNC): This field contains the offset to the next PCI Express capability structure in the linked list of capabilities (Link Declaration Capability).
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Direct Media Interface (DMI) RCRB 9.3 DMIPVCCTL—DMI Port VC Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR C–Dh 0000h RO, RW 16 bits Bit Access Default Value 15:4 RO 000h Reserved 3:1 RW 000b VC Arbitration Select (VCAS): This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field. 0 RO 0b Description See the PCI express specification for more details 9.
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Direct Media Interface (DMI) RCRB 9.5 DMIVC0RCTL0—DMI VC0 Resource Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 14–17h 800000FFh RO, RW 32 bits This register controls the resources associated with PCI Express Virtual Channel 0. Bit Access Default Value 31 RO 1b Virtual Channel 0 Enable (VC0E): For VC0 this is hardwired to 1 and read only as VC0 can never be disabled.
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Direct Media Interface (DMI) RCRB 9.6 DMIVC0RSTS—DMI VC0 Resource Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 1A–1Bh 0002h RO 16 bits This register reports the Virtual Channel specific status. Bit Access Default Value 15:2 RO 0000h Description Reserved Virtual Channel 0 Negotiation Pending (VC0NP): 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
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Direct Media Interface (DMI) RCRB 9.8 DMIVC1RCTL1—DMI VC1 Resource Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 20–23h 01000000h RW, RO 32 bits This register controls the resources associated with PCI Express Virtual Channel 1. Bit Access Default Value 31 RW 0b 0 = Virtual Channel is disabled. 1 = Virtual Channel is enabled.
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Direct Media Interface (DMI) RCRB 9.9 DMIVC1RSTS—DMI VC1 Resource Status B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 26–27h 0002h RO 16 bits This register reports the Virtual Channel specific status. Bit Access Default Value 15:2 RO 0000h Description Reserved Virtual Channel 1 Negotiation Pending (VC1NP): 1 RO 1b 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling). 0 RO 0b Reserved 9.
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Direct Media Interface (DMI) RCRB 9.11 DMILCTL—DMI Link Control B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/DMIBAR 88–89h 0000h RW, RO 16 bits This register allows control of DMI. Bit Access Default Value 15:8 RO 00h Description Reserved Extended Synch (EXTSYNC): 7 RW 0b 0 = Standard Fast Training Sequence (FTS). 1 = Forces the transmission of additional ordered sets when exiting the L0s state and when in the Recovery state.
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Functional Description 10 Functional Description 10.1 Host Interface The MCH supports Dual-Core Intel® Xeon® Processor 3000 Series and Quad-Core Intel® Xeon® Processor 3200 Series processors. The cache line size is 64 bytes. Source synchronous transfer is used for the address and data signals. The address signals are double pumped and a new address can be generated every other bus clock. At 200/ 267/333MHz bus clock the address signals run at 667MT/s.
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Functional Description Table 17. Host Interface 4X, 2X, and 1X Signal Groups Signals Associated Clock or Strobe ADS#, BNR#, BPRI#, DEFER#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, RS[2:0]#, TRDY#, RESET, BR0# BCLK HA[16:3]#, REQ[4:0]# ADSTB[0]# HA[35:17]# ADSTB[1]# D[15:0]#, DBI0# DSTBP0#, DSTBN0# D[31:16]#, DBI1# DSTBP1#, DSTBN1# D[47:32]#, DBI2# DSTBP2#, DSTBN2# D[63:48]#, DBI3# DSTBP3#, DSTBN3# Signal Group 1X 2X 4X 10.1.
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Functional Description 10.2 System Memory Controller The system memory controller supports DDR2 protocol with two independent 64 bit wide channels each accessing one or two DIMMs. It supports a maximum of two unbuffered ECC or non-ECC DDR2 DIMMs per channel thus allowing up to four device ranks per channel. 10.2.1 System Memory Organization Modes The system memory controller supports two memory organization modes, Single Channel and Dual Channel. 10.2.1.
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Functional Description Table 19 is a sample dual channel asymmetric memory configuration showing the rank organization with Intel® Flex Memory Mode Enabled. Table 19. 10.2.1.2.
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Functional Description Table 21. Memory Type Supported DIMM Module Configurations Raw Card Version C D DDR2 E 667 and 800 F G 10.2.
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Functional Description Table 22.
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Functional Description Table 22. Syndrome Bit Values Syndrome Byte 64 54 13 55 C8 56 1A 57 85 58 F4 59 7 60 29 61 46 62 31 63 Every data bit appears in either exactly 3 or exactly 5 check bit and syndrome bit equations. Every check bit appears en exactly 1 syndrome bit equation. This leads to six cases. 1. If the data comes back exactly as it was written, then the calculated check byte will match the stored check byte, and the syndrome will be all 0s. 2.
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Functional Description 10.3 PCI Express* See Section 1.2 for a list of PCI Express features, and the PCI Express specification for further details. This MCH is part of a PCI Express root complex. This means it connects a host processor/memory subsystem to a PCI Express hierarchy. The control registers for this functionality are located in Device 1 and Device 6 configuration space and three Root Complex Register Blocks (RCRBs). The DMI RCRB contains registers for control of the Intel ICH9 attach ports.
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Functional Description 10.4 Thermal Sensor There are several registers that need to be configured to support the MCH thermal sensor functionality and SMI# generation. Customers must enable the Catastrophic Trip Point as protection for the MCH. If the Catastrophic Trip Point is crossed, then the MCH will instantly turn off all clocks inside the device. Customers may optionally enable the Hot Trip Point to generate SMI #.
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Functional Description 10.5 Power Management Power Management Feature List: • ACPI 1.0b support • ACPI S0, S1, S5, C0, C1, and C2 states • Enhanced power management state transitions for increasing time processor spends in low power states • PCI Express Link States: L0, L0s, L2/L3 Ready, L3 10.6 Clocking The MCH has a total of 3 PLLs providing many times that many internal clocks. The PLLs are: • Host PLL – Generates the main core clocks in the host clock domain.
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Functional Description Figure 11.
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Functional Description 278 Datasheet
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Electrical Characteristics 11 Electrical Characteristics This chapter contains the DC specifications for the MCH. 11.1 Absolute Minimum and Maximum Ratings Table 23 specifies the MCH absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
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Electrical Characteristics Table 23. Absolute Minimum and Maximum Ratings Symbol Parameter Min Max Unit 1.25 V PCI Express* and DMI Supply Voltage with respect to VSS -0.3 1.375 V 3.3 V PCI Express* Analog Supply Voltage with respect to VSS -0.3 3.63 V 1.25 V Primary PCI Express* PLL Analog Supply Voltage with respect to VSS -0.3 1.375 V 1.25 V Secondary PCI Express* PLL Analog Supply Voltage with respect to VSS -0.3 1.375 V 1.25 V Supply Voltage with respect to VSS -0.3 1.
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Electrical Characteristics 11.2 Current Consumption Table 24 shows the current consumption for the MCH in the Advanced Configuration and Power Interface (ACPI) S0 state. Icc max values are determined on a per-interface basis, at the highest frequencies for each interface. Sustained current values or Max current values cannot occur simultaneously on all interfaces. Sustained Values are measured sustained RMS maximum current consumption and includes leakage estimates.
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Electrical Characteristics 11.3 Signal Groups The signal description includes the type of buffer used for the particular signal. Type Description PCI Express* PCI Express interface signals. These signals are compatible with PCI Express 2.0 Signaling Environment AC Specifications and are AC coupled. The buffers are not 3.3 V tolerant. Differential voltage spec = (|D+ – D-|) * 2 = 1.2Vmax. Single-ended maximum = 1.25 V. Single-ended minimum = 0 V. DMI GTL+ Open Drain GTL+ interface signal.
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Electrical Characteristics Table 25. Signal Groups Signal Type Signals Notes Host Interface Signal Groups GTL+ Input/Outputs FSB_ADSB, FSB_BNRB, FSB_DBSYB, FSB_DINVB_3:0, FSB_DRDYB, FSB_AB_35:3, FSB_ADSTBB_1:0, FSB_DB_63:0, FSB_DSTBPB_3:0, FSB_DSTBNB_3:0, FSB_HITB, FSB_HITMB, FSB_REQB_4:0 GTL+ Common Clock Outputs FSB_BPRIB, FSB_BREQ0B, FSB_CPURSTB, FSB_DEFERB, FSB_TRDYB, FSB_RSB_2:0 Analog Host I/F Ref & Comp.
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Electrical Characteristics Table 25. Signal Groups Signal Type Signals Notes Clocks HCSL HPL_CLKINP, HPL_CLKINN, EXP_CLKINP, EXP_CLKINN, DPL_REFCLKINN, DPL_REFCLKINP Reset, and Miscellaneous Signal Groups CMOS Input EXP_SLR, PWROK, RSTINB CMOS Output ICH_SYNCB I/O Buffer Supply Voltages System Bus Input Supply Voltage VTT_FSB 1.25 V PCI Express* Supply Voltages VCC_EXP 3.3 V PCI Express* Analog Supply Voltage VCCA_EXP 1.8 V DDR2 Supply Voltage VCC_DDR 1.
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Electrical Characteristics 11.4 Buffer Supply and DC Characteristics 11.4.1 I/O Buffer Supply Voltages The I/O buffer supply voltage is measured at the MCH package pins. The tolerances shown in Table 26 are inclusive of all noise from DC up to 20 MHz. In the lab, the voltage rails should be measured with a bandwidth limited oscilloscope with a roll off of 3 dB/decade above 20 MHz under all operating conditions.
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Electrical Characteristics 11.4.2 General DC Characteristics Platform Reference Voltages at the top of Table 27 are specified at DC only. VREF measurements should be made with respect to the supply voltage. Table 27. DC Characteristics Symbol Parameter Min Nom Max Unit 0.666 x VTT_FSB –2% 0.666 x VTT_FSB 0.666 x VTT_FSB +2% V 0.25 x VTT_FSB –2% 0.25 x VTT_FSB 0.
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Electrical Characteristics Table 27. DC Characteristics Symbol CI/O Parameter Min Nom Max Unit DQ/DQS/DQSB DDR2 Input/ Output Pin Capacitance 1.0 — 4.0 pF Notes 1.25V PCI Express* Interface 2.0 VTX-DIFF P-P Differential Peak to Peak Output Voltage 0.800 — 1.2 V VTX_CM-ACp AC Peak Common Mode Output Voltage — — 20 mV ZTX-DIFF-DC DC Differential TX Impedance 80 100 120 VRX-DIFF p-p Differential Peak to Peak Input Voltage 0.175 — 1.
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Electrical Characteristics Table 27. DC Characteristics Symbol Parameter Min Nom Unit Notes — mA @VOH_HI min — 0.33 V 2.97 — — V IOH Output High Current (CMOS Outputs) -2.0 — VOL Output Low Voltage (CMOS Outputs) — VOH Output High Voltage (CMOS Outputs) Max EXP_SLR, EXP_EN VIL Input Low Voltage -0.10 0 (0.63 x VTT) – 0.1 V VIH Input High Voltage (0.63 x VTT)+0.1 VTT VTT +0.1 V ILEAK Input Leakage Current — — 20 μA CIN Input Capacitance 2 — 2.
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Ballout and Package Information 12 Ballout and Package Information This chapter provides the ballout and package dimensions for the MCH. 12.1 Ballout Information Figure 12, Figure 13, and Figure 14 provide the MCH ballout as viewed from the top side of the package. Table 28 provides a ballout list arranged alphabetically by signal name. Table 29 provides a ballout list arranged numerically by ball number. Note: Notes for Figure 12, Figure 13, Figure 14, Table 28 and Table 29. 1.
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Ballout and Package Information Figure 12.
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Ballout and Package Information Figure 13.
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Ballout and Package Information Figure 14.
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Ballout and Package Information Table 28. MCH Ballout Sorted By Name Datasheet Table 28. MCH Ballout Sorted By Name Table 28.
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Ballout and Package Information Table 28. MCH Ballout Sorted By Name 294 Table 28. MCH Ballout Sorted By Name Table 28.
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Ballout and Package Information Table 28. MCH Ballout Sorted By Name Datasheet Table 28. MCH Ballout Sorted By Name Signal Name Ball # Signal Name DDR_B_DQSB_5 AP40 DDR_B_DQSB_6 AG38 DDR_B_DQSB_7 DDR_B_DQSB_8 Table 28.
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Ballout and Package Information Table 28. MCH Ballout Sorted By Name 296 Table 28. MCH Ballout Sorted By Name Table 28.
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Ballout and Package Information Table 28. MCH Ballout Sorted By Name Signal Name Datasheet Ball # Table 28. MCH Ballout Sorted By Name Signal Name (4) Table 28.
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Ballout and Package Information Table 28. MCH Ballout Sorted By Name 298 Table 28. MCH Ballout Sorted By Name Table 28.
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Ballout and Package Information Table 28. MCH Ballout Sorted By Name Datasheet Table 28. MCH Ballout Sorted By Name Signal Name Ball # Signal Name VCC_DDR BE40 VCC_DDR BE36 VCC_DDR Table 28.
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Ballout and Package Information Table 28. MCH Ballout Sorted By Name 300 Table 28. MCH Ballout Sorted By Name Table 28.
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Ballout and Package Information Table 28. MCH Ballout Sorted By Name Datasheet Table 28. MCH Ballout Sorted By Name Table 28.
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Ballout and Package Information Table 28. MCH Ballout Sorted By Name 302 Table 28.
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Ballout and Package Information Table 29. MCH Ballout Sorted By Ball Datasheet Table 29. MCH Ballout Sorted By Ball Table 29.
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Ballout and Package Information Table 29. MCH Ballout Sorted By Ball 304 Table 29. MCH Ballout Sorted By Ball Table 29.
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Ballout and Package Information Table 29. MCH Ballout Sorted By Ball Ball # Datasheet Signal Name Table 29. MCH Ballout Sorted By Ball Ball # Table 29.
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Ballout and Package Information Table 29. MCH Ballout Sorted By Ball 306 Table 29. MCH Ballout Sorted By Ball Table 29.
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Ballout and Package Information Table 29. MCH Ballout Sorted By Ball Table 29. MCH Ballout Sorted By Ball Ball # Signal Name Ball # Signal Name Ball # Signal Name AF45 DDR_A_DQ_53 AE14 EXP2_CLKINP AD4 PEG2_TXP_1 (4) AD3 PEG2_TXN_2 (4) AD1 VSS AF43 Datasheet Table 29.
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Ballout and Package Information Table 29. MCH Ballout Sorted By Ball 308 Table 29. MCH Ballout Sorted By Ball Table 29.
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Ballout and Package Information Table 29. MCH Ballout Sorted By Ball Ball # Datasheet Table 29. MCH Ballout Sorted By Ball Table 29.
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Ballout and Package Information Table 29. MCH Ballout Sorted By Ball 310 Table 29. MCH Ballout Sorted By Ball Table 29.
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Ballout and Package Information Table 29. MCH Ballout Sorted By Ball Datasheet Table 29. MCH Ballout Sorted By Ball Table 29.
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Ballout and Package Information Table 29. MCH Ballout Sorted By Ball 312 Table 29.
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Ballout and Package Information 12.2 Package Information The MCH is available in a 40 mm [1.57 in] x 40 mm [1.57 in] Flip Chip Ball Grid Array (FC-BGA) package with an integrated heat spreader (IHS) and 1300 solder balls. Figure 15 shows the package dimensions. Figure 15.
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Ballout and Package Information 314 Datasheet
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Testability 13 Testability In the MCH, testability for Automated Test Equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one input pin connected to it which allows for pad to ball to trace connection testing. The XOR testing methodology is to boot the part using straps to enter XOR mode (A description of the boot process follows). Once in XOR mode, all of the pins of an XOR chain are driven to logic 1.
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Testability The above figure shows the wave forms to be able to boot the part into XOR mode. The straps that need to be controlled during this boot process are BSEL[2:0], RSVD (Ball L18), EXP_SLR, and XORTEST. On the 3200 and 3210 Chipset platforms, all strap values must be driven before PWROK asserts. BSEL0 must be a 1. BSEL[2:1] need to be defined values, but logic value in any order will do. XORTEST must be driven to 0. Not all of the pins will be used in all implementations.
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Testability Table 31. 13.3 XOR Chain Outputs XOR Chain Output Pins Coordinate Location xor_out0 ALLZTEST M21 xor_out1 XORTEST L22 xor_out2 ICH_SYNCB P16 xor_out3 RSVD N18 xor_out4 RSVD AN12 xor_out5 RSVD AM14 xor_out6 BSEL1 F21 xor_out7 BSEL2 F18 xor_out8 RSVD AN13 xor_out9 RSVD AP12 xor_out10 EXP_SLR K19 xor_out11 RSVD L18 xor_out12 BSEL0 M22 xor_out13 RSVD H21 xor_out14 RSVD G22 XOR Chains This section provides the XOR chains.
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Testability 13.4 XOR Chains Table 32.
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Testability Table 33. Table 33. Pin Count Datasheet XOR Chain 1 Ball # Chain 1 L22 XORTEST XOR Chain 1 Pin Count Ball # Chain 1 35 V38 FSB_AB_23 36 AB34 FSB_AB_29 37 V39 FSB_AB_24 1 H39 FSB_REQB_4 38 AA40 FSB_AB_33 2 K42 FSB_AB_15 39 V43 FSB_AB_28 3 G40 FSB_REQB_1 40 AA38 FSB_AB_35 4 K36 FSB_REQB_3 5 F43 FSB_AB_3 6 M36 FSB_AB_5 Table 34.
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Testability Table 35. Table 36.
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Testability Table 37. Table 38.
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Testability Table 38.
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Testability Table 40. Pin Count Ball # Chain 8 35 AW16 DDR_B_DM_2 36 AR12 DDR_B_DQSB_1 37 AT13 DDR_B_DM_1 38 AT10 DDR_B_DQSB_0 39 AY8 DDR_B_DM_0 Table 41.
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Testability Table 42. 324 XOR Chain 10 Table 42.
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Testability Table 44. Table 45.
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Testability Table 45. Pin Count Ball # Chain 13 61 C4 PEG_TXN_8 62 C6 PEG_TXP_8 63 D5 PEG_RXN_8 PEG_RXP_8 64 Table 46. E6 Table 46.