R Intel® Pentium® 4 Processor in 478-pin Package and Intel® 845 Chipset Platform for SDR Design Guide Update March 2004 Notice: The Intel® 845 chipset family may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in the Specification Update.
Preface R Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Preface R Contents Preface ............................................................................................................................................ 5 Nomenclature...................................................................................................................... 5 Codes Used in Summary Table .......................................................................................... 6 General Design Considerations .......................................................
Preface R Revision History Rev. Draft/Changes Date -001 Initial Release March 2002 -002 (1) Added Documentation Change #3, Replace Figure 118, Intel® 845 Chipset Platform Using PC133 SDRAM System Memory Power Delivery Map May 2002 (2) Added Documentation Change #4, Added Section 4.6.7, Electrostatic Discharge Platform Recommendations (3) Added Documentation Change #5, Change Table 3, System Bus Routing Summary for the Processor (4) Added Documentation Change #6, Add Section 13.
Preface R Preface This Design Guide Update document is an update to the specifications and information contained in the Intel® Pentium® 4 Processor in 478-pin Package and Intel® 845 Chipset Platform for SDR Design Guide, January 2002. This Design Guide Update may reference other documents listed in the following Affected Documents/Related Documents table. This document is a compilation of updates to the general design considerations; schematic, layout, and routing updates; and documentation changes.
Preface R Codes Used in Summary Table Doc: Document change or update that will be implemented. Shaded: This item is either new or modified from the previous version of the document. NO. Plans GENERAL DESIGN CONSIDERATIONS There are no General Design Consideration changes in this Design Guide Update revision. 6 NO. Plans SCHEMATIC, LAYOUT, AND ROUTING UPDATES 1 Doc NO. Plans 1 Doc Change Section 12.4.2, 3.3V/V5REF Sequencing 2 Doc Change Section 14.
General Design Considerations R General Design Considerations There are no General Design Considerations in this Design Guide Update revision.
General Design Considerations R This page is intentionally left blank.
Schematic, Layout, and Routing Updates R Schematic, Layout, and Routing Updates 1. Schematic Change to the 82845SDR MCH HSWING Circuit Reference Appendix A, Customer Reference Board Schematics, of the Intel® Pentium® 4 Processor in 478-Pin Package and Intel® 845 Chipset Platform for SDR Design Guide, 298354002, dated January 2002. Sheet 11 of the “Intel® 845 SDR Schematics Rev 1.3” contains a circuit at grid location C-7. This circuit has a VCCP input and an HSWING output.
Schematic, Layout, and Routing Updates R This page is intentionally left blank.
Documentation Changes R Documentation Changes 1. Changed: Change Section 12.4.2, 3.3V/V5REF Sequencing Change the third paragraph to read: As an additional consideration, during suspend, the only signals that are 5 V tolerant capable are USB OC:[3:0]#. If these signals are not needed during suspend, V5REF_SUS can be connected to either VccSus3_3 or 5 V_Always/5V_AUX.
Documentation Changes R ATX 12V Power Supply 3.3V 5V 5VSB 12V VRM Processor Core Processor Vtt VID VREG Processor VID 1.5 V VREG ® Intel 1.8 V VREG ® Intel ® Intel ® Intel 3.3V FET Switch Intel ® MCH Core 1 .5V MCH Vtt MCH AGP MCH Hub Interface 1.8V MCH System Memory SDR 3.3V 3.3V VREG PC-133 System Memory 3.3V Intel Intel Intel 1.8 V VREG ® ® ® Intel Intel ® ® ICH2 Core 1.8V ICH2 I/O 3.3V ICH2 Resume 1.8V ICH2 Resume I/O 3.3V ICH2 RTC 3.
Documentation Changes R Intel recommends that the I/O area on the top and bottom signal layers of a 4-layer motherboard near the I/O back panel be filled with a ground fill as shown in Figures 1-4. In addition, a ground fill cutout should be placed on the Vcc layer in the area where the ground fill is done on the top and bottom layers. Intel recommends filling the I/O area as much as possible without effecting the signal routing. The board designer should fill the entire I/O area along the board edge.
Documentation Changes R Figure 3, Bottom signal layer before the ground fill near the I/O area Ground Fill Figure 4, Bottom signal layer after the ground fill near the I/O area 5. Change Table 3, System Bus Routing Summary for the Processor Reference Table 3, System Bus Routing Summary for the Processor, in Section 4.1. The parameter “Clock keep out zones” is changed as shown: Clock keep out zones Refer to Table 55, BCLK [1:0]# Routing Guidelines, of this Design Guide. 6. Add Section 13.
Documentation Changes R 7. Add Section 15.1.3, Intel® Boxed Processor Mechanical Keep-Outs The following new section is added: 15.1.3 Intel® Boxed Processor Mechanical Keep-Outs Checklist Item Intel® Boxed Processor Mechanical Keep-Outs • Verify Intel’s Boxed Processor mechanical keep-outs are marked and visible during board layout. This keep-out zone should be considered during chassis selection. 8. Revise Section 14.1, Schematic Checklist, Host Interface, PWRGOOD Revise Section 14.
