Intel® Pentium® M Processor Datasheet April 2004 Order Number: 252612-003
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Contents 1 Introduction ...................................................................................................................... 7 1.1 1.2 2 Low Power Features ...................................................................................................... 11 2.1 2.2 2.3 2.4 3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Processor Pin-Out and Pin List ............................................................................ 47 Alphabetical Signals Reference .....................................
Figures 1 2 3 4 5 6 7 8 9 10 11 4 Clock Control States................................................................................................................... 11 Illustration of Active State VCC Static and Ripple Tolerances (Highest Frequency Mode) ........ 28 Illustration of Deep Sleep State Voltage Tolerances (Lowest Frequency Mode) ....................... 30 Micro-FCPGA Package Top and Bottom Isometric Views .........................................................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 References ................................................................................................................................... 9 Voltage Identification Definition .................................................................................................. 19 System Bus Pin Groups..............................................................................................................
Revision History Document Number 252612 252612 252612 6 Revision Description Date 001 Initial release of datasheet March 2003 002 Updates include: • Added specifications for Intel Pentium M Processor 1.7 GHz, Low Voltage Pentium M processor 1.2 GHz, and Ultra Low Voltage Pentium M processor 1 GHz in Table 5 and Table 23 June 2003 003 Updates include: • Added specifications for Intel Pentium M Processor Low Voltage 1.30 GHz, and Intel Pentium M Processor Ultra Low Voltage 1.
Introduction 1 Introduction This document provides electrical, mechanical, and thermal specifications for the Intel® Pentium® M processor. The Intel Pentium M processor is offered at the following core frequencies: • • • • • 1.30 GHz 1.40 GHz 1.50 GHz 1.60 GHz 1.70 GHz The Low Voltage Intel Pentium M processor is offerred at the following core frequencies: • 1.10 GHz • 1.20 GHz • 1.30 GHz The Ultra Low Voltage Intel Pentium M processor is offered at the following core frequencies: • 900 MHz • 1.
Introduction • Micro-op Fusion and Advanced Stack Management that reduce the number of micro-ops handled by the processor. • Advanced branch prediction architecture that significantly reduces the number of mispredicted branches. • Double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3D geometry techniques, such as ray tracing.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Also, please note that “platform design guides,” when used throughout this document, refers to the following documents: Intel® 855PM MHz Chipset Platform Design Guide and Intel® 855GM Chipset Platform Design Guide. Table 1. References Document Order Number ® http://developer.intel.com ® Intel 855PM Chipset Datasheet http://developer.intel.
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Low Power Features 2 Low Power Features 2.1 Clock Control and Low Power States The Intel Pentium M processor supports the AutoHALT, Stop-Grant, Sleep, Deep Sleep, and Deeper Sleep states for optimal power management. See Figure 1 for a visual representation of the processor low-power states. Figure 1.
Low Power Features While in AutoHALT Powerdown state, the processor will process bus snoops. Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VCCP ) for minimum power drawn by the termination resistors in this state.
Low Power Features If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence.
Low Power Features — If the target frequency is higher than the current frequency, Vcc is ramped up by placing a new value on the VID pins and the PLL then locks to the new frequency. — If the target frequency is lower than the current frequency, the PLL locks to the new frequency and the Vcc is changed through the VID pin mechanism. — Software transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until its completion.
Low Power Features 2.4 Processor Power Status Indicator (PSI#) Signal The Intel Pentium M processor incorporates the PSI# signal that is asserted when the processor is in a low power (Deep Sleep or Deeper Sleep) state. This signal is asserted upon Deep Sleep entry and deasserted upon exit. PSI# can be used to improve the light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life.
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Electrical Specifications 3 Electrical Specifications 3.1 System Bus and GTLREF The Intel Pentium M processor system bus signals use Advanced Gunning Transceiver Logic (AGTL+) signalling technology, a variant of GTL+ signalling technology with low power enhancements. This signalling technology provides improved noise margins and reduced ringing through low-voltage swings and controlled edge rates. The termination voltage level for the Intel Pentium M processor AGTL+ signals is VCCP = 1.05 V (nominal).
Electrical Specifications 3.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, must be provided by the voltage regulator solution. For more details on decoupling recommendations, please refer to the platform design guides.
Electrical Specifications Table 2. Voltage Identification Definition VID 5 4 3 VID VC C V 2 1 0 5 4 3 VCC V 2 1 0 0 0 0 0 0 0 1.708 1 0 0 0 0 0 1.196 0 0 0 0 1 0 1.676 1 0 0 0 1 0 1.164 0 0 0 0 1 1 1.660 1 0 0 0 1 1 1.148 0 0 0 1 0 0 1.644 1 0 0 1 0 0 1.132 0 0 0 1 0 1 1.628 1 0 0 1 0 1 1.116 0 0 0 1 1 0 1.612 1 0 0 1 1 0 1.100 0 0 0 1 1 1 1.596 1 0 0 1 1 1 1.084 0 0 1 0 0 0 1.
Electrical Specifications 3.5 Catastrophic Thermal Protection The Intel Pentium M processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures.
Electrical Specifications Table 3.
Electrical Specifications 3.9 Maximum Ratings Table 4 lists the processor’s maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the DC tables. Extended exposure to the maximum ratings may affect device reliability.
Electrical Specifications Table 5. Voltage and Current Specifications Symbol Parameter Min Typ VC C17 Intel Pentium M processor 1.70 GHz Core VC C for Enhanced Intel SpeedStep technology operating points: 1.70 GHz 1.40 GHz 1.20 GHz 1.00 GHz 800 MHz 600 MHz 1.484 1.308 1.228 1.116 1.004 0.956 VC C16 Intel Pentium M processor 1.60 GHz Core VC C for Enhanced Intel SpeedStep technology operating points: 1.60 GHz 1.40 GHz 1.20 GHz 1.00 GHz 800 MHz 600 MHz 1.484 1.420 1.276 1.164 1.036 0.
Electrical Specifications Symbol Low Voltage Intel Pentium M processor 1.30 GHz Core VCC for Enhanced Intel SpeedStep technology operating points: 1.30 GHz 1.20 GHz 1.10 GHz 1.00 GHz 900 MHz 800 MHz 600 MHz Min Typ Max Unit Notes 1.180 1.164 1.100 1.020 1.004 0.988 0.956 V 1,2 VC CLV12 Low Voltage Intel Pentium M processor 1.20 GHz Core VCC for Enhanced Intel SpeedStep technology operating points: 1.20 GHz 1.10 GHz 1.00 GHz 900 MHz 800 MHz 600 MHz 1.180 1.164 1.100 1.020 1.004 0.
Electrical Specifications Symbol VC CULV9 Parameter Min Ultra Low Voltage Intel Pentium M processor 900 MHz Core VCC for Enhanced Intel SpeedStep technology operating points: 900 MHz 800 MHz 600 MHz Typ Max Unit Notes V 1, 2 1.004 0.988 0.844 VC C,BOOT Default VCC Voltage for initial power up 1.14 1.20 1.26 V 2 VC CP AGTL+ Termination Voltage 0.997 1.05 1.102 V 2 VC CA PLL Supply Voltage 1.71 1.8 1.89 V 2 VC CDPRSL P,TR Transient Deeper Sleep voltage 0.695 0.748 0.
Electrical Specifications Symbol Parameter Min Typ Max Unit IDPRSLPU LV ICC Deeper Sleep (ULV Intel Pentium M only) 1.2 A dICC /DT VCC power supply current slew rate 0.5 A/ns ICCA ICC for VC CA supply 120 mA ICCP ICC for VC CP supply 2.5 A Notes 4 6, 7 NOTES: 1. The typical values shown are the VID encoded voltages. Static and Ripple tolerances (for minimum and maximum voltages) are defined in the load line tables i.e. Table 6 through Table 13. 2.
Electrical Specifications Table 6. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.484 V (Active State) ACTIVE Mode Highest Frequency Mode: VID = 1.484 V, Offset = 0% STATIC Ripple ICC , A VCC , V Min Max Min Max Lowest Frequency Mode: VID = 0.956 V, Offset = 0% STATIC Ripple ICC , A VCC , V Min Max Min Max 0 1.484 1.462 1.506 1.452 1.516 0.0 0.956 0.942 0.970 0.932 0.980 0.9 1.481 1.459 1.503 1.449 1.513 0.4 0.955 0.941 0.969 0.931 0.979 1.9 1.478 1.
Electrical Specifications Figure 2. Illustration of Active State VCC Static and Ripple Tolerances (Highest Frequency Mode) Vcc, V Highest-Frequency Mode (VID = 1.484V): Active 1.540 1.520 1.500 1.484 1.480 1.460 1.440 1.420 1.400 1.380 1.
Electrical Specifications Table 7. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.484 V (Deep Sleep State) Deep Sleep Highest Frequency Mode: VID = 1.484 V, Offset = 1.2% Mode STATIC Ripple ICC, A VC C, V Min Max Min Max Lowest Frequency Mode: VID = 0.956 V, Offset = 1.2% STATIC Ripple ICC, A VC C, V Min Max Min Max 0.0 1.466 1.444 1.488 1.434 1.498 0.0 0.945 0.930 0.959 0.920 0.969 0.5 1.465 1.442 1.487 1.432 1.497 0.2 0.944 0.930 0.958 0.920 0.968 1.0 1.
Electrical Specifications Figure 3. Illustration of Deep Sleep State Voltage Tolerances (Lowest Frequency Mode) Vcc, V Lowest-FrequencyMode (VID = 0.956V): Deep Sleep 0.980 0.970 0.960 0.950 0.940 0.945 0.930 0.920 0.910 0.900 0.0 0.5 1.0 1.5 2.0 2.5 3.
Electrical Specifications Table 8. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.388 V (Active State) ACTIVE Mode Highest Frequency Mode: VID = 1.388 V, Offset = 0% STATIC Ripple VCC, A VCC , V Min Max Min Max Lowest Frequency Mode: VID = 0.956 V, Offset = 0% STATIC Ripple IC C, A VCC, V Min Max Min Max 0 1.388 1.367 1.409 1.357 1.419 0.0 0.956 0.942 0.970 0.932 0.980 0.9 1.385 1.364 1.406 1.354 1.416 0.4 0.955 0.941 0.969 0.931 0.979 1.9 1.382 1.362 1.
Electrical Specifications Table 9. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.388 V (Deep Sleep State) Deep Sleep Highest Frequency Mode: VID =1.388 V, Offset = 1.2% Mode STATIC Ripple ICC, A VC C, V Min Max Min Max 32 Lowest Frequency Mode: VID = 0.956 V, Offset = 1.2% STATIC Ripple ICC, A VCC , V Min Max Min Max 0.0 1.371 1.351 1.392 1.341 1.402 0.0 0.945 0.930 0.959 0.920 0.969 0.6 1.370 1.349 1.390 1.339 1.400 0.2 0.944 0.930 0.958 0.920 0.968 1.
Electrical Specifications Table 10. Voltage Tolerances for Low Voltage Intel Pentium M Processors (Active State) ACTIVE Mode Highest Frequency Mode: VID = 1.180 V, Offset = 0% STATIC Ripple VCC, A VCC , V Min Max Min Max Lowest Frequency Mode: VID = 0.956 V, Offset = 0% STATIC Ripple IC C, A VCC, V Min Max Min Max 0 1.180 1.162 1.198 1.152 1.208 0.0 0.956 0.942 0.970 0.932 0.980 0.4 1.179 1.161 1.196 1.151 1.206 0.4 0.955 0.941 0.969 0.931 0.979 0.9 1.177 1.160 1.195 1.150 1.
Electrical Specifications Table 11. Voltage Tolerances for Low Voltage Intel Pentium M Processors (Deep Sleep State) Deep Sleep Highest Frequency Mode: VID = 1.180 V, Offset = 1.2% Mode STATIC Ripple ICC, A VC C, V Min Max Min Max 34 Lowest Frequency Mode: VID = 0.956 V, Offset = 1.2% STATIC Ripple ICC, A VCC , V Min Max Min Max 0.0 1.166 1.148 1.184 1.138 1.194 0.0 0.945 0.930 0.959 0.920 0.969 0.3 1.165 1.147 1.183 1.137 1.193 0.2 0.944 0.930 0.958 0.920 0.968 0.6 1.164 1.
Electrical Specifications Table 12. Voltage Tolerances for Ultra Low Voltage Intel Pentium M Processors (Active State) ACTIVE Mode Highest Frequency Mode: VID = 1.004 V, Offset = 0% STATIC Ripple VCC, A VCC , V Min Max Min Max Lowest Frequency Mode: VID = 0.844 V, Offset = 0% STATIC Ripple IC C, A VCC, V Min Max Min Max 0 1.004 0.989 1.019 0.979 1.029 0.0 0.844 0.831 0.857 0.821 0.867 0.3 1.003 0.988 1.018 0.978 1.028 0.3 0.843 0.831 0.856 0.821 0.866 0.7 1.002 0.987 1.017 0.
Electrical Specifications Table 13. Voltage Tolerances for Ultra Low Voltage Intel Pentium M Processors (Deep Sleep State) Deep Sleep Highest Frequency Mode: VID = 1.004 V, Offset = 1.2% Mode STATIC Ripple ICC, A VC C, V Min Max Min Max 36 Lowest Frequency Mode: VID = 0.844 V, Offset = 1.2% STATIC Ripple ICC, A VCC , V Min Max Min Max 0.0 0.992 0.977 1.007 0.967 1.017 0.0 0.834 0.821 0.847 0.811 0.857 0.2 0.992 0.976 1.007 0.966 1.017 0.1 0.834 0.821 0.846 0.811 0.856 0.3 0.
Electrical Specifications Table 14. System Bus Differential BCLK Specifications Min Typ Max Parameter VL Input Low Voltage VH Input High Voltage 0.660 0.710 0.850 V VC ROSS Crossing Voltage 0.25 0.35 0.55 V 2 ∆VCR OSS Range of Crossing Points N/A N/A 0.140 V 6 VTH Threshold Region VCROSS -0.100 VCR OSS +0.100 V 3 ILI Input Leakage Current ± 100 µA 4 Cpad Pad Capacitance 2.75 pF 5 0 1.8 2.3 Unit Notes1 Symbol V NOTES: 1.
Electrical Specifications . Table 16. CMOS Signal Group DC Specifications Symbol Unit Notes1 Parameter Min Typ Max VCCP I/O Voltage 0.997 1.05 1.102 V VIL Input Low Voltage CMOS -0.1 0.3*VCCP V 2 VIH Input High Voltage 0.7*VCCP VCCP+0.1 V 2 VOL Output Low Voltage -0.1 0 0.1*VCCP V 2 VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2 IOL Output Low Current 1.49 4.08 mA 3 IOH Output High Current 1.49 4.
Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information The Intel Pentium M processor is available in 478-pin, Micro-FCPGA and 479-ball, MicroFCBGA packages. The Low Voltage and Ultra Low Voltage Intel Pentium M processors are available only in the Micro-FCBGA package. Different views of the Micro-FCPGA package are shown in Figure 4 through Figure 6. Package dimensions are shown in Table 18.
Package Mechanical Specifications and Pin Information Figure 5. Micro-FCPGA Package - Top and Side Views S U B S T R A TE K E E P O U T ZO N E D O N O T C ON T A C T P A C K A G E IN S ID E TH IS L IN E 7 (K 1) 8 places 5 (K) 4 plac es 0.286 A 1.25 M A X (A3) D1 35 (D ) Ø 0.3 2 (B) 478 places E1 35 (E) A2 P IN A1 C OR N ER 2.03 ± 0.08 (A 1) NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 18 for details.
Package Mechanical Specifications and Pin Information Figure 6. Micro-FCPGA Package - Bottom View 14 ( K3) AF AD AB Y V T P M K H F D B AE AC AA W U R 1 4 ( K3) N L J G E C A 1 25X 1.27 (e) 3 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 21 20 23 22 25 24 26 25X 1.2 7 (e ) NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 18 for details. Figure 7.
Package Mechanical Specifications and Pin Information Table 18. Micro-FCPGA Package Dimensions Symbol Parameter Min M ax Unit A Overall height, top of die to pack age seating plane 1.88 2.02 mm - Overall height, top of die to PCB surfac e, including socket (Refer to Note 1) 4.74 5.16 mm A1 Pin length 1.95 2.11 mm A2 Die height A3 Pin-s ide capacitor height B 0.82 mm - 1.25 mm Pin diameter 0.28 0.36 mm D Package substrate length 34.9 35.
Package Mechanical Specifications and Pin Information Figure 8.
Package Mechanical Specifications and Pin Information Figure 9. Micro-FCBGA Package Top and Side Views SUBSTRATE KEEPOUT ZONE DO NOT CONTACT PACKAGE INSIDE THIS LINE 7 (K1) 8 places 5 (K) 4 places 0.20 A A2 D1 35 (D) Ø 0.78 (b) 479 places E1 35 (E) K2 PIN A1 CORNER NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 19 for details.
Package Mechanical Specifications and Pin Information Table 19. Micro-FCBGA Package Dimensions Symbol Parameter Min Max Unit A Overall height, as delivered (Refer to Note 1) 2.60 2.85 mm A2 Die height 0.82 mm b Ball diameter 0.78 mm D Package substrate length 34.9 35.1 mm E Package substrate width 34.9 35.1 mm D1 Die length 10.56 mm E1 Die width 7.84 mm F To Package Substrate Center 17.5 mm G Die Offset from Package Center 1.133 mm e Ball pitch 1.
Package Mechanical Specifications and Pin Information Figure 10. Micro-FCBGA Package Bottom View 1.625 (S) 4 places AF AD AB Y V AE AC 1.625 (S) 4 places AA W U T P M K H F D B R N L J G E C A 1 25X 1.27 (e) 3 2 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 25X 1.27 (e) NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 19 for details.
Package Mechanical Specifications and Pin Information 4.1 Processor Pin-Out and Pin List Figure 11 on the next page shows the top view pinout of the Intel Pentium M processor. The pin list arranged in two different formats is shown in Table 19 and Table 20.
Package Mechanical Specifications and Pin Information Figure 11.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Pin Name Table 20.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction Table 20.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type RS[2]# L2 Common Clock RSVD AF7 RSVD Direction Input Table 20.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction Table 20.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction Table 20.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction Table 20.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Pin Number Pin Name Signal Buffer Type Table 21.
Package Mechanical Specifications and Pin Information Table 21. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 21.
Package Mechanical Specifications and Pin Information Table 21. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 21.
Package Mechanical Specifications and Pin Information Table 21. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type C10 VSS Power/Other C11 TMS CMOS C12 TDI CMOS C13 VSS C14 RSVD C15 VSS C16 Direction Table 21.
Package Mechanical Specifications and Pin Information Table 21. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 21.
Package Mechanical Specifications and Pin Information Table 21. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 21.
Package Mechanical Specifications and Pin Information Table 21.
Package Mechanical Specifications and Pin Information 4.2 Alphabetical Signals Reference Table 22. Signal Description (Sheet 1 of 7) Name Type Description 32 Input/ Output A[31:3]# (Address) define a 2 -byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel Pentium M processor system bus.
Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 2 of 7) Name COMP[3:0] Type Description Analog COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Refer to the platform design guides for more implementation details. D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on both agents.
Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 3 of 7) Name Type Description DPSLP# Input DPSLP# when asserted on the platform causes the processor to transition from the Sleep state to the Deep Sleep state. In order to return to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and also connects to the MCH-M component of the Intel 855PM or Intel 855GM chipset.
Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 4 of 7) Name HIT# HITM# IERR# IGNNE# INIT# ITP_CLK[1:0] LINT[1:0] LOCK# Type Input/ Output Input/ Output Description HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.
Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 5 of 7) Name PRDY# PREQ# Description Output Probe Ready signal used by debug tools to determine processor debug readiness. Please refer to the ITP700 Debug Port Design Guide and the platform design guides for more implementation details. Input Probe Request signal used by debug tools to request debug operation of the processor.
Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 6 of 7) Name Type Description Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts.
Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 7 of 7) Name Description TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both system bus agents. TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The Intel Pentium M processor requires a thermal solution to maintain temperatures within operating limits. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die.
Thermal Specifications and Design Considerations Table 23. Power Specifications for the Intel Pentium M Processor Symbol TDP Symbol Core Frequency & Voltage Thermal Design Power Unit Notes 24.5 24.5 24.5 22 22 12 12 12 7 7 7 6 4 W At 100°C, Notes 1, 4 Unit Notes 1.70 GHz & 1.484 V 1.60 GHz & 1.484 V 1.50 GHz & 1.484 V 1.40 GHz & 1.484 V 1.30 GHz & 1.388 V 1.30 GHz & 1.180 V 1.20 GHz & 1.180 V 1.10 GHz & 1.180 V 1.10 GHz & 1.004 V 1.00 GHz & 1.004 V 900 MHz & 1.004V 600 MHz & 0.
Thermal Specifications and Design Considerations 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4.
Thermal Specifications and Design Considerations 1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. Characterized at 100°C. 3. Not 100% tested. Specified by design/characterization. 4.
Thermal Specifications and Design Considerations 2.If the processor load-based Enhanced Intel SpeedStep technology transition target frequency is lower than the Intel Thermal Monitor 2 transition based target frequency, the processor will transition to the processor load-based Enhanced Intel SpeedStep technology target frequency point.
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Debug Tools Specifications 6 Debug Tools Specifications Please refer to the ITP700 Debug Port Design Guide and the platform design guides for information regarding debug tools specifications. 6.1 Logic Analyzer Interface (LAI) Intel is working with logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Intel Pentium M processor systems. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
