Intel® Pentium® M Processor on 90 nm Process with 2-MB L2 Cache and Intel® Processor A100 and A110 on 90 nm process with 512-KB L2 Cache Includes FLI Process consolidation to 65 nm Specification Update May 2012 Revision 028 302209-028
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Contents Preface ................................................................................................................................. 6 Summary Tables of Changes ................................................................................................... 8 Identification Information ...................................................................................................... 14 Errata................................................................................................
Revision History Revision Description Date -001 Initial Release May 2004 -002 Updated Processor Identification Table June 2004 -003 Updated Processor Identification Table Added Erratum X10 July 2004 -004 Added Erratum X11, X12 and X13 October 2004 -005 Added Erratum X14, X15 and X16 November 2004 -006 Added Erratum X17 and X18 December 2004 -007 Updated Processor Identification Table: Added C-0 S-Specs Updated Summary Tables of Changes February 2005 Added Erratum
Revision -018 Description Date Added Errata X36 and X37 April 2006 Updated Erratum X35 Updated Processor Identification Table 1 -019 Added Errata X38-X47 November 2006 Updated Errata X23 and X35 Updated Related Documents Table Update CPU Identification table with new processors -020 Added new processors to the key in the Summary Tables of Changes Added Errata X47-X50 December 2006 Updated CPU Identification table with new processors -021 Added Errata X51, X52 -022 Adde
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Nomenclature Errata are design defects or errors. Errata may cause the Intel® Pentium® M processor on 90 nm process with 2-MB L2 cache behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Each specification update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates: A= C= D= E= F= I= J= K= L= M= N= O= P= Q= R= S= T= U= V= W= X= Y= Z= AA = AB = AC = AD = AE = AF = AG = AH = AI = AJ = AK = AL = AM = AN = AO = Specification Update Dual-Core Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes Dual-Core Intel® Xeon® processor 3000 series Intel® Pentium® dual-core desktop processor E2000 sequence Intel® Celeron® processor 500 series Intel® Xeon® processor 7200, 7300 series Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000 series Intel® Core™ 2 Duo processor E8000 series Quad-Core Intel® Xeon® processor 5400 series Dual-Core Intel® Xeon® processor 5200 series Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Process Quad-
Summary Tables of Changes NO. B1 C0 Plans X13 ERRATA Removed, see Erratum X1.
Summary Tables of Changes 12 NO.
Summary Tables of Changes NO. SPECIFICATION CLARIFICATION X1 Specification Clarification with Respect to Time-stamp Counter – Removed X2 Thermal Diode Offset Specification Clarification Number X1 Number SPECIFICATION CHANGES AGTL+ Buffer On Resistance (Ron) Specification Correction DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision.
Identification Information Identification Information The Intel® Pentium M processor on 90 nm process with 2-MB L2 cache can be identified by the following values: Family1 Model2 Brand ID3 0110 1101 00010110 NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after Reset, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register. 2.
Identification Information QDF/ S-spec Processor Numbers Product Stepping FSB Frequency CPU Signature Core Speed Highest Freq. Mode (HFM) SL7VB 780 C-0 533 06D8h 2.26 GHz SL86M 730 C-0 533 06D8h 1.6 GHz 800 MHz Micro-FCBGA 2,7 SL7S8 740 C-0 533 06D8h 1.73 GHz 800 MHz Micro-FCBGA 2,7 SL7SR 750 C-0 533 06D8h 1.86 GHz 800 MHz Micro-FCBGA 2,7 SLJGC 750 C-0 533 06D8h 1.86 GHz 800 MHz Micro-FCBGA 2,7 SL7SQ 760 C-0 533 06D8h 2.
Product Stepping 745 C-0 Core Speed CPU Signature Processor Numbers SLJ8Q FSB Frequency QDF/ S-spec Identification Information Highest Freq. Mode (HFM) Lowest Freq. Mode (LFM) 06D8h 1.8 GHz Package MicroFCBGA-Pb= µBGA Lead Free QDF Notes 600 MHz Micro-FCPGA 2,12,13, 15 400 SL8TV 738 C-0 400 06D8h 1.4 GHz 600 MHz Micro-FCBGA-Pb 2,3,14 SL89N 738 C-0 400 06D8h 1.4 GHz 600 MHz Micro-FCBGA-Pb 2,3,14 SLJ8U 738 400 06D8h 1.
Identification Information Table 2. Identification Table for Intel® Processors A110 and A110 on 90 nm Process with 512-KB L2 Cache QDF/ S-spec Processor Numbers Product Stepping FSB Frequency CPU Signature Core Speed Highest Freq. Mode (HFM) QSEJ A110 C-0 400 06D8h 800 MHz 600 MHz Micro-FCBGA 1 QUAC A100 C-0 400 06D8h 600 MHz 600 MHz Micro-FCBGA 2 Lowest Freq. Mode (LFM) Package MicroFCBGA-Pb= µBGA Lead Free QDF Notes NOTES: 1. This product is for Ultra Mobile Devices products.
Identification Information Figure 2.
Errata Errata X1. Problem: Code Segment (CS) Is Wrong on SMM Handler When SMBASE Is Not Aligned With SMBASE being relocated to a non-aligned address, during SMM entry the CS can be improperly updated, which can lead to an incorrect SMM handler. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software or system. Workaround: Align SMBASE to 32 KB.
Errata Implication: For RDMSR, undefined values will be read into EDX:EAX. For WRMSR, undefined processor behavior may result. Workaround: Do not use invalid MSR addresses with RDMSR or WRMSR. Status: For the steppings affected, see the Summary of Tables of Changes. X5. Unable to Disable Reads/Writes to Performance Monitoring Related MSRs Problem: The Performance Monitoring Available bit in the miscellaneous processor features MSR (IA32_MISC_ENABLES.
X8. Code Fetch Matching Disabled Debug Register May Cause Debug Exception Problem: The bits L0-3 and G0-3 enable breakpoints local to a task and global to all tasks, respectively. If one of these bits is set, a breakpoint is enabled, corresponding to the addresses in the debug registers DR0-DR3. If at least one of these breakpoints is enabled, any of these registers are disabled (i.e.
Errata Implication: Due to this erratum, any of the following events may occur: 1. A data access break point may be incorrectly reported on the instruction pointer (IP) just before the store instruction. 2. A non-cacheable store can appear twice on the external bus (the first time it will write only 8 bytes, the second time it will write the entire 16 bytes). Intel has not observed this erratum with any commercially available software. This erratum has been seen in a synthetic test environment.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary of Tables of Changes. X15. Under Certain Conditions LTR (Load Task Register) Instruction May Result in System Hang Problem: An LTR instruction may result in a system hang if all the following conditions are met: 1. Invalid data selector of the TR (Task Register) resulting with either #GP (General Protection Fault) or #NP (Segment Not Present Fault). 2. GDT (Global Descriptor Table) is not 8-bytes aligned. 3.
Errata Status: For the steppings affected, see the Summary of Tables of Changes. X18.
Errata Status: For the steppings affected, see the Summary of Tables of Changes. X22. Invalid Entries in Page-Directory-Pointer-Table-Register (PDPTR) May Cause General Protection (#GP) Exception If the Reserved Bits are Set to One Problem: Invalid entries in Page-Directory-Pointer-Table-Register (PDPTR) that have the reserved bits set to one, may cause a General Protection (#GP) exception. Implication: Intel has not observed this erratum with any commercially available software.
Errata X25. Machine Check Exception May Occur When Interleaving Code between Different Memory Types Problem: A small window of opportunity exists where code fetches interleaved between different memory types may cause a machine check exception. A complex set of microarchitectural boundary conditions is required to expose this window. Implication: Interleaved instruction fetches between different memory types may result in a machine check exception.
Errata X28. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store Instruction May Incorrectly Increment Performance Monitoring Count for Saturating SIMD Instructions Executed (Event B1h) Problem: Performance monitoring for Event B1h normally increments on saturating SIMD instruction executed. Regardless of DR7 programming, if the linear address of a memory store MOVD/MOVQ/MOVNTQ instruction executed matches the address in DR3, the B1h counter may be incorrectly incremented.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary of Tables of Changes. X32. CS Limit Violation on RSM May Be Serviced before Higher Priority Interrupts/Exceptions Problem: When the processor encounters a CS (Code Segment) limit violation, a #GP (General Protection Exception) fault is generated after all higher priority Interrupts and exceptions are serviced.
Errata Problem: STPCLK# is asserted to enable the processor to enter a low-power state. Under some circumstances, when STPCLK# becomes active, a pending BTS (Branch Trace Store) message may be either lost and not written or written with corrupted branch address to the Debug Store area. Implication: BTS messages may be lost in the presence of STPCLK# assertions. Workaround: None identified. Status: For the steppings affected, see the Summary of Tables of Changes. X36.
Errata Implication: If SMM turns on paging with global paging enabled and then maps any of linear addresses of SMRAM using global pages, RSM load may load data from the wrong location. Workaround: Do not use global pages in system management mode. Status: For the steppings affected, see the Summary of Tables of Changes. X39.
Errata Status: For the steppings affected, see the Summary of Tables of Changes. X41. #GP Fault is NOT Generated on Writing IA32_MISC_ENABLE [34] When Execute Disable (XD) is Not Supported Problem: #GP fault is not generated on writing to IA32_MISC_ENABLE [34] bit in a processor which does not support Execute Disable (XD) functionality. Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating a fault. Workaround: None identified.
Errata be incorrect. Note: This issue would only occur when one of the 3 above mentioned debug support facilities are used. Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be used. Workaround: None identified. Status: For the steppings affected, see the Summary of Tables of Changes. X45.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary of Tables of Changes. X48. Unaligned Accesses to Paging Structures May Cause the Processor to Hang Problem: When an unaligned access is performed on paging structure entries, accessing a portion of two different entries simultaneously, the processor may live lock. Implication: When this erratum occurs, the processor may live lock causing a system hang.
Errata X51. EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown Problem: When the processor is going into shutdown due to an RSM inconsistency failure, EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be asserted. This may be observed if the processor is taken out of shutdown by NMI#. Implication: A processor that has been taken out of shutdown may have an incorrect EFLAGS, CR0 and CR4. In addition the EXF4 signal may still be asserted.
Errata [r/e]SP, [r/e]BP instruction. This results in a debug exception being signaled on an unexpected instruction boundary since the MOV SS/POP SS and the following instruction should be executed atomically. Implication: This can result in incorrect signaling of a debug exception and possibly a mismatched Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception.
Specification Changes Specification Changes X1. AGTL+ Buffer on Resistance (RON) Specification Correction The AGTL+ Buffer On Resistance (Ron) specification has been corrected for Intel Pentium M processor with 2-MB L2 cache and 533-MHz Front Side Bus. Intel® Pentium® M Processor with 2-MB L2 Cache and 533 MHz Front Side Bus Electrical, Mechanical, and Thermal Specification (EMTS) Revision 2.
Specification Clarifications Specification Clarifications X1. Removed See the Revision History for details. X2. Thermal Diode Offset Spec Clarification The following text has been added to Intel® Pentium® M Processor on 90-nm Process with 2-MB L2 Cache and Intel® Pentium® M Processor on 90-nm Process with 2-MB L2 Cache and 533 MHz Front Side Bus datasheets chapter 5, section 5.1.
Documentation Changes Documentation Changes There are no documentation changes in this Specification Update revision.
