Intel® Pentium® M Processor Specification Update August 2008 Notice: The Intel® Pentium® M processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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Contents Preface ...............................................................................................................................6 Summary Tables of Changes ..................................................................................................8 Identification Information ....................................................................................................14 Errata .......................................................................................................
Revision History Revision Number Description Date 001 Initial Release March 2003 002 • Added Erratum Y15 • Clarified Status description for all Erratum 003 • Updated Pentium M processor Identification Table June 2003 004 • Added Erratum Y16, Y17 July 2003 005 • Added Erratum Y18 September 2003 006 • Added Erratum Y19 - Y21 November 2003 007 • Updated Erratum Y20 April 2003 December 2003 • Added Erratum Y22 008 • Added Erratum Y23 and Y24 April 2004 • Added Specification Cla
020 • Added Erratum Y49 021 • • • • 022 February 2006 Update processors code section Updated Erratum Y7 Updated Erratum Y34 Updated processor name for AF in processor code • Added Erratum Y50 023 March 2006 April 2006 • Updated Errata Y27 • Updated Errata Y43 May 2006 • Added new Errata Y51 • Added SDM Changes link in ‘Documentation Changes’ section 024 • Updated Errata Y12 • Updated Errata Y38 – Workaround updated.
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications. Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in the next release of the specifications. Documentation Changes include typos, errors, or omissions from the current published specifications.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes F= I= J= K= L= M= N= O= P= Q= R= S= T= U= V= W= X= Y= Z= AA = AB = AC = AD = AE = AF = AG = AH = AI = AJ = AK = AL = AM = AN = AO = AP = AQ = AR = AS = AV = AW = Specification Update Intel® Pentium® processor Extreme Edition and Intel® Pentium® processor Dual-Core Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel® Pentium® 4 processor Intel®
Summary Tables of Changes AX = AY = AZ = AAA= AAB= AAC= AAD= AAE= Quad-Core Intel® Xeon® processor 5400 series Dual-Core Intel® Xeon® processor 5200 series Inte® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Process Quad-Core Intel® Xeon® processor 3300 series Dual-Core Intel® Xeon® E3110 Processor Intel® Celeron® dual-core processor E1000 series Intel® Core™2 Extreme Processor QX9775Δ Intel® Atom™ processor Z5xx series Δ Intel processor numbers are not a measure of performance.
Summary Tables of Changes Stepping NO.
Summary Tables of Changes Stepping 12 NO.
Summary Tables of Changes Stepping NO.
Identification Information Identification Information The Pentium M processor can be identified by the following values: Family1 Model2 Brand ID3 0110 1001 00010110 NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after Reset, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register. 2.
Identification Information NOTE: 1. 2. 3. 4. VID[5:0] VID[5:0] VID[5:0] VID[5:0] = = = = 100001; 101111; 101100; 110110; VCC_CORE VCC_CORE VCC_CORE VCC_CORE = = = = 1.180 0.956 1.004 0.844 V V V V for for for for Highest Frequency Mode (HFM). Lowest Frequency Mode (LFM). Highest Frequency Mode (HFM). Lowest Frequency Mode (LFM). Component Marking Information Figure 1.
Errata Errata Y1. Performance Monitoring Event That Counts Intel® Thermal Monitor 2 Transitions (59h) Is Not Accurate. Problem: The performance monitoring event that counts Intel Thermal Monitor 2 (Enhanced Intel SpeedStep® technology based) transitions may have inaccurate results. Implication: There is no functional impact of this erratum. However this Performance Monitoring Event should not be used when accurate performance monitoring is required. Workaround: None.
Errata Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system. Workaround: Avoid code that wraps around segment limit. Status: For the steppings affected, see the Summary of Tables of Changes. Y5.
Errata technology MOV instruction) and the load has an longer than typical latency the processor can enter a livelock. Implication: When this erratum occurs, the processor will enter a livelock condition. Intel has not observed this erratum with any commercially available software or system. Workaround: None. Status: For the steppings affected, see the Summary of Tables of Changes. Y9.
Errata Y12. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints until after execution of the following instruction. This is intended to allow the sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an invalid stack during interrupt handling.
Y15. RDMSR or WRMSR to Invalid MSR Address May Not Cause GP Fault Problem: The RDMSR and WRMSR instructions allow reading or writing of MSRs (Model Specific Registers) based on the index number placed in ECX. The processor should reject access to any reserved or unimplemented MSRs by generating #GP(0). However, there are some invalid MSR addressers for which the processor will not generate #GP(0). This erratum has not been observed with commercially available software.
Errata Implication: MOV to Control Register Instruction is not expected to generate a breakpoint report. Workaround: Ignore breakpoint data from MOV to CR instruction. Status: For the steppings affected, see the Summary of Tables of Changes. Y19.
Errata multiple speculative branches and memory accesses, there exists a one cycle long window in which the processor may signal a MCE in the Instruction Fetch Unit (IFU) because instructions previously decoded have been evicted from the IFU. The one cycle long window is opened when an opportunistic fetch receives a partial hit on a previously executed but not as yet completed store resident in the store buffer.
Errata Implication: When the OS recovers from the double fault handler, the processor will no longer be in VM86 mode. Workaround: None. Status: For the steppings affected, see the Summary of Tables of Changes. Y25. Code Fetch Matching Disabled Debug Register May Cause Debug Exception Problem: The bits L0-3 and G0-3 enable breakpoints local to a task and global to all tasks, respectively.
Errata Problem: An SSE or SSE2 streaming store that results in a Self-Modifying Code (SMC) event may cause unexpected behavior. The SMC event occurs on a full address match of code contained in L1 cache. Implication: Due to this erratum, any of the following events may occur: 1. A data access break point may be incorrectly reported on the instruction pointer (IP) just before the store instruction. 2.
Errata Implication: This erratum may result in system hang if all conditions have been met. This erratum has not been observed in commercial operating systems or software. For performance reasons, GDT is typically aligned to 8-bytes. Workaround: Do not use memory type USWC for memory that has read side-effects. Status: For the steppings affected, see the Summary of Tables of Changes. Y33.
Errata Workaround: User mode code should not count on being able to recover from illegal accesses to memory regions protected with supervisor only access when using FP instructions. Status: For the steppings affected, see the Summary of Tables of Changes. Y36.
Y39. Use of Memory Aliasing with Inconsistent Memory Type May Cause System Hang or a Machine Check Exception Problem: Software that implements memory aliasing by having more than one linear addresses mapped to the same physical page with different cache types may cause the system to hang or to report a machine check exception (MCE). This would occur if one of the addresses is non-cacheable and used in a code segment and the other is a cacheable address.
Errata Implication: A processor livelock may occur causing a system hang. This issue has only been observed in synthetic lab testing conditions and has not been seen in any commercially available applications. The erratum does not occur with Intel mobile chipset-based platforms. Workaround: Use the PIC instead of the APIC for the interrupt controller. Status: For the steppings affected, see the Summary of Tables of Changes. Y42.
Errata Y45. Certain Performance Monitoring Counters Related to Bus, L2 Cache and Power Management are Inaccurate Problem: All Performance Monitoring Counters in the ranges 21H-3DH and 60H-7FH may have inaccurate results up to ±7.’ Implication: There may be a small error in the affected counts. Workaround: None identified. Status: For the steppings affected, see the Summary of Tables of Changes. Y46.
Y48. The Processor May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary of Tables of Changes. Y49.
Errata Y51. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur it is possible that the load portion of the instruction will have executed before the exception handler is entered.
Errata Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be used. Workaround: None identified. Status: For the steppings affected, see the Summary of Tables of Changes. Y54. FP Inexact-Result Exception Flag May Not Be Set Problem: Problem: When the result of a floating-point operation is not exactly representable in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception occurs.
Errata Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to execute a MOV on debug registers in V86 mode, a debug exception will be generated instead of the expected general-protection fault. Workaround: In general, operating systems do not set the GD bit when they are in V86 mode. The GD bit is generally set and used by debuggers. The debug exception handler should check that the exception did not occur in V86 mode before continuing.
Errata Status: For the steppings affected, see the Summary of Tables of Changes. Y58. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum, if execution of the ENTER instruction results in a fault, the dynamic storage area of the resultant stack frame may contain unexpected values (i.e. residual stack data as a result of processing the fault).
Errata Y61. Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault Problem: If code segment limit is set close to the end of a code page, then due to this erratum the memory page Access bit (A bit) may be set for the subsequent page prior to general protection fault on code segment limit. Implication: When this erratum occurs, a non-accessed page which is present in memory and follows a page that contains the code segment limit may be tagged as accessed.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary of Tables of Changes. Y65.
Specification Changes Specification Changes There are no Specification Changes in this Specification Update revision.
Specification Clarifications Specification Clarifications There are no specification clarifications in this Specification Update revision.
Documentation Changes Documentation Changes Note: Documentation changes for Intel® 64 and IA-32 Architectures Software Developer Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document named Intel® 64 and IA-32 Architecture Software Developer's Manual Documentation Changes. Follow the link below to become familiar with this file. http://developer.intel.com/design/pentium4/specupdt/252046.
