Datasheet

126 Datasheet
Intel
®
Celeron
®
Processor up to 1.10 GHz
7.1 Signal Summaries
Table 60 through Table 63 list attributes of the Celeron processor output, input, and I/O signals.
VCORE
DET
(PGA packages
only)
O
The V
CORE
DET
signal will float for 2.0 V core processors and will be grounded for the
Celeron
®
FC-PGA/FC-PGA2 processor with a 1.5V core voltage.
VID[4:0]
(S.E.P.P.)
VID[3:0]
(PGA packages
only)
O
The VID (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to V
SS on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on Intel Celeron processors. See Table 2 for
definitions of these pins. The power supply must supply the voltage that is requested
by these pins, or disable itself.
V
REF[7:0]
(PGA packages
only)
I
These input signals are used by the AGTL+ inputs as a reference voltage. AGTL+
inputs are differential receivers and will use this voltage to determine whether the
signal is a logic high or logic low.
For the FC-PGA/FC-PGA2 packages, V
REF is typically 2/3 of VTT
Table 59. Alphabetical Signal Reference (Sheet 7 of 7)
Signal Type Description
Table 60. Output Signals
Name Active Level Clock Signal Group
CPUPRES# (PGA
packages only)
Low Asynch Power/Other
FERR# Low Asynch CMOS Output
IERR# Low Asynch CMOS Output
PRDY# Low BCLK AGTL+ Output
SLOTOCC#
(S.E.P.P. only)
Low Asynch Power/Other
TDO High TCK TAP Output
THERMDN N/A Asynch Power/Other
THERMTRIP# Low Asynch CMOS Output
V
CORE
DET
(PGA packages only)
High Asynch Power/Other
VID[4:0] (S.E.P.P.)
VID[3:0] (PGA
packages)
High Asynch Power/Other