Datasheet

42 Datasheet
Intel
®
Celeron
®
Processor up to 1.10 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after V
CC
CORE
, VTT, VCC
CMOS
, and BCLK become stable.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
®
Celeron
®
processor frequencies.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Celeron FC-PGA/FC-PGA2 processors at all
frequencies and cache sizes.
2. For a reset, the clock ratio defined by these signals must be a safe value (their final or a lower-multiplier)
within this delay unless PWRGOOD is being driven inactive.
3. These parameters apply to processor engineering samples only. For production units, the processor core
frequency will be determined through the processor internal logic.
Table 19. System Bus AC Specifications (CMOS Signal Group)
1, 2, 3, 4
T# Parameter Min Max Unit Figure Notes
T14: CMOS Input Pulse Width, except
PWRGOOD
2BCLKs4
Active and
Inactive states
T15: PWRGOOD Inactive Pulse Width 10 BCLKs 4, 8 5
Table 20. System Bus AC Specifications (Reset Conditions)
(for Both S.E.P. and PPGA Packages)
T# Parameter Min Max Unit Figure Notes
T16: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Setup Time
4BCLKs6
Before deassertion
of RESET#
T17: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Hold Time
220BCLKs6
After clock that
deasserts RESET#
Table 21. System Bus AC Specifications (Reset Conditions) (for the FC-PGA/FC-PGA2
Packages)
T# Parameter Min Max Unit Figure Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#)
Setup Time
4BCLKs7
Before deassertion of
RESET#
T17: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Hold
Time
220BCLKs7
After clock that
deasserts RESET#
T18: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Setup Time
1ms7
Before deassertion of
RESET#, 3
T19: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Delay Time
5BCLKs7
After assertion of
RESET#, 2, 3
T20: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Hold Time
220BCLKs7
After clock that
deasserts RESET#, 3