Datasheet

Datasheet 7
Intel
®
Celeron
®
Processor up to 1.10 GHz
Tables
1 Processor Identification .......................................................................................13
2 Voltage Identification Definition ...........................................................................20
3Intel
®
Celeron
®
Processor System Bus Signal Groups.......................................22
4 Absolute Maximum Ratings................................................................................24
5 Voltage and Current Specifications .....................................................................25
6 AGTL+ Signal Groups DC Specifications............................................................31
7 Non-AGTL+ Signal Group DC Specifications......................................................32
8 Processor AGTL+ Bus Specifications .................................................................33
9 System Bus AC Specifications (Clock) at the Processor Edge Fingers
(for S.E.P. Package)............................................................................................35
10 System Bus AC Specifications (Clock) at the Processor
Core Pins (for Both S.E.P. and PGA Packages).................................................36
11 System Bus AC Specifications (SET Clock)........................................................37
12 Valid Intel
®
Celeron
®
Processor System Bus, Core Frequency..........................38
13 System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Edge Fingers (for S.E.P. Package) .....................................................................39
14 System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Core Pins (for S.E.P. Package)...........................................................................39
15 Processor System Bus AC Specifications (AGTL+ Signal Group) at the
Processor Core Pins (for PPGA Package)..........................................................40
16 System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Core Pins (for FC-PGA/FC-PGA2 Packages).....................................................40
17 System Bus AC Specifications (CMOS Signal Group) at the Processor
Edge Fingers (for S.E.P. Package) .....................................................................41
18 System Bus AC Specifications (CMOS Signal Group) at the Processor
Core Pins (for Both S.E.P., PGA, and FC-PGA/FC-PGA2 Packages)................41
19 System Bus AC Specifications (CMOS Signal Group) .......................................42
20 System Bus AC Specifications (Reset Conditions)
(for Both S.E.P. and PPGA Packages) ...............................................................42
21 System Bus AC Specifications (Reset Conditions) (for the
FC-PGA/FC-PGA2 Packages) ............................................................................42
22 System Bus AC Specifications (APIC Clock and APIC I/O) at the
Processor Edge Fingers (for S.E.P. Package) ....................................................43
23 System Bus AC Specifications (APIC Clock and APIC I/O) at the
Processor Core Pins (For S.E.P. and PGA Packages).......................................44
24 System Bus AC Specifications (APIC Clock and APIC I/O) ................................45
25 System Bus AC Specifications (TAP Connection) at the Processor
Edge Fingers (For S.E.P. Package) ....................................................................45
26 System Bus AC Specifications (TAP Connection) at the Processor
Core Pins (for Both S.E.P. and PPGA Packages)...............................................46
27 System Bus AC Specifications (TAP Connection) ..............................................47
28 BCLK Signal Quality Specifications for Simulation at the Processor Core
(for Both S.E.P. and PPGA Packages) ...............................................................52
29 BCLK/PICCLK Signal Quality Specifications for Simulation at the
Processor Pins (for the FC-PGA/FC-PGA2 Packages).......................................53
30 BCLK Signal Quality Guidelines for Edge Finger Measurement
(for the S.E.P. Package)......................................................................................54
31 AGTL+ Signal Groups Ringback Tolerance Specifications at the
Processor Core (For Both the S.E.P. and PPGA Packages) ..............................55