Datasheet

Datasheet 93

Intel

Celeron

Processor up to 1.10 GHz

NOTES:

1. Capacitors and resistors may be placed on the pin-side of the FC-PGA package in the area defined by G1,

G2, and G3. This area is a keepout zone for motherboard designers.

The bare processor die has mechanical load limits that should not be exceeded during heatsink

assembly, mechanical stress testing, or standard drop and shipping conditions. The heatsink attach

solution must not induce permanent stress into the processor substrate with the exception of a

uniform load to maintain the heatsink to the processor thermal interface. The package dynamic and

static loading parameters are listed in Table 52.

For Table 52, the following apply:

1. It is not recommended to use any portion of the processor substrate as a mechanical reference

or load bearing surface for thermal solutions.

2. Parameters assume uniformly applied loads

NOTES:

1. This specification applies to a uniform and a non-uniform load.

2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and

processor interface.

Table 51. Package Dimensions (FC-PGA Package)

Millimeters Inches

Symbol Min Max Notes Min Max Notes

A1 0.787 0.889 0.031 0.035

A2 1.000 1.200 0.039 0.047

B1 11.183 11.285 0.440 0.445

B2 9.225 9.327 0.363 0.368

C1 23.495 max 0.925 max

C2 21.590 max 0.850 max

D 49.428 49.632 1.946 1.954

D1 45.466 45.947 1.790 1.810

G1 0.000 17.780 1 0.000 0.700

G2 0.000 17.780 1 0.000 0.700

G3 0.000 0.889 1 0.000 0.035

H 2.540 Nominal 0.100 Nominal

L 3.048 3.302 0.120 0.130

ϕP 0.431 0.483 0.017 0.019

Pin TP 0.508 Diametric True Position (Pin-to-Pin) 0.020 Diametric True Position (Pin-to-Pin)

Table 52. Processor Die Loading Parameters (FC-PGA Package)

Parameter Dynamic (max)

Static (max)

Unit

Silicon Die Surface 200 50 lbf

Silicon Die Edge 100 12 lbf