82555 10/100 Mbps LAN Physical Layer Interface Networking Silicon Datasheet Product Features ■ Optimal integration for lower cost solutions — Integrated 10/100 Mbps single chip physical layer interface solution — Complete 10/100 Mbps MII compliance with MDI support — Full duplex operation in 10 Mbps and 100 Mbps modes — IEEE 802.
82555 — Networking Silicon ■ Low power consumption — Typical total solution power including all resistors and magnetics: - 275 mA 100BASE-TX - 230 mA 10BASE-T - 250 mA Auto-Negotiation — 300 mA maximum total solution power in DTE (adapter) mode — Power-down of 10BASE-T/100BASETX sections when not in use ■ Added modes for design, testing, and manufacturability — Test Access Port (TAP) - NAND Tree - Board Level Functional Test (BIST) — Programmable bypass for 4B/5B encoding/decoding and scrambler/ descram
Networking Silicon — 82555 Contents 1.0 INTRODUCTION.......................................................................................................................... 1 1.1 1.2 2.0 ARCHITECTURAL OVERVIEW................................................................................................... 3 2.1 2.2 2.3 3.0 Pin Types ....................................................................................................................... 8 Clock Pins ..................................
82555 — Networking Silicon Contents 5.4 5.5 5.6 5.7 6.0 REPEATER MODE .................................................................................................................... 25 6.1 6.2 7.0 Special Repeater Features............................................................................................ 25 Connectivity................................................................................................................... 25 MANAGEMENT DATA INTERFACE............................
Networking Silicon — 82555 1.0 Introduction The 82555 is a highly integrated, physical layer interface solution designed for 10 and 100 Mbps Ethernet systems based on the IEEE 10BASE-T and 100BASE-TX specifications. 100BASE-TX is an IEEE 802.3 physical layer specification for use over two pairs of Category 5 unshielded twisted pair or Type 1 shielded twisted pair cable. 100BASE-TX defines a signaling scheme not only for 100 Mbps, but also provides CSMA/CD compatibility with the 10 Mbps IEEE 802.
82555 — Networking Silicon The 82555 also complies with the IEEE 802.3u Auto-Negotiation and the IEEE 802.3x Full Duplex Flow Control sections. The MAC interface on the 82555 is a superset of the IEEE 802.3u Media Independent Interface (MII) standard.
Networking Silicon — 82555 2.0 Architectural Overview The 82555 is an advanced combination of both digital and analog logic which combine to provide a functional stack between the Media Independent Interface (MII) and the wire through the magnetics. Figure 2 shows a general block diagram of the 82555 component. Figure 2. 82555 Simplified Block Diagram 2.
2555 — Networking Silicon • Receive: The 82555 takes receive analog MLT-3 data from the receive differential pair and converts it into a digital 125 Mbps stream, recovering both clock and data signals. MII TX Interface MII RX Interface 4b/5b Encoding 4b/5b Decoding Scrambler De-scrambler Serialization Serial to 5B NRZ to NRZI NRZI to NRZ NRZI to MLT3 MLT3 to NRZI Magnetics Module 1 2 3 4 5 6 7 8 RJ-45 Connector Figure 3. 82555 Analog Logic 2.
Networking Silicon — 82555 The 82555 provides a glueless interface to Intel components such as the 82557 Fast Ethernet Controller, as well as any MII compatible device. Figure 4 shows a schematic-level diagram of the 82557 Fast Ethernet controller implementation connected to the 82555 using the MII interface. Flash (optional) EEPR O M (optional) RXD[3:0] RXC RXERR RXDV CRS COL 82557 82555 TXD[3:0] TXC TXEN MDC MDIO RESET PCI Bus Signals Figure 4. Intel 82557/82555 Solution 2.
82555 — Networking Silicon Table 1.
Networking Silicon — 82555 3.0 Pin Definitions All active digital pins are defined to have transistor-to-transistor logic voltage levels except the X1 and X2 crystal signals. The transmit differential and receive differential pins are specified as analog outputs and inputs, respectively. The figure below show the pin locations on the 82555 component. The following subsections describe the pin functions. Figure 5.
82555 — Networking Silicon Pin allocation is based on a 100-lead quad flat package. All pin locations are based on printed circuit board layout and other design constraints. 3.1 Pin Types Pin Type 3.2 I This type of pin is an input pin to the 82555. O This type of pin is an output pin from the 82555. I/O This type of pin is both an input and output pin for the 82555. B This pin is used as a bias pin. The bias pin is either pulled up or down with a resistor.
Networking Silicon — 82555 Symbol 3.5 Type Name and Function RXC 90 O Receive Clock. The Receive Clock may be either 25 MHz or 2.5 MHz depending on the 82555’s operating speed (25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps). The Receive Clock is recovered directly from incoming data and is continuous into the Media Access Controller (MAC). Thus, it must be resynchronized in 10 Mbps mode at the start of each incoming packet. RXDV 86 O Receive Data Valid.
82555 — Networking Silicon Symbol TXRDY Pin 4 Type O (TOUT) Name and Function This pin is multiplexed and can be used for one of the following: Transmit Ready. If full duplex and PHY Base (Bay Technologies) flow control modes are enabled, the TXRDY signal enables transmission while it is asserted. TOUT. When the Test Enable signal is activated, this signal functions as the Test Output port. FDX_N 5 I/O Full Duplex.
Networking Silicon — 82555 3.8 Miscellaneous Control Pins Symbol Pin Type Name and Function RESET 1 I Reset. The Reset signal is active high and resets the 82555. A reset pulse width of at least 1 µs should be used. FRC100 51 I This pin is multiplexed and can be used for one of the following: (MACTYP) Force 100/10 Mbps. In repeater mode, this pin configures the repeater to either 100 Mbps (active high) or to 10 Mbps (active low). MAC Type.
82555 — Networking Silicon 3.
Networking Silicon — 82555 4.0 100BASE-TX Adapter Mode Operation 4.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal or a 25 MHz oscillator is used to drive the 82555’s X1 and X2 pins. The 82555 derives its internal transmit digital clocks from this crystal or oscillator input. The Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external crystal or oscillator must be ± 0.0005% (50 PPM). 4.
82555 — Networking Silicon Table 2. 4B/5B Encoder Symbol 4.2.
Networking Silicon — 82555 maintained (either positive, negative or zero). When an NRZ “1” arrives at the input of the encoder, the output steps to the next level. The order of steps is negative-zero-positive-zero which continues periodically. The figure below illustrates this process. Clock 1 NRZ 1 0 0 1 0 0 1 NRZ1 1 1 0 0 1 0 0 1 MLT-3 1 1 0 0 1 0 0 1 Figure 6. NRZ to MLT-3 Encoding Diagram 4.2.
82555 — Networking Silicon 4.2.4 Transmit Driver The transmit differential lines are implemented with a digital slope controlled current driver that meets the TP-PMD specifications. Current is sunk from the isolation transformer by the transmit differential pins. The conceptual transmit differential waveform for 100 Mbps is illustrated in the following figure. (V TDP -V TDN ) +1V t 0V -1V I TDP 40mA 20mA t 0 I TDN 40mA 20mA t 0 Figure 7.
Networking Silicon — 82555 4.3.1 Adaptive Equalizer The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer performs adaptation based on the shape of the received signal, equalizing the signal to meet superior Data Dependent Jitter performance. 4.3.2 Receive Clock and Data Recovery The clock recovery circuit uses advanced digital signal processing technology to compensate for various signal jitter causes.
82555 — Networking Silicon 4.5 100BASE-TX Link Integrity and Auto-Negotiation Solution The 82555’s Auto-Negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. Auto-Negotiation is widely described in IEEE specification 802.3u, Clause 28. The 82555 supports 10BASE-T half duplex, 10BASE-T full duplex, 100BASE-TX half duplex, and 100BASE-TX full duplex.
Networking Silicon — 82555 The figure below illustrates an 82557/82555/PHY-T4 solution in a block diagram. T4 adv 82555 Common Magnetics slave_tri MII 82557 listat_n fdx_n PCI BUS PHY-T4 3669 Figure 8. Combination Card Example 4.6 Auto 10/100 Mbps Speed Selection The MAC may either allow the 82555 to automatically select its operating speed or force the 82555 into 10 Mbps or 100 Mbps mode. The Management Data Interface (MDI) can control the 82555 speed mode.
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Networking Silicon — 82555 5.0 10BASE-T Functionality in Adapter Mode 5.1 10BASE-T Transmit Clock Generation The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz crystal or oscillator. The 82555 provides the transmit clock and receive clock to the MAC at 2.5 MHz. 5.2 10BASE-T Transmit Blocks 5.2.1 10BASE-T Manchester Encoder After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs the Manchester encoding.
82555 — Networking Silicon Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the requirements of the 10BASE-T standard. The following line activity is determined to be inactive and is rejected: • Differential pulses of peak magnitude less than 300 mV. • Continuous sinusoids with a differential amplitude less than 6.2 Vpp and frequency less than 2 MHz.
Networking Silicon — 82555 5.7 10BASE-T Full Duplex The 82555 supports 10 Mbps full duplex by disabling the collision function, the squelch test, and the carrier sense transmit function. This allows the 82555 to transmit and receive simultaneously, achieving up to 20 Mbps of network bandwidth. The configuration can be achieved through AutoNegotiation. Full duplex should only be used in point-to-point connections (no shared media). Flow control is always disabled.
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Networking Silicon — 82555 6.0 Repeater Mode The 82555 has a compete set of repeater features making it the ideal PHY for Class 1 (MII) repeater designs. The 82555 works in repeater mode when the RPT signal (pin 50) is high. The FRC100 signal (pin 51) determines which type of repeater is supported, either 100BASE-TX or 10BASE-T. 6.1 Special Repeater Features Special features of the 82555 repeater mode operation include: • Fully IEEE compliant with automatic carrier disconnect.
82555 — Networking Silicon PHYs connected to the RIC. Signals TXEN, CRS, and PORTEN are connected from each of the 82555 devices to the specified RIC pin. The figure below illustrates an example of multiple 82555s connected to a 25 MHz (or 2.5 MHz) oscillator. RIC CLK 2.5/25 MHz (10/100) 2.5/25 MHz (10/100) TXCLK TXCLK PHY1 PHY2 X1 X1 TXCLK PHY3 X1 PC-3691 Figure 9.
Networking Silicon — 82555 7.0 Management Data Interface The 82555 provides status and accepts management information through the Management Data Interface (MDI). This is accomplished through read and write operations to various registers in accordance with the IEEE 802.3u MII specification. 7.1 MDI Frame Structure Data read from or written to a particular register is called a management frame and is sent serially over the MDIO pin synchronously to the MDC signal.
82555 — Networking Silicon The 82555 address can be configured to four 0 through 3 in DTE (adapter) mode and 0 through 31 in repeater mode. A special functions for switches allows 32 addresses to exist in repeater mode. The management frame structure is as follows: Transition 7.
Networking Silicon — 82555 Bit(s) 11 Name Power-Down Description Default R/W 0 RW 0 RW This bit sets the 82555 into a low power mode. 1 = Power-down enabled 0 = Power-down disabled (normal operation) 10 Isolate This bit allows the 82555 to electrically isolate the Media Independent Interface. When the MII is isolated, the 82555 does not respond to TXD[3:0], TXEN, and TXERR input signals. Also, the 82555 presents high impedance on its TXC, RXC, RXDV, RXERR, RXD[3:0], COL, and CRS output signals.
82555 — Networking Silicon Bit(s) 6 5 4 Name Description Management Frames Preamble Suppression 1 = 82555 will accept management frames with preamble suppressed Auto-Negotiation Complete 1 = Auto-Negotiation process completed Remote Fault Default -- RO 0 RO 0 RO 0 = 82555 will not accept management frames with preamble suppressed 0 = Auto-Negotiation process has not completed 1 = Remote fault condition detected 0 = No remote fault condition detected 3 2 R/W Auto-Negotiation Ability 1 =
Networking Silicon — 82555 7.2.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions Bit(s) 7.2.1.7 Name Description Default R/W 15 Next Page This bit reflects the 82555’s link partner’s AutoNegotiation ability. -- RO 14 Acknowledge This bit is used to indicate that the 82555 has successfully received its link partner’s AutoNegotiation advertising ability. -- RO 13 Remote Fault This bit reflects the 82555’s link partner’s AutoNegotiation ability.
82555 — Networking Silicon 7.2.3.1 Register 16: 82555 Status and Control Register Bit Definitions Bit(s) 15 Name Flow Control Description This bit enables PHY Base (Bay Technologies) flow control. Default R/W 0 RW 0 RW RW 1 = Enable PHY Base flow control 0 = Disable PHY Base flow control 14 Reserved These bits are reserved and should be set to 0b 13 Carrier Sense Disconnect Control This bit enables the disconnect function.
Networking Silicon — 82555 Bit(s) 13 12 11 Name Description Force Transmit HPattern 1 = Force transmit H-pattern Force 34 Transmit Pattern 1 = Force 34 transmit pattern Good Link 1 = 100BASE-TX link good Default R/W 0 RW 0 RW 0 RW 0 = Normal operation 0 = Normal operation 0 = Normal operation 10 Reserved This bit is reserved and should be set to 0b.
82555 — Networking Silicon 7.2.3.5 Register 22: Receive Symbol Error Counter Bit Definitions Bit(s) 15:0 Name Symbol Error Counter Description Default This field contains a 16-bit counter that increments for each symbol error. The counter stops when full (and does not roll over) and self-clears on read. -- R/W RO SC In a frame with a bad symbol, each sequential six bad symbols count as one. 7.2.3.
Networking Silicon — 82555 8.0 Auto-Negotiation Functionality The 82555 supports Auto-Negotiation. Auto-Negotiation is a scheme of auto-configuration designed to manage interoperability in multifunctional LAN environments. It allows two stations with “N” different modes of communication to establish a common mode of operation. At powerup, Auto-Negotiation automatically establishes a link that takes advantage of an Auto-Negotiation capable device.
82555 — Networking Silicon Table 5. Technology Priority Priority Technology 4 10BASE-T Full Duplex 5 10BASE-T Half Duplex To detect the correct technology, the two register fields should be ANDed together to obtain the highest common denominator. This value should then be used to map into a priority resolution table used by the MAC driver to use the appropriate technology. The following is an outline of the Auto-Negotiation process: 1. Receive 3 consecutive, matching code words 2.
Networking Silicon — 82555 Negotiation or Parallel Detection with no data packets being transmitted. Connection is then established either by FLP exchange or Parallel Detection. The 82555 will look for both FLPs and link integrity pulses. The following diagram illustrates this process. Force_Fail Ability detect either by parallel detect or autonegotiation.
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Networking Silicon — 82555 9.0 LED Descriptions The 82555 supports four LED pins to indicate link status, network activity and network speed. • Link: This LED is off (logic high) until a valid link has been detected. After a valid link has been detected, the LED will remain on (active-low). • Activity: This LED is on (active-low) when activity is detected on the wire. In DTE (adapter) mode, this LED is on during transmit and receive when the 82555 is not in loopback mode.
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Networking Silicon — 82555 10.0 Reset and Miscellaneous Test Modes 10.1 Reset When the 82555 RESET signal is asserted (high), all internal circuits are reset. TXC and RXC should run continuously even though RESET is active. The 82555 may also be reset through the MDI reset bit. 10.2 Loopback When the loopback pin is being driven high, the 82555 executes a loopback diagnostics operation. This mode can also be accessed through the MDI registers. 10.
82555 — Networking Silicon The TOUT pin is controlled by different sources according to the active test instruction. The TOUT signal is activated by the falling edge of TCK. The TAP must be reset during power-up. Otherwise, the 82555 can wake-up during high-Z mode or NAND Test, which can be harmful to the board. The TAP should be reset only with a hardware reset input pin and not with software reset. The TOUT control logic selects the TISR output in all tests, except burn-in test modes. Table 6.
Networking Silicon — 82555 11.0 Electrical Specifications and Timing Parameters 11.1 Absolute Maximum Ratings Symbol Parameter Description Min Typ Max Units 0 85 C TC Case temperature under bias TS Storage temperature -65 140 C VSUP Supply voltage -0.5 7.0 V All output voltages -0.5 7.0 V VOTD Transmit Data Output Voltage -0.5 8.0 V VIA All input voltages -1.0 6.0 V VOA a a.
82555 — Networking Silicon Symbol Parameter Description Condition VIDA10 Input differential accept voltage 5 MHz ≤ f ≤ 10 MHz VIDR10 Input differential reject voltage 5 MHz ≤ f ≤ 10 MHz VICM10 Input common mode voltage VOD10 Output differential voltage ICCT10c Line driver supply d Min Typ ±585 Units ±3100 mVP ±300 mVP VCC/2 RL = 100 Ωb ±2.2 RBIAS10 = 768 Ω RBIAS10 = 768 Ω V ±2.
Networking Silicon — 82555 Symbol ICC100 Parameter Description c ICCT100TOT Condition Min Typ Max Units Current on all VCC pins 235 mA Total supply current 275 mA a. Transmitter current is measured with a 1:1 transformer on the center tap. b. Transmitter current is measured with a 1:1 transformer on the center tap. c. Current is measured on all VCC pins at VCC = 5.25 V. Rbias100 667Ω 6 3 4Ω 6 0 4Ω 38mA 42mA 40mA Icct100 Figure 12. RBIAS100 Resistance versus ICCT100 11.
82555 — Networking Silicon 1.5V T4,T5,T6 T4,T5,T6 T1,T2,T3 Figure 14. MII Clocks AC Timing 11.4.
Networking Silicon — 82555 RXCLK T9 RXD[3:0], RXER,RXDV Data Invalid T10 Data Valid Data Invalid Figure 16. MII Receive Timing Parameters MDC T11 MDIO (Input) Data Invalid T12 Data Valid Data Invalid Data Valid Data Invalid T13 MDIO (Output) Data Invalid Figure 17. MII Timing Parameters: MDC/MDIO 11.4.3 Repeater Mode Timing Parameters Symbol Parameter Conditions Min Typ Max Units T14 TRDRV PORTEN assertion to RXD[3:0], RXDV, and RXERR (RXC driven) 1.5 2.
82555 — Networking Silicon 11.4.4 Transmit Packet Timing Parameters Symbol Parameter Conditions Min Typ Max Units T15 TXEN_ST TXC on first TXEN active to start of frame 100 Mbps 10 12 bits T15a TXEN_ST TXC on first TXEN active to start of frame 10 Mbps 3.5 5 bits T16 TXEN_CRSH TXC on first TXEN active to rising edge of CRS 100 Mbps 4 bits T16a TXEN_CRSH TXC on first TXEN active to rising edge of CRS 10 Mbps 1.
Networking Silicon — 82555 TXCLK TXEN T20 T21 COL Figure 20. Squelch Test Timing Parameters 11.4.6 Jabber Timing Parameters Symbol Parameter Conditions Min Typ Max Units T22 TJAB_ON Jabber turn-on delay (TXEN asserted to end of transmit frame) 10 Mbps 26 ms T23 TJAB_OFF Jabber turn-off delay (TXEN deasserted to falling edge of COL) 10 Mbps 410 ms TXEN T23 COL T22 TDP/TDN Figure 21. Jabber Timing Parameters 11.4.
82555 — Networking Silicon Symbol Parameter Conditions Min Typ Max Units T26a TR_CRSL End of receive frame to falling edge of CRS 10 Mbps 4.5 bits T27 TR_RXDVL End of receive frame to falling edge of RXDV 100 Mbps 12 bits T27a TR_RXDVL End of receive frame to falling edge of RXDV 10 Mbps 4 bits Max Units 24 ms RXCLK RXDV T25,T25a T24,T24a CRS T27,T27a T26,T26a Frame On link Valid Frame Data Figure 22. Receive Packet Timing Parameters 11.4.
Networking Silicon — 82555 Symbol Parameter Conditions T33 TFLP_BUR_NUM Number of pulses in one burst T34 TFLP_BUR_WID FLP Burst width T35 TFLP_BUR_PER FLP burst period Min Typ Max 17 Units 33 2 ms 8 24 ms Max Units T30 T31 T30 Fast Link Pulse Clock Pulse T35 Data Pulse Clock Pulse T34 FLP Bursts Figure 24. Fast Link Pulse Timing Parameters 11.4.
82555 — Networking Silicon 4.0V 2.5V 0.4V T39 T39 T38 Figure 26. X1 Clock Specifications 11.4.
Networking Silicon — 82555 12.0 82555 Package Information This section provides the physical packaging information for the 82555. The 82555 is an 100-pin plastic Quad Flat Pack (QFP) device. Package attributes are provided in Table 7 and the dimensions are shown in Figure 27. Plane Seating D D1 A1 E E1 e A b C Detail A Seating Plane Y See Detail A T L1 PC-3712 Figure 27. Dimension Diagram for the 82555 QFP Table 7.
82555 — Networking Silicon Table 7. Dimensions for the 82555 QFP Symbol 54 Description Min Norm Max T Lead Angle 0.0 - 10.0 Y Coplanarity - - 0.
