Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 Supporting: Intel® Xeon® Processor E3-1125C Intel® Xeon® Processor E3-1105C Intel® Core™ i3 Processor 2115C Intel® Pentium® Processor B915C Intel® Celeron® Processor 725C Document #324803 - 2nd Generation Intel® Core™ Processor Family Mobile Datasheet Volume 2 completes the documentation set and contains additional product information.
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Revision History Revision History Date Revision Description May 2012 001 Initial release May 2012 Document Number: 327405-001 Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 3
Contents Contents 1.0 Introduction ............................................................................................................11 1.1 Purpose / Scope / Audience.................................................................................11 1.2 Related Documents ............................................................................................11 1.3 Terminology......................................................................................................13 2.
Contents 4.2 4.3 4.4 4.5 4.1.4 4.1.5 Intel® Intel® Intel® 4.4.1 Intel® Intel® VT-d Features .............................................................................. 40 Intel® VT-d Features Not Supported ......................................................... 41 Hyper-Threading Technology ..................................................................... 41 Advanced Vector Extensions (Intel® AVX) ...................................................
Contents 9.0 Electrical Specifications ...........................................................................................81 9.1 Power and Ground Pins.......................................................................................81 9.2 Decoupling Guidelines ........................................................................................81 9.2.1 Voltage Rail Decoupling ...........................................................................81 9.3 Processor Clocking (BCLK, BCLK#).
Contents 3-5 3-6 6-1 6-2 6-3 6-4 7-1 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 10-1 10-2 10-3 10-4 10-5 10-6 PCI Express* PCI Port Bifurcation ......................................................................... 33 PCIe* Typical Operation 16 Lanes Mapping ............................................................ 34 Power States .....................................................................................................
Contents 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 10-1 10-2 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 Memory Reference and Compensation ...................................................................74 Reset and Miscellaneous Signals ...........................................................................74 PCI Express* Interface Signals ........
Contents 11-13 Error Syndrome - ERRSYND...............................................................................
Contents Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 10 May 2012 Document Number: 327405-001
Introduction 1.0 Introduction 1.1 Purpose / Scope / Audience This document is to be used by Intel customers in place of the 2nd Generation Intel® Core™ Processor Family Mobile Datasheet - Volume 1 document #324803.
Introduction Table 1-2. Public Specifications Document Document Number/ Location Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/ PCI Local Bus Specification 3.0 http://www.pcisig.com/ specifications PCI Express Base Specification, Rev. 2.0 http://www.pcisig.com DDR3 SDRAM Specification http://www.jedec.org DisplayPort Specification http://www.vesa.org Intel® 64 and IA-32 Architectures Software Developer's Manuals: http://www.intel.
Introduction 1.3 Terminology Table 1-3. Terminology (Sheet 1 of 2) Term DDR3 Description Third-generation Double Data Rate SDRAM memory technology DMA Direct Memory Access DMI Direct Media Interface DTS Digital Thermal Sensor ECC Error Correction Code Enhanced Intel SpeedStep® Technology Technology that provides power management capabilities to laptops.
Introduction Table 1-3. Terminology (Sheet 2 of 2) Term Description PCU Power Control Unit Rank A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a DIMM. SCI System Control Interrupt. Used in ACPI protocol. Storage Conditions A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.
Product Overview 2.0 Product Overview The Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure is a repackaging of the 2nd Generation Intel® Core™ Mobile Processor family. This document addresses pairing the Intel® Xeon®, Intel® Core™, Intel® Pentium®, and Intel® Celeron® processors with an Intel® Platform Controller Hub (known as the PCH), which is referred to as the Crystal Forest Platform.
Ch B XDP0 Ch A Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 16 Clock IC CK420BQ DRAM DDR3 (Ch B) DDR3 (Ch A) PS2 37.5x37.5 1284 balls Processor DRA SIO M SERIAL SMBus PECI PCIe Gen1 x1 PCIe Gen1 x1 PCIe Gen1 x1 PCIe Gen1 x1 x4 DMI PCIe Gen2 x16 2 PCH LPC 480Mbs USB 3.0Gbs SATA SPI 1.25Gbs/lane SGMII Port 80 TPM USB 2 SATA Conn(s) PCH JTAG 4 ports – Rear Panel 2 ports – Front HDR.
Product Overview 2.1 Product Features 2.2 Processor Details • Four, two or single execution cores (4C, 2C or 1C respectively) • 32-KB data first-level cache (L1) for each core, parity protected • 32-KB instruction first-level cache (L1) for each core, ECC protected • 256-KB shared instruction/data second-level cache (L2) for each core, ECC protected • Up to 8-MB shared instruction/data third-level cache (L3) across all cores, ECC protected 2.
Product Overview • 72-bit wide channels, 64-bit data + 8-bit ECC • 64-bit wide channels, without ECC option • DDR3 I/O Voltage of 1.5 V • Supports ECC and non-ECC, unbuffered DDR3 DIMMs — Mixing of ECC and Non-ECC DIMMS is not supported • Theoretical maximum memory bandwidth of: — 17.1 GB/s in dual-channel mode assuming DDR3 1066 MT/s — 21.3 GB/s in dual-channel mode assuming DDR3 1333 MT/s — 25.
Product Overview — Four single-lane PCI Express* ports intended for I/O via the PCH • PCI Express* 1 x16 port is mapped to PCI Device 1. — One 16-lane/Two 8-lane/One 8-lane and Two 4-lane PCI Express* port • PCI Express* 1 x4 port is mapped to PCI Device 6. • The port may negotiate down to narrower widths. — Support for x16/x8/x4/x1 widths for a single PCI Express* mode. • 2.5 GT/s and 5.0 GT/s PCI Express* frequencies are supported. • Gen1 Raw bit-rate on the data pins of 2.
Product Overview • Static lane numbering reversal — Does not support dynamic lane reversal, as defined (optional) by the PCI Express Base Specification, Rev. 2.0. • Supports Half Swing “low-power/low-voltage” mode. Note: The processor does not support PCI Express* Hot-Plug. 2.4.3 Direct Media Interface (DMI) • DMI 2.0 support. • Four lanes in each direction. • 2.5 GT/s and 5.0 GT/s DMI interface to PCH • Gen1 Raw bit-rate on the data pins of 2.
Product Overview 2.5 Power Management Support 2.5.1 Processor Core • Full support of ACPI C-states as implemented by the following processor C-states: C0, C1, C1E, C3, C6, C7 • Enhanced Intel SpeedStep® Technology 2.5.2 System Full support of the ACPI S-states as implemented by the following system S-states: S0, S3, S4, S5 2.5.3 Memory Controller • Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM)) • Dynamic power-down 2.5.
Product Overview Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 22 May 2012 Document Number: 327405-001
Interfaces 3.0 Interfaces This chapter describes the interfaces supported by the processor. 3.1 System Memory Interface 3.1.1 System Memory Configurations Supported The Integrated Memory Controller (IMC) of the processor supports DDR3 protocols with two independent, 72-bit wide channels. These two memory channels are capable of running speeds up to 1600MT/s. Each channel consists of 64 data and 8 ECC bits.
Interfaces 3.1.1.1 UDIMM Configurations This section describes the UDIMM modules supported.
Interfaces 3.1.1.2 SO-DIMM Configurations The processor supports SO-DIMM and ECC SO-DIMM designs. Table 3-2 details the SODIMM modules that are supported. However, these have not been fully validated. Table 3-2.
Interfaces 3.1.1.3 Memory Down Configurations The processor supports the following Memory Down configurations. Table 3-3.
Interfaces Table 3-4. DDR3 System Memory Timing Support Processor SKUs 4-Core SKUs 2-Core SKUs 1-Core SKUs Note: 3.1.
Interfaces Figure 3-1. Intel® Flex Memory Technology Operation TOM C N o n in te r le a v e d access B C D ual channel in te r le a v e d a c c e s s B B CH A CH B B B – T h e la rg e s t p h y s ic a l m e m o ry a m o u n t o f th e s m a lle r s iz e m e m o ry m o d u le C – T h e re m a in in g p h y s ic a l m e m o ry a m o u n t o f th e la rg e r s iz e m e m o ry m o d u le 3.1.3.2.
Interfaces 3.1.5.1 Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next. The most efficient request is picked from all pending requests and issued to system memory Just-in-Time to make optimal use of Command Overlapping.
Interfaces The processor has four PCI Express* controllers that can be independently configured to either Gen 1 or Gen 2, allowing operation at both 2.5 GT/s (Giga-Transfers per second) and 5.0 GT/s data rates.
Interfaces PCI Express* uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers.
Interfaces 3.2.2 PCI Express* Configuration Mechanism All of the PCI Express* controllers are mapped through a PCI-to-PCI bridge structure. The controllers for the 16 lanes (Port 1) are mapped to the root port of Device 1: • The x16 controller is mapped to Function 0 • The x8 controller is mapped to Function 1 • The x4 controller is mapped to Function 2 The additional x4 controller for lanes (Port 2) is mapped to Device 6 Function 0. Port 2 is not available on 1 Core SKUs.
Interfaces Figure 3-5.
Interfaces 3.2.4 PCI Express* Lanes Connection Figure 3-6 demonstrates the PCIe* lanes mapping. Figure 3-6.
Interfaces 3.2.5 Configuring PCIe* Lanes Note: The controllers in Port 1 cannot be used to function with the controller in Port 2. Therefore, the x16 lanes of Port 1 must not be combined with the x4 lanes of Port 2. The following details apply to the 3 controllers in Port 1, as Port 2 cannot be bifurcated. The configuration of the PCIe* bus is statically determined by the pre-boot software prior to initialization.
Interfaces 3.2.6 Lane Reversal on PCIe* Interface The PCI Express* lanes can be reversed for ease of design and layout. Lane reversal is done statically, which means that the BIOS needs to configure the reversal before the relevant root port is enabled. For the x16 configuration, only one reversal option is supported allowing either a straight or a rotated CPU on the motherboard. No other combination of partial slot reversal is permitted.
Interfaces • Allow communication of processor thermal and other information to the PECI master. • Read averaged Digital Thermal Sensor (DTS) values for fan speed control. 3.5 Interface Clocking 3.5.1 Internal Clocking Requirements Table 3-7.
Interfaces Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 38 May 2012 Document Number: 327405-001
Technologies 4.0 Technologies 4.1 Intel® Virtualization Technology Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel® VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets.
Technologies • Virtual Processor IDs (VPID) — Ability to assign a VM ID to tag processor core hardware structures (e.g., TLBs) — This avoids flushes on VM transitions to give a lower-cost VM transition time and an overall reduction in virtualization overhead. • Guest Preemption Timer — Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM.
Technologies • MSI cycles (MemWr to address FEEx_xxxxh) not translated — Translation faults result in cycle forwarding to VBIOS region (byte enables masked for writes). Returned data may be bogus for internal agents, PEG/DMI interfaces return unsupported request status • Interrupt Remapping is supported • Queued invalidation is supported.
Technologies 4.4 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) The processor supports Advanced Encryption Standard New Instructions (Intel® AESNI), which are a set of Single Instruction Multiple Data (SIMD) instructions that enable fast and secure data encryption and decryption based on the Advanced Encryption Standard (AES).
Technologies — In x2APIC mode, APIC registers are accessed through Model Specific Register (MSR) interfaces. In this mode, the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery. • Increased range of processor addressability in x2APIC mode: — Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt processor addressability up to 4G-1 processors in physical destination mode.
Technologies Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 44 May 2012 Document Number: 327405-001
Processor SKUs 5.0 Processor SKUs 5.1 Overview This section details the features of the various SKUs of the Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure. The mix of SKUs are chosen to span cost, performance, temperature environment and power consumption. 5.1.1 SKU Features Table 5-1 outlines the processor SKUs available. Table 5-1.
Processor SKUs Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 46 May 2012 Document Number: 327405-001
Power Management 6.0 Power Management This chapter provides information on the following power management topics: • ACPI States • Processor Core • Integrated Memory Controller (IMC) • PCI Express* • Direct Media Interface (DMI) Figure 6-1.
Power Management 6.1 ACPI States Supported The ACPI states supported by the processor are described in this section. 6.1.1 System States Table 6-1. System States State Description G0/S0 Full On G1/S3-Cold Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor). G1/S4 Suspend-to-Disk (STD). All power lost (except wakeup on PCH). G2/S5 Soft off. All power lost (except wakeup on PCH). Total reboot. G3 Mechanical off.
Power Management 6.1.4 PCIe* Link States Table 6-4. PCIe* Link States State Description L0 Full on – Active transfer state. L0s First Active Power Management low power state – Low exit latency. L1 Lowest Active Power Management - Longer exit latency. L3 Lowest power state (power-off) – Longest exit latency. 6.1.5 DMI States Table 6-5. DMI States State Description L0 Full on – Active transfer state. L0s First Active Power Management low power state – Low exit latency.
Power Management 6.2.1 Enhanced Intel SpeedStep® Technology The following are the key features of Enhanced Intel SpeedStep Technology: • Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.
Power Management Entry and exit of the C-States at the thread and core level are shown in Figure 6-3. Figure 6-3. Thread and Core C-State Entry and Exit C0 MWAIT(C1), HLT MWAIT(C1), HLT (C1E Enabled) C1 MWAIT(C7), P_LVL4 I/O Read MWAIT(C6), P_LVL3 I/O Read MWAIT(C3), P_LVL2 I/O Read C1E C3 C6 C7 While individual threads can request low power C-states, power saving actions only take place once the core C-state is resolved. Core C-states are automatically resolved by the processor.
Power Management Table 6-8. P_LVLx to MWAIT Conversion P_LVLx MWAIT(Cx) Notes P_LVL2 MWAIT(C3) The P_LVL2 base address is defined in the PMG_IO_CAPTURE MSR. P_LVL3 MWAIT(C6) C6. No sub-states allowed. P_LVL4 MWAIT(C7) C7. No sub-states allowed. P_LVL5+ MWAIT(C7) C7. No sub-states allowed. The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict the range of I/O addresses that are trapped and emulate MWAIT like functionality.
Power Management 6.2.4.3 Core C3 State Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while maintaining its architectural state. All core clocks are stopped at this point.
Power Management • A package C-state request is determined by the lowest numerical core C-state amongst all cores. • A package C-state is automatically resolved by the processor depending on the core idle power states and the status of the platform components. — Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C-state. — The platform may allow additional power savings to be realized in the processor.
Power Management Figure 6-4. Package C-State Entry and Exit C0 C3 C6 C1 6.2.5.1 C7 Package C0 The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0. 6.2.5.
Power Management 6.2.5.3 Package C3 State A processor enters the package C3 low power state when: • At least one core is in the C3 state. • The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform. • The platform has not granted a request to a package C6/C7 state but has allowed a package C6 state. In package C3-state, the L3 shared cache is snoopable. 6.2.5.
Power Management 6.3 IMC Power Management The main memory is power managed during normal operation and in low-power ACPI Cx states. 6.3.1 Disabling Unused System Memory Outputs Any system memory (SM) interface signal that goes to a memory module connector in which it is not connected to any actual memory devices (such as DIMM connector is unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM signals are: • Reduced power consumption.
Power Management 1. No power-down. 2. APD: The rank enters power-down as soon as idle-timer expires, no matter what is the bank status. 3. PPD: When idle timer expires the MC sends PRE-all to rank and then enters powerdown. 4. DLL-off: same as option (2) but DDR is configured to DLL-off. 5. APD, change to PPD (APD-PPD): Begins as option (1), and when all page-close timers of the rank are expired, it wakes the rank, issues PRE-all, and returns to PPD. 6.
Power Management 6.3.2.1 Initialization Role of CKE During power-up, CKE is the only input to the SDRAM that has its level is recognized (other than the DDR3 reset pin) once power is applied. It must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during powerup. CKE signals remain LOW (while any reset is active) until the BIOS writes to a configuration register.
Power Management Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 60 May 2012 Document Number: 327405-001
Thermal Management 7.0 Thermal Management The thermal solution provides both the component-level and the system-level thermal management. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed so that the processor: • Remains below the maximum junction temperature (TJ-MAX) specification at the maximum Thermal Design Power (TDP).
Thermal Management Table 7-1. Table 7-2. TDP Specifications Product Number State CPU Core Frequency Thermal Design Power Intel® Xeon® Processor E3-1125C HFM up to 2.0 GHz 40 LFM 800 MHz 22 Intel® Xeon® Processor E3-1105C HFM up to 1.0 GHz 25 LFM 800 MHz 22 Intel® Core™ i3 Processor 2115C HFM up to 2.0 GHz 25 LFM 800 MHz 13 Intel® Pentium® Processor B915C HFM up to 1.5 GHz 15 LFM 800 MHz 13 Intel® Celeron® Processor 725C HFM up to 1.
Thermal Management 7.3 Thermal Management Features This section covers thermal management features for the processor. 7.3.1 Processor Package Thermal Features This section covers thermal management features for the entire processor complex (including the processor core and integrated memory controller hub) and is referred to as processor package or package. Occasionally the package operates in conditions that exceed its maximum allowable operating temperature.
Thermal Management • The voltage is optimized according to the temperature, the core bus ratio, and number of cores in deep C-states. • The core power and temperature are reduced while minimizing performance degradation. A small amount of hysteresis has been included to prevent an excessive amount of operating point transitions when the processor temperature is near its maximum operating temperature.
Thermal Management If a processor load-based Enhanced Intel SpeedStep Technology/P-state transition (through MSR write) is initiated while the Adaptive Thermal Monitor is active, there are two possible outcomes: • If the P-state target frequency is higher than the processor core optimized target frequency, the p-state transition is deferred until the thermal event has been completed.
Thermal Management Unlike traditional thermal devices, the DTS outputs a temperature relative to the maximum supported operating temperature of the processor (TJ-MAX), regardless of TCC activation offset. It is the responsibility of software to convert the relative temperature to an absolute temperature. The absolute reference temperature is readable in the TEMPERATURE_TARGET MSR 1A2h. The temperature returned by the DTS is an implied negative integer indicating the relative offset from TJ-MAX.
Thermal Management consumption. Bi-directional PROCHOT# can allow VR thermal designs to target thermal design current (ICCTDC) instead of maximum current. Systems should still provide proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. Overall, the system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. 7.3.1.3.
Thermal Management 7.3.2 Processor Core Specific Thermal Features 7.3.2.1 On-Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption via clock modulation. This mechanism is referred to as “On-Demand” mode and is distinct from Adaptive Thermal Monitor and bi-directional PROCHOT#. Processor platforms must not rely on software usage of this mechanism to limit the processor temperature.
Thermal Management The PECI physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a Logic 0 or Logic 1. PECI also includes variable data transfer rate established with every message. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components.
Thermal Management Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 70 May 2012 Document Number: 327405-001
Signal Description 8.0 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type: Notations Signal Type I Input Pin O Output Pin I/O Bi-directional Input/Output Pin The signal description also includes the type of buffer used for the particular signal. Table 8-1.
Signal Description Table 8-2. Table 8-3. Memory Channel A (Sheet 2 of 2) Signal Name Description Direction/Buffer Type SA_CAS# CAS Control Signal: Used with SA_RAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands. O DDR3 SA_DQS[7:0] SA_DQS#[7:0] Data Strobes: SA_DQS[7:0] and its complement signal group make up a differential strobe pair. The data is captured at the crossing point of SA_DQS[7:0] and its SA_DQS#[7:0] during read and write transactions.
Signal Description Table 8-3. Memory Channel B (Sheet 2 of 2) Signal Name Description Direction/Buffer Type SB_CAS# CAS Control Signal: Used with SB_RAS# and SB_WE# (along with SB_CS#) to define the SRAM Commands. O DDR3 SB_DQS[7:0] SB_DQS#[7:0] Data Strobes: SB_DQS[7:0] and its complement signal group make up a differential strobe pair. The data is captured at the crossing point of SB_DQS[7:0] and its SB_DQS#[7:0] during read and write transactions.
Signal Description 8.2 Memory Reference and Compensation Table 8-4. Memory Reference and Compensation Signal Name SM_RCOMP[2:0] SM_VREF Direction/Buffer Type Description System Memory Impedance Compensation: SM_RCOMP[0] Pull Down to VSS via 140 Ω ±1% SM_RCOMP[1] Pull Down to VSS via 25.5 Ω ±1% SM_RCOMP[2] Pull Down to VSS via 200 Ω ±1% DDR3 Reference Voltage: This provides reference voltage to the DDR3 interface and is defined as VDDQ/2 8.3 Reset and Miscellaneous Signals Table 8-5.
Signal Description Table 8-5. Reset and Miscellaneous Signals (Sheet 2 of 2) Signal Name Description DDR3 DRAM Reset: Reset signal from processor to DRAM devices. One common to all channels. SM_DRAMRST# RSVD_[21:1],RSVD_[32:23], RSVD_[43:34],RSVD_[57:45] RESERVED: All signals in this group are RSVD pins which must be left unconnected. RSVD_22, RSVD_33, RSVD_44 Terminated RESERVED: These pins must be shorted together and tied to VCCP through 24.9 Ω ±1% resistor. 8.
Signal Description 8.6 PLL Signals Table 8-8. PLL Signals Signal Name Description Direction/Buffer Type BCLK BCLK# Differential bus clock input to the processor and PCI Express*. I Diff Clk 8.7 TAP Signals Table 8-9. TAP Signals Signal Name Description Direction/Buffer Type BPM#[7:0] Breakpoint and Performance Monitor Signals: Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance.
Signal Description 8.8 Error and Thermal Protection Table 8-10. Error and Thermal Protection Signal Name Description Direction/Buffer Type CATERR# Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor sets this for non-recoverable machine check errors or other unrecoverable internal errors. External agents are allowed to assert this pin which causes the processor to take a machine check exception.
Signal Description 8.9 Power Sequencing Table 8-11. Power Sequencing Signal Name SM_DRAMPWROK UNCOREPWRGOOD PROC_DETECT# 8.10 Direction/Buffer Type Description SM_DRAMPWROK Processor Input: Connects to PCH DRAMPWROK. I Asynchronous CMOS The processor requires this input signal to be a clean indication that the VCCSA, VCCIO, VAXG, and VDDQ, power supplies are stable and within specifications. This requirement applies regardless of the S-state of the processor.
Signal Description 8.11 Sense Pins Table 8-13. Sense Pins 8.12 Signal Name Description Direction/Buffer Type VCC_SENSE VSS_SENSE VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to the processor core voltage and ground. They can be used to sense or measure voltage near the silicon. O Analog VCCIO_SENSE VSS_SENSE_VCCIO VCCIO_SENSE and VSS_SENSE_VCCIO provide an isolated, low impedance connection to the processor VCCIO voltage and ground.
Signal Description Table 8-15.
Electrical Specifications 9.0 Electrical Specifications 9.1 Power and Ground Pins The processor has VCC, VCCIO, VDDQ, VCCPLL, VCCSA and VSS (ground) inputs for on-chip power distribution. All power pins must be connected to their respective processor power planes, while all VSS pins must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop.
Electrical Specifications 9.3 Processor Clocking (BCLK, BCLK#) The processor utilizes a differential clock to generate the processor core(s) operating frequency, memory controller frequency, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by 100 MHz. Clock multiplying within the processor is provided by an internal phase locked loop (PLL), which requires a constant frequency input, with exceptions for Spread Spectrum Clocking (SSC).
Electrical Specifications Table 9-1. IMVP7 Voltage Identification Definition (Sheet 2 of 8) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 0 0 0 1 0 0 0 0 8 0.28500 0 0 0 0 1 0 0 1 0 9 0.29000 0 0 0 0 1 0 1 0 0 A 0.29500 0 0 0 0 1 0 1 1 0 B 0.30000 0 0 0 0 1 1 0 0 0 C 0.30500 0 0 0 0 1 1 0 1 0 D 0.31000 0 0 0 0 1 1 1 0 0 E 0.31500 0 0 0 0 1 1 1 1 0 F 0.32000 0 0 0 1 0 0 0 0 1 0 0.
Electrical Specifications Table 9-1. IMVP7 Voltage Identification Definition (Sheet 3 of 8) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 0 1 1 0 0 0 0 3 0 0.48500 0 0 1 1 0 0 0 1 3 1 0.49000 0 0 1 1 0 0 1 0 3 2 0.49500 0 0 1 1 0 0 1 1 3 3 0.50000 0 0 1 1 0 1 0 0 3 4 0.50500 0 0 1 1 0 1 0 1 3 5 0.51000 0 0 1 1 0 1 1 0 3 6 0.51500 0 0 1 1 0 1 1 1 3 7 0.52000 0 0 1 1 1 0 0 0 3 8 0.
Electrical Specifications Table 9-1. IMVP7 Voltage Identification Definition (Sheet 4 of 8) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 1 0 1 1 0 0 0 5 8 0.68500 0 1 0 1 1 0 0 1 5 9 0.69000 0 1 0 1 1 0 1 0 5 A 0.69500 0 1 0 1 1 0 1 1 5 B 0.70000 0 1 0 1 1 1 0 0 5 C 0.70500 0 1 0 1 1 1 0 1 5 D 0.71000 0 1 0 1 1 1 1 0 5 E 0.71500 0 1 0 1 1 1 1 1 5 F 0.72000 0 1 1 0 0 0 0 0 6 0 0.
Electrical Specifications Table 9-1. IMVP7 Voltage Identification Definition (Sheet 5 of 8) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 0 0 0 0 0 0 0 8 0 0.88500 1 0 0 0 0 0 0 1 8 1 0.89000 1 0 0 0 0 0 1 0 8 2 0.89500 1 0 0 0 0 0 1 1 8 3 0.90000 1 0 0 0 0 1 0 0 8 4 0.90500 1 0 0 0 0 1 0 1 8 5 0.91000 1 0 0 0 0 1 1 0 8 6 0.91500 1 0 0 0 0 1 1 1 8 7 0.92000 1 0 0 0 1 0 0 0 8 8 0.
Electrical Specifications Table 9-1. IMVP7 Voltage Identification Definition (Sheet 6 of 8) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 0 1 0 1 0 0 0 A 8 1.08500 1 0 1 0 1 0 0 1 A 9 1.09000 1 0 1 0 1 0 1 0 A A 1.09500 1 0 1 0 1 0 1 1 A B 1.10000 1 0 1 0 1 1 0 0 A C 1.10500 1 0 1 0 1 1 0 1 A D 1.11000 1 0 1 0 1 1 1 0 A E 1.11500 1 0 1 0 1 1 1 1 A F 1.12000 1 0 1 1 0 0 0 0 B 0 1.
Electrical Specifications Table 9-1. IMVP7 Voltage Identification Definition (Sheet 7 of 8) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 0 1 0 0 0 0 D 0 1.28500 1 1 0 1 0 0 0 1 D 1 1.29000 1 1 0 1 0 0 1 0 D 2 1.29500 1 1 0 1 0 0 1 1 D 3 1.30000 1 1 0 1 0 1 0 0 D 4 1.30500 1 1 0 1 0 1 0 1 D 5 1.31000 1 1 0 1 0 1 1 0 D 6 1.31500 1 1 0 1 0 1 1 1 D 7 1.32000 1 1 0 1 1 0 0 0 D 8 1.
Electrical Specifications Table 9-1. 9.5 IMVP7 Voltage Identification Definition (Sheet 8 of 8) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX VCC_MAX 1 1 1 1 1 0 0 0 F 8 1.48500 1 1 1 1 1 0 0 1 F 9 1.49000 1 1 1 1 1 0 1 0 F A 1.49500 1 1 1 1 1 0 1 1 F B 1.50000 1 1 1 1 1 1 0 0 F C 1.50500 1 1 1 1 1 1 0 1 F D 1.51000 1 1 1 1 1 1 1 0 F E 1.51500 1 1 1 1 1 1 1 1 F F 1.
Electrical Specifications 9.6 Reserved or Unused Signals The following are the general types of reserved (RSVD) signals and connection guidelines: • RSVD_22, RSVD_33 and RSVD_44 - These pins must be shorted together and tied to VCCP through 24.9 ohm 1% resistor. • RSVD_[21:1], RSVD_[32:23], RSVD_[43:34] and RSVD_[57:45] - these signals should not be connected. Note: For more information regarding termination and layout guidelines, see the appropriate platform design guide.
Electrical Specifications Table 9-3.
Electrical Specifications Table 9-3.
Electrical Specifications Table 9-4. Storage Condition Ratings Symbol Parameter Min Max Notes -25°C 125°C 1, 2, 3, 4 5, 6 Tabsolute storage The non-operating device storage temperature. Damage (latent or otherwise) may occur when exceeded for any length of time. Tsustained storage The ambient storage temperature (in shipping media) for a sustained period of time). -5°C 40°C Tshort term storage The ambient storage temperature (in shipping media) for a short period of time.
Electrical Specifications 9.10.1 Voltage and Current Specifications Note: The following specifications and parameters are based on characterized data from silicon measurements. Table 9-5.
Electrical Specifications Table 9-5. Symbol Ripple Processor Core (VCC) DC Voltage and Current Specifications (Sheet 2 of 2) Product Number Parameter Ripple Tolerance Min Typ Max PS0 & Icc > TDC+30% +/- 15 PS0 & Icc <= TDC+30% +/- 10 PS1 +/- 13 PS2 - 7.5/+18.5 PS3 - 7.5/+27.
Electrical Specifications Table 9-6. Processor Uncore (VCCIO) Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit 1.
Electrical Specifications Table 9-8. System Agent (VCCSA) Supply DC Voltage and Current Specifications Symbol Parameter Slew Rate Voltage Ramp rate (dV/dT) di/dt Step current Min Typ 0.5 Max Unit Note 10 mV/uS 1 A 2, 3 2 Notes: 1. Long term reliability cannot be assured in conditions above or below Max/Min functional limits. 2. Step current is done in 100nS 3. di/dt values are for platform testing only. This parameter is not tested on Intel silicon.
Electrical Specifications Table 9-10. DDR3 Signal Group DC Specifications (Sheet 2 of 2) Symbol Parameter Min Typ Max Units Notes1 RON_DN(CMD) DDR3 Command Buffer pull-down Resistance 15.7 19.8 24.0 Ω 5 RON_UP(CTL) DDR3 Control Buffer pull-up Resistance 14.9 20.1 23.7 Ω 5 RON_DN(CTL) DDR3 Control Buffer pull-down Resistance 14.5 19.2 24.3 Ω 5 ILI Input Leakage Current (DQ, CK) 0V 0.2*VDDQ 0.8*VDDQ VDDQ ± 0.75 ± 0.55 ± 0.9 ± 1.4 mA ILI Input Leakage Current (CMD, CTL) 0V 0.
Electrical Specifications Table 9-12. PCI Express* DC Specifications Symbol Parameter Min Typ Max Units Notes1 VTX-DIFF-p-p Differential Peak-to-Peak Tx Voltage Swing 0.4 0.5 0.6 V 4 VTX_CM-AC-p Tx AC Peak Common Mode Output Voltage (Gen 1 Only) 0.8 1 1.
Electrical Specifications Figure 9-1. Example of PECI Host-Client Connection 9.10.2.2 PECI DC Characteristics The PECI interface operates at a nominal voltage set by VCCIO. The set of DC electrical specifications shown in Table 9-13 are used with devices normally operating from a VCCIO interface supply. VCCIO nominal levels will vary between processor families. All PECI devices will operate at the VCCIO level determined by the processor installed in the system. Table 9-13.
Electrical Specifications Table 9-13. PECI DC Electrical Limits (Sheet 2 of 2) Symbol Definition and Conditions Min Max Units Ileak075 leakage current @ 0.75*VCCIO - 0.13 mA Ileak100 leakage current @ VCCIO - 0.10 mA Notes1 Notes: 1. VCCIO supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. 2. The leakage specification applies to powered devices on the PECI bus. 3. The PECI buffer internal pull up resistance measured at 0.75*VCCIO 9.10.2.
Electrical Specifications Table 9-14. Differential Clocks (SSC on) SSC ON 1CLK 1 μs 0.1 s Signal Name -Jitter c-c Abs PerMin -SSC Short AvgMin -ppm Long AvgMin BCLK 9.849063 9.999063 10.02406 0.1 s 1 μs 1CLK Ideal DC Target +ppm Long AvgMax +SSC Short AvgMax +Jitter c-c Abs PerMax Units 10.02506 10.02607 10.05120 10.20120 ns Notes: 1. Ideal DC Target: This serves only as an ideal reference target (0 ppm) to use for calculating the rest of the period measurement values 2. 0.
Electrical Specifications Table 9-17. System Reference Clock DC and AC Specifications VCROSS Crossing Point Voltage Single Ended 250 550 mV RT 9-4 1,4,5 VCROSS_DELTA Variation of VCROSS Single Ended 140 mV RT 9-4 1,4,8 VMAX Max Output Voltage Single Ended 1.15 V RT 9-4 1,6 VMIN Min Output Voltage Single Ended V RT 9-4 1,7 DTY_CYC Duty Cycle Diff 60 % Avg 9-3 2 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. -0.
Electrical Specifications Table 9-18. DDR3 Electrical Characteristics and AC Timings at 1066 MT/s, VDDQ = 1.5 V ±0.075 V Symbol Parameter Channel A Channel B Max Unit Figure Note1,9 Min System Memory Latency Timings TCL – TRCD – TRP 7 – 7– 7 8– 8– 8 CAS Latency – RAS to CAS Delay – Pre-charge Command Period TCK Electrical Characteristics TSLR_D DQ[63:0], DQS[8:0], DQS#[8:0] Input Slew Rate 6.5 2.0 V/ns 2 System Memory Clock Timings TCK CK Period TCH CK High Time 0.
Electrical Specifications Table 9-19. DDR3 Electrical Characteristics and AC Timings at 1333 MT/s, VDDQ = 1.5 V ±0.075 V Symbol Channel A Channel B Parameter Max Unit Figure Note1,9 Min System Memory Latency Timings TCL – TRCD – TRP CAS Latency – RAS to CAS Delay – Pre-charge Command Period 9 – 9– 9 TCK Electrical Characteristics TSLR_D DQ[63:0], DQS[8:0], DQS#[8:0] Input Slew Rate 6.5 2.0 V/ns 2 System Memory Clock Timings TCK CK Period TCH CK High Time 0.
Electrical Specifications Table 9-20. DDR3 Electrical Characteristics and AC Timings at 1600 MT/s, VDDQ = 1.5 V ±0.075 V Symbol Parameter Channel A Channel B Max Unit Figure Note1,9 Min System Memory Latency Timings TCL – TRCD – TRP CAS Latency – RAS to CAS Delay – Pre-charge Command Period 11 – 11– 11 TCK Electrical Characteristics TSLR_D DQ[63:0], DQS[8:0], DQS#[8:0] Input Slew Rate 6.5 2.0 V/ns 2 System Memory Clock Timings TCK CK Period TCH CK High Time 0.
Electrical Specifications 9.11.2 PCI Express* AC Specification Table 9-21. PCI Express* AC Specification Symbol UI TTX-EYE TTX-RISE/FALL Parameter Min Max Units Unit Interval (Gen 1) 399.88 400.12 ps Unit Interval (Gen 2) 199.94 200.06 Minimum Transmission Eye Width UI D+/D- TX Out put Rise/Fall time (Gen 1) 0.125 UI D+/D- TX Out put Rise/Fall time (Gen 2) 0.15 UI 0.
Electrical Specifications 9.11.3 Miscellaneous AC Specifications Table 9-22. Miscellaneous AC Specifications T# Parameter T1: Asynchronous GTL input pulse width T4: PROCHOT# pulse width Min Max Unit Figure Notes 8 - BCLKs 9-10 1,2,3 500 - μs 9-10 1,2,3 - 500 ms 9-11 1,2,3 T5: THERMTRIP# assertion until VCC removed Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
Electrical Specifications 9.11.5 SVID Signal Group AC Specifications Table 9-24. SVID Signal Group AC Specifications T # Parameter VIDSCLK period Min Max Unit 38.90 - ns VIDSOUT output valid delay wrt to BCLK 1.20 9.60 ns VIDSOUT output jitter -3.60 0.65 ns Notes1, 2 3 VIDSOUT input setup time 1.00 - ns 3,4 VIDSOUT input hold time 3.00 - ns 3,4 VIDSCLK High Time 12.00 - ns 5 VIDSCLK Low Time 12.00 - ns 6 VIDSCLK Rise Time - 2.50 ns 7 VIDSCLK Fall Time - 2.
Electrical Specifications Figure 9-3. Differential Clock – Differential Measurements Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) 0.0V Clock-Clock# Rise Edge Rate Fall Edge Rate Vih_min = +150mV 0.
Electrical Specifications Figure 9-4. Differential Clock – Single Ended Measurements Clock# V max Vcross max Vcross min Clock V min Clock# Vcross delta Clock Vcross median l al Vcross median Tf Vcross median +75mV is e Clock# Tr Clock# Vcross median 75mV Clock Figure 9-5.
Electrical Specifications Figure 9-6. DDR3 Receiver Eye Mask 5% UI Vref + 100mV Vref – 100mV 25%UI Figure 9-7. DDR3 Clock to DQS Skew Timing Waveform CK# (IMC) CK (IMC) TSKEW_CK-DQS DQS (IMC) Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 112 TSKEW_CK-DQS 0.
Electrical Specifications Figure 9-8. PCI Express* Receiver Eye Margins Figure 9-9. TAP Valid Delay Timing Waveform TCK V Tx Signal Ts Th V Valid Tx = T17: TDO Clock to Output Delay Ts = T15: TDI, TMS Setup Time Th = T16: TDI, TMS Hold Time V = 0.5 * VTT Note: See Table 9-11 for TAP Signal Group DC specifications and Table 9-23 for TAP Signal Group AC specifications.
Electrical Specifications Figure 9-10. Test Reset (TRST#), Async Input, and PROCHOT# Timing Waveform V Tq T1 (Async CMOS Pulse Width) T = T4 (PROCHOT# Pulse Width) q T18 (TRST# Pulse Width) Figure 9-11. THERMTRIP# Power Down Sequence TA THERMTRIP# Vcc TA = T5: THERMTRIP# assertion until VCC removal 9.13 Signal Quality Data transfer requires the clean reception of data signals and clock signals.
Electrical Specifications 9.13.1 Input Reference Clock Signal Quality Specifications Overshoot/Undershoot and Ringback specifications for BCLK/BCLK# are found in Table 9-26. Overshoot/Undershoot and Ringback specifications for the DDR3 Reference Clocks are specified by the DIMM. 9.13.2 DDR3 Signal Quality Specifications Signal Quality specifications for Differential DDR3 Signals are included as part of the DDR3 DC specifications and DDR3 AC specifications.
Electrical Specifications Figure 9-12. VCC Overshoot Example Waveform Example Overshoot Waveform VID + VOS VOS Voltage (V) VID TOS Time TOS: Overshoot time above VID VOS: Overshoot above VID Note: Oscillations below the reference voltage cannot be subtracted from the total overshoot/ undershoot pulse duration. 9.14.2 Overshoot/Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the processor, both are referenced to VSS.
Electrical Specifications Table 9-26. Processor Overshoot/Undershoot Specifications Signal Group Control Sideband and TAP Signals groups PCIe and DMI Maximum Overshoot Overshoot Duration Minimum Undershoot Undershoot Duration Notes 1.18*VCCIO 37ns -0.27*VCCIO 3ns 1,2 1.2*VCCIO 0.25UI -0.275*VCCIO 0.25UI 1,2 Notes: 1. These specifications are measured at the processor pin. 2. See Figure 9-13 for description of allowable Overshoot/Undershoot magnitude and duration. Figure 9-13.
Electrical Specifications Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 118 May 2012 Document Number: 327405-001
Processor Ball and Package Information 10.0 Processor Ball and Package Information 10.1 Processor Ball Assignments • Table 10-1 provides a listing of all processor pins ordered alphabetically by ball name. • Table 10-2 provides a listing of all processor pins ordered alphabetically by ball number. • Figure 10-1, Figure 10-2, Figure 10-3, and Figure 10-4 show the bottom view of the processor ballmap.
Processor Ball and Package Information Table 10-1.
Processor Ball and Package Information Ball Signal Ball Signal Ball Signal D16 VSS E21 VCC F26 BPM#[7] D17 VCC E22 VSS F27 RSVD_43 D18 VCC E23 VCC F28 PROC_DETECT# D19 VSS E24 VCC F29 VSS D20 VCC E25 VSS F30 TMS D21 VCC E26 BPM#[6] F31 VSS D22 VSS E27 RSVD_41 F32 RSVD_19 D23 VCC E28 PM_SYNC F33 RSVD_16 D24 VCC E29 VIDSCLK F34 VSS D25 VSS E30 TDI F35 RSVD_36 D26 BPM#[3] E31 VIDALERT# F36 RSVD_17 D27 VSS E32 RSVD_37 G1 PCIE1_RX[15]
Processor Ball and Package Information Ball Signal Ball Signal Ball Signal G31 THERMTRIP# H36 VSS K5 PCIE1_TX#[9] G32 VSS J1 PCIE_ICOMPI K6 PCIE1_TX[9] G33 RSVD_34 J2 VSS K7 VSS G34 RSVD_32 J3 PCIE1_TX[10] K8 PCIE1_TX#[3] G35 VSS J4 PCIE1_TX#[8] K9 PCIE1_TX[3] G36 RSVD_35 J5 PCIE1_TX[8] K10 VSS H1 PCIE1_RX#[15] J6 PCIE1_TX#[6] K11 PCIE2_TX#[3] H2 VSS J7 PCIE1_TX[6] K12 PCIE2_TX[3] H3 VSS J8 VSS K13 VSS H4 VSS J9 PCIE1_TX#[2] K14 VCC H5 PCIE
Processor Ball and Package Information Ball Signal Ball Signal Ball Signal L10 PCIE2_TX#[2] M15 VCC N20 VCC L11 PCIE2_TX[2] M16 VSS N21 VCC L12 RSVD_8 M17 VCC N22 VSS L13 VSS M18 VCC N23 VCC L14 VCC M19 VSS N24 VCC L15 VCC M20 VCC N25 VSS L16 VSS M21 VCC N26 VCC L17 VCC M22 VSS N27 VSS L18 VCC M23 VCC N28 VCCIO L19 VSS M24 VCC N29 VCCIO L20 VCC M25 VSS N30 VSS L21 VCC M26 VCC_SENSE N31 CFG[3] L22 VSS M27 VSS_SENSE N32 CFG[6]
Processor Ball and Package Information Ball Signal Ball Signal Ball Signal P25 VSS R30 VSS T35 SA_DQ[57] P26 VCC R31 VSS T36 SA_DQ[56] P27 VSS R32 SA_DQS[7] U1 DMI_TX[1] P28 VCCIO R33 SA_DQ[59] U2 DMI_TX[2] P29 VCCIO R34 SA_DQ[58] U3 VSS P30 VSS R35 SA_DQ[62] U4 DMI_RX[2] P31 VSS R36 SA_DQ[63] U5 VSS P32 VSS T1 DMI_TX#[1] U6 VSS P33 VSS T2 VSS U7 VCCIO P34 VSS T3 DMI_RX#[0] U8 VCCIO P35 VSS T4 DMI_RX#[1] U9 VCCSA P36 VSS T5 VSS U10
Processor Ball and Package Information Ball Signal Ball Signal Ball Signal V4 DMI_RX#[2] W9 VSS Y14 VCC V5 DMI_RX[3] W10 VCCIO Y15 VCC V6 VSS W11 VCCSA Y16 VSS V7 VCCIO W12 VCC Y17 VCC V8 VCCIO W13 VSS Y18 VCC V9 VCCSA W14 VCC Y19 VSS V10 VSS W15 VCC Y20 VCC V11 VCCSA W16 VSS Y21 VCC V12 VCC W17 VCC Y22 VSS V13 VSS W18 VCC Y23 VCC V14 VCC W19 VSS Y24 VCC V15 VCC W20 VCC Y25 VSS V16 VSS W21 VCC Y26 VCC V17 VCC W22 VSS Y2
Processor Ball and Package Information Ball Signal Ball Signal Ball Signal AA19 VSS AB24 VCCIO AC29 VCCIO AA20 VCC AB25 VSS AC30 VCCIO AA21 VCC AB26 VCCIO AC31 VSS AA22 VSS AB27 VCCIO AC32 VSS AA23 VCC AB28 VCCIO AC33 VSS AA24 VCC AB29 VCCIO AC34 VSS AA25 VSS AB30 VCCIO AC35 VSS AA26 VCC AB31 VSS AC36 VSS AA27 VSS AB32 SA_DQS#[5] AD1 SB_DQ[6] AA28 VCCIO AB33 SA_DQ[44] AD2 SB_DQ[7] AA29 VCCIO AB34 SA_DQ[45] AD3 SB_DQ[2] AA30 VCCIO AB3
Processor Ball and Package Information Ball Signal Ball Signal Ball Signal AD34 SB_DQ[58] AF3 SA_DQ[0] AG8 SB_DQ[9] AD35 SB_DQ[62] AF4 SA_DQ[4] AG9 VSS AD36 SB_DQ[63] AF5 SA_DQS#[0] AG10 SA_DQ[16] AE1 VSS AF6 VSS AG11 SA_DQ[17] AE2 VSS AF7 SB_DQ[12] AG12 VSS AE3 VSS AF8 SB_DQ[13] AG13 SB_ECC_CB[0] AE4 VSS AF9 VSS AG14 SB_ECC_CB[1] AE5 VSS AF10 SA_DQ[20] AG15 VSS AE6 VSS AF11 SA_DQ[21] AG16 SB_CKE[1] AE7 VSS AF12 VSS AG17 VSS AE8 VSS AF13
Processor Ball and Package Information Ball Signal Ball Signal Ball Signal AH13 SB_DQS#[8] AJ18 SB_MA[8] AK23 VDDQ AH14 SB_DQS[8] AJ19 SB_MA[5] AK24 SA_WE# AH15 VSS AJ20 VSS AK25 SA_CS#[0] AH16 SB_BS[2] AJ21 SB_CK[1] AK26 VDDQ AH17 VDDQ AJ22 SB_CK#[2] AK27 SA_CS#[3] AH18 SB_MA[6] AJ23 VSS AK28 SA_ODT[3] AH19 SB_MA[4] AJ24 SB_BS[1] AK29 VSS AH20 VDDQ AJ25 SB_BS[0] AK30 SA_DQ[32] AH21 SB_CK[0] AJ26 VSS AK31 SA_DQ[36] AH22 SB_CK#[0] AJ27 SB_ODT[0]
Processor Ball and Package Information Ball Signal Ball Signal Ball Signal AL28 SA_ODT[1] AM33 VSS AP2 VSS AL29 VSS AM34 VSS AP3 SB_DQ[18] AL30 VSS AM35 VSS AP4 VSS AL31 VSS AM36 SB_DQS#[5] AP5 VSS AL32 VSS AN1 VSS AP6 VSS AL33 SB_DQ[46] AN2 SB_DQ[22] AP7 SB_DQ[29] AL34 SB_DQ[45] AN3 SB_DQ[23] AP8 SB_DQ[26] AL35 SB_DQ[41] AN4 SB_DQS[2] AP9 VSS AL36 SB_DQS[5] AN5 SB_DQ[19] AP10 SA_DQ[29] AM1 SB_DQ[20] AN6 VSS AP11 SA_DQ[26] AM2 SB_DQ[17] AN
Processor Ball and Package Information Ball Signal Ball Signal AR8 SB_DQ[31] AT16 SB_CKE[3] AR9 VSS AT17 VDDQ AR10 SA_DQ[24] AT18 SB_MA[14] AR11 SA_DQ[31] AT19 SB_MA[12] AR12 VSS AT20 VDDQ AR13 SA_ECC_CB[0] AT21 SB_MA[3] AR14 SA_ECC_CB[7] AT22 SB_MA[2] AR15 VSS AT23 VDDQ AR16 SM_VREF AT24 SM_RCOMP[1] AR17 VSS AT25 VDDQ AR18 SA_CKE[0] AT26 VDDQ AR19 SB_MA[9] AT27 SB_CS#[2] AR20 VSS AT28 SB_CAS# AR21 SA_MA[5] AT29 SM_RCOMP[0] AR22 SB_MA[1] AT30 S
Processor Ball and Package Information Table 10-2.
Processor Ball and Package Information Signal Ball Signal Ball Signal Ball PCIE2_TX[3] K12 RSVD_35 G36 SA_CKE[2] AK18 PCIE2_TX#[0] M7 RSVD_36 F35 SA_CKE[3] AM16 PCIE2_TX#[1] L8 RSVD_37 E32 SA_CS#[0] AK25 PCIE2_TX#[2] L10 RSVD_38 E34 SA_CS#[1] AN28 PCIE2_TX#[3] K11 RSVD_39 D33 SA_CS#[2] AP28 PECI J33 RSVD_40 D36 SA_CS#[3] AK27 PM_SYNC E28 RSVD_41 E27 SA_DIMM_VREFDQ AL16 PRDY# K26 RSVD_42 C28 SA_DQ[0] AF3 PREQ# G29 RSVD_43 F27 SA_DQ[1] AF1 PROC_DETE
Processor Ball and Package Information Signal Ball Signal Ball Signal Ball SA_DQ[4] AF4 SA_DQS#[2] AH10 SB_CK[0] AH21 SA_DQ[40] AB36 SA_DQS#[3] AM10 SB_CK[1] AJ21 SA_DQ[41] AB35 SA_DQS#[4] AH30 SB_CK[2] AK22 SA_DQ[42] AA34 SA_DQS#[5] AB32 SB_CK[3] AG21 SA_DQ[43] AA33 SA_DQS#[6] W32 SB_CK#[0] AH22 SA_DQ[44] AB33 SA_DQS#[7] T32 SB_CK#[1] AK21 SA_DQ[45] AB34 SA_DQS#[8] AM13 SB_CK#[2] AJ22 SA_DQ[46] AA35 SA_ECC_CB[0] AR13 SB_CK#[3] AG22 SA_DQ[47] AA36 SA_
Processor Ball and Package Information Signal Ball Signal Ball Signal Ball SB_DQ[30] AT8 SB_DQS[1] AH8 SB_ODT[0] AJ27 SB_DQ[31] AR8 SB_DQS[2] AN4 SB_ODT[1] AG27 SB_DQ[32] AP31 SB_DQS[3] AM8 SB_ODT[2] AR28 SB_DQ[33] AR31 SB_DQS[4] AM32 SB_ODT[3] AG28 SB_DQ[34] AP32 SB_DQS[5] AL36 SB_RAS# AH25 SB_DQ[35] AN32 SB_DQS[6] AG33 SB_WE# AG24 SB_DQ[36] AN31 SB_DQS[7] AD32 SM_DRAMPWROK AF19 SB_DQ[37] AT31 SB_DQS[8] AH14 SM_DRAMRST# AN16 SB_DQ[38] AR32 SB_DQS#[0]
Processor Ball and Package Information Signal Ball Signal Ball Signal Ball VCC C21 VCC H23 VCC N23 VCC C23 VCC H24 VCC N24 VCC C24 VCC J14 VCC N26 VCC D14 VCC J15 VCC P12 VCC D15 VCC J17 VCC P14 VCC D17 VCC J18 VCC P15 VCC D18 VCC J20 VCC P17 VCC D20 VCC J21 VCC P18 VCC D21 VCC J23 VCC P20 VCC D23 VCC J24 VCC P21 VCC D24 VCC K14 VCC P23 VCC E14 VCC K15 VCC P24 VCC E15 VCC K17 VCC P26 VCC E17 VCC K18 VCC R12 VCC E18
Processor Ball and Package Information Signal Ball Signal Ball Signal Ball VCC U24 VCC AA26 VCCIO Y29 VCC U26 VCC_SENSE M26 VCCIO Y30 VCC V12 VCCIO M11 VCCIO AA1 VCC V14 VCCIO M12 VCCIO AA2 VCC V15 VCCIO N8 VCCIO AA3 VCC V17 VCCIO N10 VCCIO AA4 VCC V18 VCCIO N28 VCCIO AA5 VCC V20 VCCIO N29 VCCIO AA6 VCC V21 VCCIO P28 VCCIO AA7 VCC V23 VCCIO P29 VCCIO AA28 VCC V24 VCCIO R7 VCCIO AA29 VCC V26 VCCIO R8 VCCIO AA30 VCC W12 VCCIO R2
Processor Ball and Package Information Signal Ball Signal Ball Signal Ball VCCIO AC19 VDDQ AD17 VDDQ AT17 VCCIO AC20 VDDQ AD18 VDDQ AT20 VCCIO AC21 VDDQ AD21 VDDQ AT23 VCCIO AC22 VDDQ AD25 VDDQ AT25 VCCIO AC23 VDDQ AE15 VDDQ AT26 VCCIO AC24 VDDQ AE16 VIDALERT# E31 VCCIO AC25 VDDQ AE17 VIDSCLK E29 VCCIO AC26 VDDQ AE18 VIDSOUT G26 VCCIO AC27 VDDQ AE19 VSS A3 VCCIO AC28 VDDQ AE20 VSS A4 VCCIO AC29 VDDQ AE21 VSS A7 VCCIO AC30 VDDQ AE22
Processor Ball and Package Information Signal Ball Signal Ball Signal Ball VSS C22 VSS F22 VSS J32 VSS C25 VSS F25 VSS J34 VSS C29 VSS F29 VSS K1 VSS C30 VSS F31 VSS K4 VSS C34 VSS F34 VSS K7 VSS D1 VSS G4 VSS K10 VSS D4 VSS G5 VSS K13 VSS D7 VSS G7 VSS K16 VSS D13 VSS G10 VSS K19 VSS D16 VSS G13 VSS K22 VSS D19 VSS G16 VSS K25 VSS D22 VSS G19 VSS K27 VSS D25 VSS G22 VSS K29 VSS D27 VSS G25 VSS K31 VSS D31 VSS G27
Processor Ball and Package Information Signal Ball Signal Ball Signal Ball VSS N6 VSS T5 VSS W6 VSS N7 VSS T9 VSS W9 VSS N11 VSS T13 VSS W13 VSS N13 VSS T16 VSS W16 VSS N16 VSS T19 VSS W19 VSS N19 VSS T22 VSS W22 VSS N22 VSS T25 VSS W25 VSS N25 VSS T28 VSS W28 VSS N27 VSS T30 VSS W31 VSS N30 VSS T31 VSS Y10 VSS P2 VSS U3 VSS Y13 VSS P3 VSS U5 VSS Y16 VSS P4 VSS U6 VSS Y19 VSS P5 VSS U10 VSS Y22 VSS P8 VSS U11 VSS
Processor Ball and Package Information Signal Ball Signal Ball Signal Ball VSS AB19 VSS AE31 VSS AJ23 VSS AB22 VSS AE36 VSS AJ26 VSS AB25 VSS AF6 VSS AJ29 VSS AB31 VSS AF9 VSS AJ32 VSS AC6 VSS AF12 VSS AJ33 VSS AC31 VSS AF15 VSS AJ34 VSS AC32 VSS AF25 VSS AJ35 VSS AC33 VSS AF27 VSS AK6 VSS AC34 VSS AF28 VSS AK9 VSS AC35 VSS AF29 VSS AK12 VSS AC36 VSS AF32 VSS AK15 VSS AD6 VSS AF33 VSS AK29 VSS AD7 VSS AF34 VSS AK32 VSS AD8
Processor Ball and Package Information Signal Ball Signal Ball VSS AM30 VSS AR26 VSS AM33 VSS AR29 VSS AM34 VSS AR34 VSS AM35 VSS AR35 VSS AN1 VSS AT3 VSS AN6 VSS AT6 VSS AN9 VSS AT9 VSS AN12 VSS AT12 VSS AN15 VSS AT15 VSS AN17 VSS AT33 VSS AN20 VSS AT34 VSS AN23 VSS_SENSE M27 VSS AN26 VSS_SENSE_VCCIO AD29 VSS AN29 VSS AN30 VSS AN33 VSS AN36 VSS AP1 VSS AP2 VSS AP4 VSS AP5 VSS AP6 VSS AP9 VSS AP12 VSS AP15 VSS AP25 VSS AP30
Processor Ball and Package Information Figure 10-1.
Processor Ball and Package Information Figure 10-2.
Processor Ball and Package Information Figure 10-3.
Processor Ball and Package Information Figure 10-4.
Processor Ball and Package Information 10.2 Package Mechanical Information The following section contains the mechanical drawings for the processor. The processor utilizes a 37.5 x 37.5 mm, FC-BGA package. There are two versions of die available on this package — a 4-Core-die version and a 2-Core-die version. The processor SKUs and their corresponding die-type are provided in Table 5-1, “Base Features by SKU” on page 45.
Processor Ball and Package Information Figure 10-5.
Processor Ball and Package Information Figure 10-6.
Processor Ball and Package Information §§ May 2012 Document Number: 327405-001 Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 149
Processor Ball and Package Information Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 150 May 2012 Document Number: 327405-001
Processor Configuration Registers 11.0 Processor Configuration Registers This section contains register information that is specific to the Intel® Xeon®, Intel® Core™, Intel® Pentium® and Intel® Celeron® Processors for Communications Infrastructure. For other register details see the latest version of the 2nd Generation Intel® Core™ Processor Family Mobile Datasheet – Volume 2. Note: The processor does not include the Integrated Display Engine or the Graphics Processor Unit (GPU).
Processor Configuration Registers Table 11-2. Register Terminology Attribute Modifier Attribute Modifier Applicable Attribute Description RO (with -V) Sticky: These bits are only re-initialized to their default value by a Power Good Reset. Note: Does not apply to RO (constant) bits. RW S RW1C RW1S -K Key: These bits control the ability to write other bits (identified with a Lock modifier). RW RW -L Lock: Hardware can make these bits Read-Only via a separate configuration bit or other logic.
Processor Configuration Registers Table 11-3. Error Status Register (Sheet 2 of 2) Bit 1 0 11.2 Access RW1C-S RW1C-S Default Value 0b 0b RST/ PWR Description Powergood Multiple-bit DRAM ECC Error Flag (DMERR): If this bit is set to 1, a memory read data transfer had an uncorrectable multiple-bit error. When this bit is set, the column, row, bank, and rank that caused the error, and the error syndrome, are logged in the ECC Error Log register in the channel where the error occurred.
Processor Configuration Registers Table 11-4. Error Command Registers Bit Access Default Value 15:2 RO 0h Reserved (RSVD) 0b Uncore SERR Multiple-Bit DRAM ECC Error (DMERR): 1 = The Host Bridge generates an SERR message over DMI when it detects a multiple-bit error reported by the DRAM controller. 0 = Reporting of this condition via SERR messaging is disabled. For systems not supporting ECC, this bit must be disabled.
Processor Configuration Registers 11.4 SCICMD - SCI Command B/D/F/Type: 0/0/0/PCI Address Offset: CE-CFh Default Value: 0000h Access: RO; RW Size: 16 bits BIOS Optimal Default 0000h This register enables various errors to generate an SCI DMI special cycle. When an error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively. One and only one message type can be enabled. Table 11-6.
Processor Configuration Registers Once the error flag bits are set as a result of an error, this bit field is locked and doesn't change as a result of a new error until the error flag is cleared by software. Same is the case with error syndrome field. Table 11-7. Channel 0 ECC Error Log 0 Bit Access Default Value RST/ PWR 31:29 ROS-V 000b Powergood Error Bank Address (ERRBANK): This field holds the Bank Address of the read transaction that had the ECC error.
Processor Configuration Registers Table 11-8. Channel 0 ECC Error Log 1 11.7 Bit Access Default Value RST/ PWR Description 31:16 ROS-V 0000h Powergood Error Column (ERRCOL): This field holds the DRAM column address of the read transaction that had the ECC error. 15:0 ROS-V 0000h Powergood Error Row (ERRROW): This field holds the DRAM row (page) address of the read transaction that had the ECC error.
Processor Configuration Registers Table 11-9. Channel 1 ECC Error Log 0 (Sheet 2 of 2) Bit 1 0 11.8 Access RO-P RO-P Default Value 0b 0b RST/ PWR Description Powergood Multiple Bit Error Status (MERRSTS): This bit is set when an uncorrectable multiple-bit error occurs on a memory read data transfer. When this bit is set, the address that caused the error and the error syndrome are also logged and they are locked until this bit is cleared. This bit is cleared when the corresponding bit in 0.0.
Processor Configuration Registers Size: 32 bits BIOS Optimal Default 00h This register defines channel characteristics - number of DIMMs, number of ranks, size, ECC, interleave options and ECC options. Table 11-11.
Processor Configuration Registers 11.10 MAD_DIMM_CH1 - Address Decode Channel 1 B/D/F/Type: 0/0/0/MCHBAR_MCMAIN Address Offset: 5008-500Bh Default Value: 00600000h Access: RW-L Size: 32 bits BIOS Optimal Default 00h This register defines channel characteristics - number of DIMMs, number of ranks, size, ECC, interleave options and ECC options. Table 11-12.
Processor Configuration Registers Table 11-12.
Processor Configuration Registers Table 11-13.
Processor Configuration Registers Table 11-13.
Processor Configuration Registers Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure Datasheet - Volume 1 of 2 164 May 2012 Document Number: 327405-001
