Intel® Atom™ Processor Z6xx Series Datasheet For the Intel® Atom™ Processor Z670 on 45-nm Process Technology April 2011 Revision 001 Document Number: 325310-001
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Contents 1 Introduction ................................................................................................... 6 1.1 1.2 1.3 1.4 2 Display Controller .......................................................................7 1.2.3 cDMI .........................................................................................7 1.2.4 cDVO ........................................................................................8 1.2.5 LVDS .....................................................
6 Package Mechanical Specifications and Pin Information ............................... 37 6.1 6.2 Package Mechanical Specifications ........................................................... 37 Processor Pinout Assignment ................................................................... 39 Figures Figure 3-1. Thread Low Power States .................................................................. 19 Figure 3-2. Package Low Power States ...............................................................
Revision History Document Number Revision Number 325314 001 Description Revision Date April 2011 • Initial release.
Introduction 1 Introduction The datasheet describes the architecture, features, buffers, signal descriptions, power management, pin states, operating parameters, and specifications for the Intel® Atom™ Processor Z670 (Core Processor and North Complex). Intel® Atom™ Processor Z670 is the next generation low power IA-32 processor that is based on the new re-partitioning architecture targeted for tablets and sleek netbooks.
Introduction 1.2 Interfaces 1.2.1 System Memory Support 1.2.
Introduction 1.2.4 1.2.5 1.3 cDVO • Peak raw BW of 800MT/s • Supports low power management schemes • Supports AGTL+ interface LVDS • Maximum resolution (internal display) of: • 1366 x 768 @ 18 bpp and 60 fps • Dot clock range from 20–83 MHz • Four differential signal pairs: Three data pairs (up to 581 Mbps on each data link) and one clock pair • Supports 18 bpp packed and 18 bpp loosely packed pixel formats • Supports 24 bpp with a limited number of validated panels.
Introduction Acronym 1.4 Description LVDS Low Voltage Differential Signaling, a high speed, low power data transmission standard used for display connections to LCD panels MSR Model-specific register NCTF Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved, so the loss of solder joint continuity at end of life conditions will not affect the overall product functionality.
Introduction Document Location/ Comments Intel® 64 and IA-32 Architectures Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M http://www.intel.com /products/processor/ manuals/index.htm Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide NOTES: 1. Contact your Intel representative for the latest revision and document number of this document.
Signal Descriptions 2 Signal Descriptions This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type. Table 2-1. Signal Types Notations Signal Type I Input Pin O Output Pin I/O Bi-directional Input/Output Pin Table 2-2.
Signal Descriptions Signal Direction Type SM_SREN# I CMOS1.8 Self-refresh enable: Signal from the chipset asserted after processor places DDR in self-refresh. SM_CKE[1:0] O CMOS1.8 Clock enable: SM_CKE is used for power control of the DRAM devices. There is one SM_CKE per rank. SM_CS[1:0]# O CMOS1.8 Chip select: These signals determine whether a command is valid in a given cycle for the devices connected to it. There is one chip select signal for each rank. SM_RAS# O CMOS1.
Signal Descriptions 2.1.2 cDMI Interface Table 2-4. cDMI Interface Signal Signal 2.1.3 Direction Type Description CDMI_RCOMP[1:0] I Analog CDMI_RCOMP: Connected to high-precision resistors on the motherboard. Used for compensating cDMI pull-up/pulldown impedances. CDMI_TX[7:0] O CMOS Data output: quad-pump (strobed) data bus from Processor to PCH.
Signal Descriptions Signal 2.1.4 Direction Type Description CDVO_STALL# I AGTL+ Stall: Allows PCH to throttle the sending of display data. CDVO_TXDPWR# O AGTL+ Line wakeup for output: When asserted, the PCH will power-up its receivers on CDVO_TX[5:0] and CDVO_TXSTB_ODD#. CDVO_TXSTB_ODD#, CDVO_TXSTB_EVEN# O AGTL+ Data strobe output: Strobes for CDVO_TX[5:0]. CDVO_VBLANK# I AGTL+ Vertical blank: Indication from PCH indicating the start of the vertical blank period.
Signal Descriptions 2.1.5 LGI/LGIe (Legacy) Signals Table 2-7. LGI/LGIe Legacy Signals Signal VID[6:0] Direction Type O CMOS Description Voltage ID: Connects to PMIC. Indicates a desired voltage for either VCC or VNN depending on the VIDEN[] pins. Resolution of 12.5 mV. Voltage ID enable: Connects to PMIC.
Signal Descriptions Signal 2.1.6 Direction Type Description PWRMODE[2:0] I CMOS Power mode: The chipset is expected to sequence Processor through various states using the POWERMODE[] pins to facilitate cold reset, and warm reset. BCLK_P/N I CMOS Reference clock: Differential 100 MHz. Debug and Miscellaneous Signals Table 2-8. Debug and Miscellaneous Signals Signal Direction Type Description BPM[3:0]# I/O AGTL+ Break/perf monitor: Various debug input and output functions.
Signal Descriptions 2.1.7 Power Signals Table 2-9. Power Signals Signal Type Description VCC PWR Processor core supply voltage: Power supply is required for processor cycles. VNN PWR North Complex logic and graphics supply voltage. VCCP PWR cDMI, cDVO, LGI, LGIe, JTAG, RCOMP, and power gating supply voltage. Needed for most bus accesses. Cannot be connected to VCCPAOAC during Standby or Self-Refresh states. VCCPDDR PWR DDR DLL and logic supply voltage: Required for memory bus accesses.
Power Management 3 Power Management Processor supports fine grain power management by having several partitions of voltage islands created through on-die power switches. The Intel® Smart Power Technology (Intel® SPT) software determines the most power efficient state for the platform at any given point in time and then provides guidance to turn ON or OFF different voltage islands on processor.
Power Management Figure 3-1.
Power Management 3.1.1 Cx State Definitions • C0 State—Full On This is the only state that runs software. All clocks are running and the processor core is active. The processor can service snoops and maintain cache coherency in this state. All power management for interfaces, clock gating, are controlled at the unit level. • C1 State—Auto-Halt The first level of power reduction occurs when the core processor executes an Auto-Halt instruction.
Power Management • C4E The C4E state is essentially the same as the C4 state except that the core processor will transition to the Low Frequency Mode (LFM) frequency and voltage upon entry and exit of this state. • C6—Deep Power Down Prior to entering the C6 state, the core processor will flush its cache and save its core context to a special on-die SRAM on a different power plane. Once the C6 entry sequence has completed, the core processor's voltage can be completely shut off.
Electrical Specifications 4 Electrical Specifications This chapter contains signal group descriptions, absolute maximum ratings, voltage identification and power sequencing. This chapter also includes DC specifications. 4.1 Power and Ground Balls The processor has Vcc and Vss (ground) inputs for on-chip power distribution. All power balls must be connected to their respective processor power planes, while all Vss balls must be connected to the system ground plane.
Electrical Specifications 4.4 Voltage Identification (VID) The VCC and VNN voltage inputs use two encoding pins (VIDEN[1:0]) to enable the VID pin inputs and seven voltage identification pins (VID[6:0]) to select the power supply voltage. The VID/VIDEN pins for the processor are CMOS outputs driven by the processor VID circuitry. Table 4-2 specifies the voltage level corresponding to the state of VID[6:0]. A “1” in this refers to a high-voltage level and a “0” refers to a low-voltage level.
Electrical Specifications 4.4.2 VID Table Note: 1. Processor will not support the entire range of the voltages listed in the VID table (grayed out). 2. VID codes below 0.3 V are not supported for VCC. Table 4-2. VID Table VID[6:0] VCC /VNN VID[6:0] VCC /VNN VID[6:0] VCC /VNN VID[6:0] VCC /VNN 00h 1.5000V 20h 1.1000V 40h 0.7000V 60h 0.3000V 01h 1.4875V 21h 1.0875V 41h 0.6875V 61h 0.2875V 02h 1.4750V 22h 1.0750V 42h 0.6750V 62h 0.2750V 03h 1.4625V 23h 1.0625V 43h 0.
Electrical Specifications VID[6:0] VCC /VNN VID[6:0] VCC /VNN VID[6:0] VCC /VNN VID[6:0] VCC /VNN 1Ch 1.1500V 3Ch 0.7500V 5Ch 0.3500V 7Ch 0.0000V 1Dh 1.1375V 3Dh 0.7375V 5Dh 0.3375V 7Dh 0.0000V 1Eh 1.1250V 3Eh 0.7250V 5Eh 0.3250V 7Eh 0.0000V 1Fh 1.1125V 3Fh 0.7125V 5Fh 0.3125V 7Fh 0.0000V 4.5 Absolute Maximum Ratings Table 4-3 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected.
Electrical Specifications Symbol Parameter Minimum Maximum Unit Note VCCD180 1.8-V LVDS I/O supply voltage -0.3 1.9 V VCC180SR 1.8-V DDR2 self-refresh supply voltage -0.4 1.9 V VCC180 1.8-V DDR2 I/O supply voltage -0.4 1.9 V TJ Operational junction temperature 0 90 °C 1,2 The ambient storage temperature limit (in shipping media) for a sustained period of time.
Electrical Specifications Symbol Parameter VCCPAOAC VCCPAOAC supply voltage VMM VMM supply voltage LVD_VBG VCCA LVDS band gap reference voltage VCCA supply voltage Min. Typ. Max. Unit 0.9975 1.05 1.1025 V 1.14 1.20 1.26 V 1.225 1.25 1.275 V 1.47 1.5 1.53 V VCCA180 VCCA180 supply voltage 1.746 1.8 1.854 V VCCD180 VCCD180 supply voltage 1.71 1.8 1.89 V VCC180SR VCC180SR supply voltage 1.71 1.8 1.89 V VCC180 supply voltage 1.71 1.8 1.
Electrical Specifications 8. 9. This is the sum of current on both rails. Specification based on LVDS panel configuration of 1024x600 resolution, 60Hz refresh rate, and 18bpp color depth. Table 4-5. Differential Clock DC Specifications Symbol Parameter Min. Typ. Max. Unit Notes Differential Clock (BCLK) VIH Input high voltage − − 1.15 V VIL Input low voltage − − -0.3 V VCROSS Crossing voltage 0.3 − 0.
Electrical Specifications NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Unless otherwise noted, all specifications in this table apply to all processor frequencies. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. VIH and VOH may experience excursions above VCCP.
Electrical Specifications Symbol Parameter Min. Typ. Max. Unit ∆VOD Change in differential output voltage − − 50 mV ISC Short-circuit current − − 12 mA ISCC Short-circuit comment current − − 24 mA IL Leakage current -380 150 380 µA Dynamic offset − − 150 mV Overshoot 50 70 90 mV Ringback 50 70 90 mV Notes NOTE: Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Table 4-3. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. Maintaining the proper thermal environment is the key to reliable, long-term system operation.
Thermal Specifications and Design Considerations 3. 4. 5.1 Scenario Power examines a common use case and may be more indicative of a more common power usage level as compared with the TDP. Measurement configuration assumes: LCD brightness 100nits, LCD 1024x800 10.1”, USB touch panel, I2C sensors, SDIO WiFi on, 2GB DDR2, 73% PMIC efficiency, 93% discrete VR efficiency, Flash* v10.2. 720p, YouTube*.
Thermal Specifications and Design Considerations When the TM1 mode is enabled and a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50 percent duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive.
Thermal Specifications and Design Considerations An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSRs, and one I/O pin (PROCHOT#).
Thermal Specifications and Design Considerations Unlike traditional thermal devices, the DTS outputs a temperature relative to the maximum supported operating temperature of the processor (TJ_max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the DTS will always be at or below TJ_max. Catastrophic temperature conditions are detectable using an Out of Specification status bit. This bit is also part of the DTS MSR.
Thermal Specifications and Design Considerations PROCHOT#. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from overheating situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC.
Package Mechanical Specifications and Pin Information 6 Package Mechanical Specifications and Pin Information This chapter describes the package specifications and pinout assignments. 6.1 Package Mechanical Specifications The processor will be available in a 518 pin FCMB3 package. The package dimensions are shown in Figure 6-1.
Package Mechanical Specifications and Pin Information Figure 6-1.
Package Mechanical Specifications and Pin Information 6.2 Processor Pinout Assignment Table 6-1, Table 6-2 and Table 6-3 are graphic representations of the processor pinout assignments. Table 6-4 lists the pinout by signal name.
Package Mechanical Specifications and Pin Information Table 6-1.
Package Mechanical Specifications and Pin Information Table 6-2.
Package Mechanical Specifications and Pin Information Table 6-3.
Package Mechanical Specifications and Pin Information Table 6-4.
Package Mechanical Specifications and Pin Information 44 Pin Name Pin # Pin Name Pin # Pin Name Pin # SM_DQ11 A29 SM_MA2 F28 RSVD AG2 SM_DQ12 B25 SM_MA3 D25 RSVD AG4 SM_DQ13 A24 SM_MA4 D29 RSVD AH7 SM_DQ14 B24 SM_MA5 A16 THERMTRIP# AE4 SM_DQ15 A23 SM_MA6 B18 TMS J2 SM_DQ16 A6 SM_MA7 D24 TRST# J1 SM_DQ17 B7 SM_MA8 D22 VCC AA10 SM_DQ18 A4 SM_MA9 A20 VCC AA12 SM_DQ19 B5 SM_MA10 A26 VCC AA14 SM_DQ2 G30 SM_MA11 B15 VCC AA16 SM_DQ20 C1 SM_MA12
Package Mechanical Specifications and Pin Information Datasheet Pin Name Pin # Pin Name Pin # Pin Name Pin # VCC W12 VCCA T6 VID0 AH2 VCC W14 VCCA180 AD24 VID1 AJ1 VCC W16 VCCA180 AF24 VID2 AH4 VCC W18 VCCD180 AD26 VID3 AH3 VCC W2 VCCD180 AF26 VID4 AK2 VCC W20 VCCP K7 VID5 AH6 VCC W22 VCCP AC28 VID6 AL2 VCC W24 VCCP AC5 VIDEN0 AD4 VCC W3 VCCP AD10 VIDEN1 AD1 VCC W4 VCCP AD14 RSVD9 AA24 VCC W7 VCCP AD16 VNN AA26 VCC W8 VCCP AD20 VN
Package Mechanical Specifications and Pin Information 46 Pin Name Pin # Pin Name Pin # Pin Name Pin # VNN P30 VSS AC30 VSS AJ2 VNN R10 VSS AD29 VSS AJ21 VNN R12 VSS AD3 VSS AJ22 VNN R14 VSS AD31 VSS AJ24 VNN R16 VSS AE11 VSS AJ25 VNN R18 VSS AE13 VSS AJ27 VNN R20 VSS AE15 VSS AJ29 VNN R22 VSS AE17 VSS AJ4 VNN R24 VSS AE19 VSS AJ5 VNN R26 VSS AE21 VSS AJ7 VNN R29 VSS AE23 VSS AJ8 VNN R31 VSS AE25 VSS AJ9 VNN R7 VSS AE29 VSS
Package Mechanical Specifications and Pin Information Datasheet Pin Name Pin # Pin Name Pin # Pin Name Pin # VSS D3 VSS K25 VSS T23 VSS E12 VSS K3 VSS T28 VSS E14 VSS K9 VSS T8 VSS E18 VSS M11 VSS T9 VSS E20 VSS M13 VSS V11 VSS E24 VSS M15 VSS V13 VSS E26 VSS M17 VSS V15 VSS E29 VSS M19 VSS V17 VSS E6 VSS M21 VSS V19 VSS E8 VSS M23 VSS V2 VSS F3 VSS M3 VSS V21 VSS G11 VSS M8 VSS V23 VSS G13 VSS M9 VSS V29 VSS G15 VSS N3
