Datasheet
Table Of Contents
- Intel® Desktop Boards D915GEV/D915GRF Technical Product Specification
- Revision History / Disclaimer
- Preface
- Contents
- 1 Product Description
- 1.1 PCI Bus Terminology Change
- 1.2 Overview
- 1.3 Online Support
- 1.4 Processor
- 1.5 System Memory
- 1.6 Intel® 915G Chipset
- 1.7 PCI Express Connectors
- 1.8 I/O Controller
- 1.9 Audio Subsystem
- 1.10 LAN Subsystem
- 1.11 Hardware Management Subsystem
- 1.12 Power Management
- 1.12.1 ACPI
- 1.12.2 Hardware Support
- 1.12.2.1 Power Connector
- 1.12.2.2 Fan Connectors
- 1.12.2.3 LAN Wake Capabilities
- 1.12.2.4 Instantly Available PC Technology
- 1.12.2.5 Resume on Ring
- 1.12.2.6 Wake from USB
- 1.12.2.7 Wake from PS/2 Devices
- 1.12.2.8 PME# Signal Wake-up Support
- 1.12.2.9 WAKE# Signal Wake-up Support
- 1.12.2.10 +5 V Standby Power Indicator LED
- 1.13 Trusted Platform Module
- 1.13.1 System Requirements
- 1.13.2 Warning of Potential Data Loss
- 1.13.3 Security Precautions
- 1.13.4 Trusted Platform Module Ownership
- 1.13.5 Enabling the Trusted Platform Module
- 1.13.6 Assuming Trusted Platform Module Ownership
- 1.13.7 Recovery Procedures
- 1.13.8 Clearing Trusted Platform Module Ownership
- 1.13.9 Software Support
- 2 Technical Reference
- 2.1 Introduction
- 2.2 Memory Resources
- 2.3 DMA Channels
- 2.4 Fixed I/O Map
- 2.5 PCI Configuration Space Map
- 2.6 Interrupts
- 2.7 PCI Conventional Interrupt Routing Map
- 2.8 Connectors
- 2.8.1 Back Panel Connectors
- 2.8.2 Component-side Connectors
- 2.9 Jumper Block
- 2.10 Mechanical Considerations
- 2.11 Electrical Considerations
- 2.12 Thermal Considerations
- 2.13 Reliability
- 2.14 Environmental
- 2.15 Regulatory Compliance
- 3 Overview of BIOS Features
- 4 Error Messages and Beep Codes
Product Description
25
1.6.1.4 Configuration Modes
A list of supported modes for the Intel GMA900 graphics controller is available as a downloadable
document.
For information about Refer to
Supported modes for the D915GEV board http://www.intel.com/design/motherbd/ev/ev_prdoc.htm
Supported modes for the D915GRF board http://www.intel.com/design/motherbd/rf/rf_prdoc.htm
1.6.2 USB
The boards support up to eight USB 2.0 ports, supports UHCI and EHCI, and uses UHCI- and
EHCI-compatible drivers.
The ICH6 provides the USB controller for all ports. The port arrangement is as follows:
•
Four ports are implemented with dual stacked back panel connectors adjacent to the audio
connectors
•
Four ports are routed to two separate front panel USB connectors
✏
NOTE
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device is attached to the cable. Use shielded cable that meets the
requirements for full-speed devices.
For information about Refer to
The location of the USB connectors on the back panel Figure 16, page 60
The location of the front panel USB connectors Figure 17, page 62
1.6.3 IDE Support
The board provides five IDE interface connectors:
• One parallel ATA IDE connector that supports two devices
• Four serial ATA IDE connectors that support one device per connector
1.6.3.1 Parallel ATE IDE Interface
The ICH6’s Parallel ATA IDE controller has one bus-mastering Parallel ATA IDE interface. The
Parallel ATA IDE interface supports the following modes:
• Programmed I/O (PIO): processor controls data transfer.
• 8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec.
• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
• ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
• ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH6’s ATA-100
logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 88 MB/sec.