Datasheet
Table Of Contents
- Intel® Desktop Boards D915GEV/D915GRF Technical Product Specification
- Revision History / Disclaimer
- Preface
- Contents
- 1 Product Description
- 1.1 PCI Bus Terminology Change
- 1.2 Overview
- 1.3 Online Support
- 1.4 Processor
- 1.5 System Memory
- 1.6 Intel® 915G Chipset
- 1.7 PCI Express Connectors
- 1.8 I/O Controller
- 1.9 Audio Subsystem
- 1.10 LAN Subsystem
- 1.11 Hardware Management Subsystem
- 1.12 Power Management
- 1.12.1 ACPI
- 1.12.2 Hardware Support
- 1.12.2.1 Power Connector
- 1.12.2.2 Fan Connectors
- 1.12.2.3 LAN Wake Capabilities
- 1.12.2.4 Instantly Available PC Technology
- 1.12.2.5 Resume on Ring
- 1.12.2.6 Wake from USB
- 1.12.2.7 Wake from PS/2 Devices
- 1.12.2.8 PME# Signal Wake-up Support
- 1.12.2.9 WAKE# Signal Wake-up Support
- 1.12.2.10 +5 V Standby Power Indicator LED
- 1.13 Trusted Platform Module
- 1.13.1 System Requirements
- 1.13.2 Warning of Potential Data Loss
- 1.13.3 Security Precautions
- 1.13.4 Trusted Platform Module Ownership
- 1.13.5 Enabling the Trusted Platform Module
- 1.13.6 Assuming Trusted Platform Module Ownership
- 1.13.7 Recovery Procedures
- 1.13.8 Clearing Trusted Platform Module Ownership
- 1.13.9 Software Support
- 2 Technical Reference
- 2.1 Introduction
- 2.2 Memory Resources
- 2.3 DMA Channels
- 2.4 Fixed I/O Map
- 2.5 PCI Configuration Space Map
- 2.6 Interrupts
- 2.7 PCI Conventional Interrupt Routing Map
- 2.8 Connectors
- 2.8.1 Back Panel Connectors
- 2.8.2 Component-side Connectors
- 2.9 Jumper Block
- 2.10 Mechanical Considerations
- 2.11 Electrical Considerations
- 2.12 Thermal Considerations
- 2.13 Reliability
- 2.14 Environmental
- 2.15 Regulatory Compliance
- 3 Overview of BIOS Features
- 4 Error Messages and Beep Codes
51
2 Technical Reference
What This Chapter Contains
2.1 Introduction ................................................................................................................51
2.2 Memory Resources ....................................................................................................51
2.3 DMA Channels ...........................................................................................................53
2.4 Fixed I/O Map.............................................................................................................54
2.5 PCI Configuration Space Map ....................................................................................55
2.6 Interrupts ....................................................................................................................56
2.7 PCI Conventional Interrupt Routing Map ....................................................................57
2.8 Connectors.................................................................................................................59
2.9 Jumper Block .............................................................................................................71
2.10 Mechanical Considerations.........................................................................................72
2.11 Electrical Considerations ............................................................................................74
2.12 Thermal Considerations .............................................................................................76
2.13 Reliability....................................................................................................................78
2.14 Environmental ............................................................................................................79
2.15 Regulatory Compliance ..............................................................................................80
2.1 Introduction
Sections 2.2 - 2.6 contain several standalone tables. Table 10 describes the system memory map,
Table 11 lists the DMA channels, Table 12 shows the I/O map, Table 13 defines the PCI
Conventional bus configuration space map, and Table 14 describes the interrupts. The remaining
sections in this chapter are introduced by text found with their respective section headings.
2.2 Memory Resources
2.2.1 Addressable Memory
The board utilizes 4 GB of addressable system memory. Typically the address space that is
allocated for PCI Conventional bus add-in cards, PCI Express configuration space, BIOS
(firmware hub), and chipset overhead resides above the top of DRAM (total system memory). On
a system that has 4 GB of system memory installed, it is not possible to use all of the installed
memory due to system address space being allocated for other system critical functions. These
functions include the following:
• BIOS/firmware hub (2 MB)
• Local APIC (19 MB)
• Digital Media Interface (40 MB)
• Front side bus interrupts (17 MB)
• PCI Express configuration space (256 MB)
• MCH base address registers, internal graphics ranges, PCI Express ports (up to 512 MB)