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02_TOCHead - Contents

Mobile Intel



Pentium



Processor-M

Datasheet

June 2003

Order Number: 250686-007

Summary of content (97 pages)

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Mobile Intel Pentium 4 Processor-M Datasheet June 2003 Order Number: 250686-007
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Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel.
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Contents 1. Introduction......................................................................................................................... 9 1.1 1.2 2. Electrical Specifications.................................................................................................... 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 3. 3.2 3.3 Processor Pin-Out ...............................................................................................
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Mobile Intel Pentium 4 Processor-M 6.1.1 6.1.2 7. Configuration and Low Power Features........................................................................... 93 7.1 7.2 7.3 8. Power-On Configuration Options ........................................................................ 93 Clock Control and Low Power States.................................................................. 93 7.2.1 Normal State .......................................................................................... 93 7.
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Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 VCCVID Pin Voltage and Current Requirements ................................................ 15 Typical VCCIOPLL, VCCA and VSSA Power Distribution .................................. 17 Phase Lock Loop (PLL) Filter Requirements ..................................................... 18 Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)....................
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Mobile Intel Pentium 4 Processor-M Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 6 References.......................................................................................................... 11 Core Frequency to System Bus Multipliers ......................................................... 14 Voltage Identification Definition...........................................................................
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40 41 Thermal Diode Specifications.............................................................................. 90 Power-On Configuration Option Pins ..................................................................
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Mobile Intel Pentium 4 Processor-M Revision History Date Description March 2002 001 Initial release of the Datasheet April 2002 002 Updates include: June 2002 September 2002 January 2003 April 2003 June 2003 8 Revision 003 004 005 006 007 • Added new processor speeds: 1.4 GHz, 1.5 GHz, & 1.8 GHz • Added PROCHOT# signal in Table 21 • Updated signal description for PROCHOT# in Table 37 and Section 6.1.
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Introduction 1. Introduction The Mobile Intel Pentium 4 Processor-M is the first Intel mobile processor with the Intel NetBurstTM micro-architecture. The Mobile Intel Pentium 4 Processor-M utilizes a 478-pin, Micro Flip-Chip Pin Grid Array (Micro-FCPGA) package, and plugs into a surface-mount, Zero Insertion Force (ZIF) socket. The Mobile Intel Pentium 4 Processor-M maintains full compatibility with IA32 software.
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Introduction The processor system bus uses a variant of GTL+ signalling technology called Assisted Gunning Transceiver Logic (AGTL+) signal technology. The Mobile Intel Pentium 4 Processor-M is available at the following core frequencies: • 2.6 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 2.5 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V) • 2.
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Introduction 1.1 Terminology A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted.
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Electrical Specifications 2. Electrical Specifications 2.1 System Bus and GTLREF Most Mobile Intel Pentium 4 Processor-M system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signalling technology. As with the Intel P6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low-voltage swings and controlled edge rates.
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Electrical Specifications affect the long term reliability of the processor. For further information and design guidelines, refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. 2.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket.
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Electrical Specifications 2. Listed frequencies are not necessarily committed production frequencies. The Mobile Intel Pentium 4 Processor-M uses a differential clocking implementation. For more information on Mobile Intel Pentium 4 Processor-M clocking. 2.4 Voltage Identification and Power Sequencing The voltage set by the VID pins is the nominal/typical voltage setting for the processor. A minimum voltage is provided in Table 7 and changes with frequency.
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Electrical Specifications Table 3. Voltage Identification Definition Processor Pins 2.4.1 VID4 VID3 VID2 VID1 VID0 VCC_ 1 1 1 1 1 0.600 1 1 1 1 0 0.625 1 1 1 0 1 0.650 1 1 1 0 0 0.675 1 1 0 1 1 0.700 1 1 0 1 0 0.725 1 1 0 0 1 0.750 1 1 0 0 0 0.775 1 0 1 1 1 0.800 1 0 1 1 0 0.825 1 0 1 0 1 0.850 1 0 1 0 0 0.875 1 0 0 1 1 0.900 1 0 0 1 0 0.925 1 0 0 0 1 0.950 1 0 0 0 0 0.975 0 1 1 1 1 1.
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Electrical Specifications processor to the Battery Optimized mode. INIT# assertions ("soft" resets) and APIC bus INIT messages do not change the operating mode of the processor. Some electrical and thermal specifications are for a specific voltage and frequency.
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Electrical Specifications . Figure 3. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB -0.5 dB forbidden zone -28 dB forbidden zone -34 dB DC 1 Hz fpeak 1 MHz 66 MHz fcore high frequency band passband NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. 2.4.
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Electrical Specifications For reliable operation, always connect unused inputs or bidirectional signals that are not terminated on the die to an appropriate signal level. Note that on-die termination has been included on the Mobile Intel Pentium 4 Processor-M to allow signals to be terminated within the processor silicon. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon.
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Electrical Specifications 2.6 System Bus Signal Groups In order to simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
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Electrical Specifications Table 4.
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Electrical Specifications 2.7 Asynchronous GTL+ Signals Mobile Intel Pentium 4 Processor-M does not utilize CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL+ input buffers. Legacy output FERR#/PBE# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) use GTL+ output buffers.
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Electrical Specifications 2.10 Maximum Ratings Table 6 lists the processor’s maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
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Electrical Specifications Table 7. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes1 V 2, 3, 4, 5, 7, 8,11 VCC VCC for core logic Maximum Performance Mode Battery Optimized Mode VCCVID VID supply voltage -5% 1.2 +10% V 2, 12 VCCDPRSLP Transient Deeper Sleep voltage 0.91 1.00 1.09 V 2 VCCDPRSLP,DC Static Deeper Sleep voltage 0.95 1.00 1.05 V 2 A 4, 5, 8, 9 1.3 1.2 Current for VCC at core frequency 2.60 GHz & 1.3 V 2.50 GHz & 1.3 V 2.40 GHz & 1.
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Electrical Specifications 10.The specification is defined per PLL pin. 11.The voltage response to a processor current load step (transient) must stay within the Transient Voltage Tolerance Window. The voltage surge or droop response measured in this window is typically on the order of several hundred nanoseconds to several microseconds. The Transient Voltage Tolerance Window is defined as follows: Case a) Load Current Step Up: e.g., from Icc = I_leakage to Icc = Icc_max.
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Electrical Specifications Table 8. IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode (Maximum Performance Mode) ICC (A) VCC Nominal (V) VCC Static Min (V) VCC Static Max (V) VCC Transient Min (V) VCC Transient Max (V) 25.0 1.250 1.225 1.275 1.205 1.295 26.0 1.248 1.223 1.273 1.203 1.293 27.0 1.246 1.221 1.271 1.201 1.291 28.0 1.244 1.219 1.269 1.199 1.289 29.0 1.242 1.217 1.267 1.197 1.287 30.0 1.240 1.215 1.265 1.195 1.285 31.0 1.238 1.
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Electrical Specifications Table 9. IMVP-III Voltage Regulator Tolerances for VID = 1.20 V Operating Mode (Battery Optimized Mode) ICC (A) VCC Nominal (V) VCC Static Min (V) VCC Static Max (V) VCC Transient Min (V) VCC Transient Max (V) 0.0 1.176 1.151 1.201 1.131 1.221 1.0 1.174 1.149 1.199 1.129 1.219 2.0 1.172 1.147 1.197 1.127 1.217 3.0 1.170 1.145 1.195 1.125 1.215 4.0 1.168 1.143 1.193 1.123 1.213 5.0 1.166 1.141 1.191 1.121 1.211 6.0 1.164 1.139 1.189 1.
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Electrical Specifications Figure 5. Illustration of VCC Static and Transient Tolerances (VID = 1.20 V) Mobile Northwood Load Line for VID = 1.20V 1.250 Vcc Transient Maximum Vcc Static Maximum 1.200 Vcc Nominal VCC 1.150 1.100 Vcc Static Minimum Vcc Transient Minimum 1.050 0. 0 1. 0 2. 0 3. 0 4. 0 5. 0 6. 0 7. 0 8. 0 9. 0 10 .0 11 .0 12 .0 13 .0 14 .0 15 .0 16 .0 17 .0 18 .0 19 .0 20 .0 21 .0 22 .0 23 .0 24 .0 25 .0 1.000 ICC Maximum Table 10.
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Electrical Specifications Table 11. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Battery Optimized Mode (VID = 1.20 V, VID Offset = 4.62%) ICC (A) VCC Nominal (V) VCC Static Min (V) VCC Static Max (V) VCC Transient Min (V) VCC Transient Max (V) 0.0 1.145 1.120 1.170 1.100 1.190 1.0 1.143 1.118 1.168 1.098 1.188 2.0 1.141 1.116 1.166 1.096 1.186 3.0 1.139 1.114 1.164 1.094 1.184 4.0 1.137 1.112 1.162 1.092 1.182 5.0 1.135 1.110 1.160 1.090 1.180 6.
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Electrical Specifications Table 12. System Bus Differential BCLK Specifications Notes1 Symbol Parameter Min Typ Max Unit Figure VL Input Low Voltage -0.150 0.000 N/A V 10 VH Input High Voltage 0.660 0.710 0.850 V 10 VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 10, 11 2,3,8 VCROSS(rel) Relative Crossing Point V 10, 11 2,3,8,9 ∆VCROSS Range of Crossing Points N/A N/A 0.140 V 10, 11 2,10 VOV Overshoot N/A N/A VH + 0.3 V 10 4 VUS Undershoot -0.
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Electrical Specifications Table 13. AGTL+ Signal Group DC Specifications Notes1 Symbol Parameter Min Max Unit GTLREF Reference Voltage 2/3 Vcc - 2% 2/3 Vcc + 2% V VIH Input High Voltage 1.10*GTLREF VCC V 2,6 VIL Input Low Voltage 0.0 0.9*GTLREF V 3,4,6 VOH Output High Voltage N/A Vcc V 7 IOL Output Low Current N/A 50 mA 6 IHI Pin Leakage High N/A 100 µA 8 ILO Pin Leakage Low N/A 500 µA 9 RON Buffer On Resistance 7 11 Ω 5 NOTES: 1.
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Electrical Specifications Table 14. Asynchronous GTL+ Signal Group DC Specifications Symbol VIH VIL Unit Notes1 V 3, 4, 5 0.9*GTLREF V 5 Parameter Min Max Input High Voltage 1.10*GTLREF VCC 0 Asynch GTL+ Input Low Voltage Asynch. GTL+ VOH Output High Voltage N/A VCC V 2, 3, 4 IOL Output Low Current N/A 50 mA 6, 8 IHI Pin Leakage High N/A 100 µA 9 ILO Pin Leakage Low N/A 500 µA 10 7 11 Ω 5, 7 Ron Buffer On Resistance Asynch GTL+ NOTES: 1.
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Electrical Specifications Table 15.
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Electrical Specifications Figure 7. ITPCLKOUT[1:0] Output Buffer Diagram Vcc Ron To Debug Port Processor Package Rext NOTES: 1. See Table 16 for range of Ron. 2. The Vcc referred to in this figure is the instantaneous Vcc. 3. Refer to the appropriate platform design guidelines for the value of Rext. Table 17. BSEL [1:0] and VID[4:0] DC Specifications Symbol Parameter Min Max Unit Notes1 Ron (BSEL) Buffer On Resistance 9.2 14.3 Ω 2 Ron (VID) Buffer On Resistance 7.8 12.
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Electrical Specifications for the AGTL+ signal group traces is known and well-controlled. For more details on platform design see the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. Table 18. AGTL+ Bus Voltage Definitions Symbol Parameter Units Notes1 Min Typ Max 2/3 VCC -2% 2/3 VCC 2/3 VCC +2% V 2, 3, 6 GTLREF Bus Reference Voltage RTT Termination Resistance 45 50 55 Ω 4 COMP[1:0] COMP Resistance 50.49 51 51.51 Ω 5 NOTES: 1.
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Electrical Specifications Table 19. System Bus Differential Clock Specifications T# Parameter Min Nom System Bus Frequency T1: BCLK[1:0] Period 10.0 T2: BCLK[1:0] Period Stability Max Unit 100 MHz 10.2 ns 200 ps Notes1 Figure 10 2 3 T3: BCLK[1:0] High Time 3.94 5 6.12 ns 10 T4: BCLK[1:0] Low Time 3.94 5 6.12 ns 10 T5: BCLK[1:0] Rise Time 175 700 ps 10 4 T6: BCLK[1:0] Fall Time 175 700 ps 10 4 NOTES: 1.
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Electrical Specifications Table 21. System Bus Source Synch AC Specifications AGTL+ Signal Group Max Unit Figure Notes1,2,3,4 1.20 ns 14, 15 5 0.85 ns 15 5, 8 T22: TVAD: Source Synchronous Data Output Valid After Strobe 0.85 ns 15 5, 9 T23: TVBA: Source Synchronous Address Output Valid Before Strobe 1.88 ns 14 5, 8 T24: TVAA: Source Synchronous Address Output Valid After Strobe 1.88 ns 14 5, 9 T25: TSUSS: Source Synchronous Input Setup Time to Strobe 0.
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Electrical Specifications Table 22. Miscellaneous Signals AC Specifications T# Parameter Min T35: Asynch GTL+ Input Pulse Width 2 T36: PWRGOOD to RESET# de-assertion time 1 T37: PWRGOOD Inactive Pulse Width T38: PROCHOT# pulse width Max Notes1,2,3,6 Figure BCLKs 10 ms 16 10 BCLKs 16 4 500 us 18 5 0.5 s 19 5 BCLKs 20 T39: THERMTRIP# to Vcc Removal T40: FERR# Valid Delay from STPCLK# deassertion Unit 0 NOTES: 1.
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Electrical Specifications Table 24. TAP Signals AC Specifications Parameter Min T55: TCK Period Max 60.0 Unit Figure ns 9 Notes1,2,3 T56: TCK Rise Time 10.0 ns 9 4 T57: TCK Fall Time 10.0 ns 9 4 T58: TMS Rise Time 8.5 ns 9 4 T59: TMS Fall Time 8.5 ns 9 4, 9 T61: TDI Setup Time 0 ns 21 5, 7 T62: TDI Hold Time 3 ns 21 5, 7 ns 21 6 TCK 18 8, 9 T63: TDO Clock to Output Delay 3.5 T64: TRST# Assert Time 2 NOTES: 1.
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Electrical Specifications . Table 26.
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Electrical Specifications Figure 8. AC Test Circuit VCC VCC Rload= 50 ohms 420 mils, 50 ohms, 169 ps/in 2.4nH 1.2pF AC Timings test measurements made here. Figure 9. TCK Clock Waveform V2 V3 V1 tr = T56, T58 (Rise Time) tf = T57, T59 (Fall Time) tp = T55 (TCK Period) Mobile Intel Pentium 4 Processor-M Datasheet V1,V2: For rise and fall times, TCK is measured between 20% to 80% points on the waveform V3: TCK is referenced to 0.
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Electrical Specifications . Figure 10.
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Electrical Specifications Figure 11. Differential Clock Crosspoint Specification Crosspoint Specification 650 600 Crossing CrossingPoint Point(mV) (V) 550 550 mV 500 450 550 + 0.5 (VHavg - 710) 400 250 + 0.5 (VHavg - 710) 350 300 250 250 mV 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg Vhavg(V) (mV) Figure 12.
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Electrical Specifications Figure 13. System Bus Reset and Configuration Timings BCLK Tt Reset Tv Tx Tw Configuration Valid A[31:3], SMI#, INIT#, BR[3:0]# Tv = T13 (RESET# Pulse Width) Tw = T45 (Reset Configuration Signals Setup TIme) Tx = T46 (Reset Configuration Signals Hold TIme) Figure 14. Source Synchronous 2X (Address) Timings T1 2.5 ns 5.0 ns T2 7.
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Electrical Specifications Figure 15. Source Synchronous 4X Timings T0 T1 2.5 ns 5.0 ns T2 7.5 ns BCLK1 BCLK0 DSTBp# (@ driver) TH DSTBn# (@ driver) TA TB TA TD D# (@ driver) DSTBp# (@ receiver) TJ DSTBn# (@ receiver) TC D# (@ receiver) TE TG TE TG TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T27: Source Sync. Setup Time to BCLK TD = T30: Source Sync.
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Electrical Specifications Figure 16. Power Up Sequence BCLK Vcc PWRGOOD Tc Td RESET# VCCVID Ta Tb VID_GOOD VID[4:0], BSEL[1:0] Ta= 1us minimum (VCCVID > 1V to VID_GOOD high) Tb= 50ms maximum (VID_GOOD to Vcc valid maximum time) Tc= T37 (PWRGOOD inactive pulse width) Td= T36 (PWRGOOD to RESET# de-assertion time) Note: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage regluator control silicon.
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Electrical Specifications Figure 18. Test Reset Timings 1.25V TRST# Tq Tq = T64 (TRST# Pulse Width), V=0.5*Vcc Tq = T37 (TRST# Pulse Width) T38 (PROCHOT# Pulse Width), V=GTLREF PCB-773 Figure 19. THERMTRIP# to Vcc Timing T39 THERMTRIP# Vcc T39 < 0.5 seconds Note: THERMTRIP# is undefined when RESET# is active Figure 20.
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Electrical Specifications Figure 21. TAP Valid Delay Timing V TCK Tx Ts Th Signal V Valid Tx = T63 (Valid Time) Ts = T61 (Setup Time) Th = T62 (Hold Time) V = 0.5 * Vcc Figure 22.
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Electrical Specifications Figure 23.
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Electrical Specifications Figure 24.
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System Bus Signal Quality Specifications 3. System Bus Signal Quality Specifications Source synchronous data transfer requires the clean reception of data signals and their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines.
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System Bus Signal Quality Specifications Figure 25. BCLK Signal Integrity Waveform Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot 3.
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System Bus Signal Quality Specifications Table 29. Ringback Specifications for PWRGOOD Input and TAP Signal Groups Signal Group Transition Maximum Ringback (with Input Diodes Present) Unit Figure TAP and PWRGOOD 0→1 Vt+(max) TO Vt-(max) V 28 1,2,3,4 TAP and PWRGOOD 1→0 Vt-(min) TO Vt+(min) V 29 1,2,3,4 Notes NOTES: 1. All signal integrity specifications are measured at the processor silicon. 2.
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System Bus Signal Quality Specifications Figure 28. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Threshold Region to switch receiver to a logic 1. Vt+ (max) Vt+ (min) 0.5 * Vcc Vt- (max) Allowable Ringback Vss Figure 29. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Allowable Ringback Vt+ (min) 0.5 * Vcc Vt- (max) Vt- (min) Threshold Region to switch receiver to a logic 0.
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System Bus Signal Quality Specifications 3.3 System Bus Signal Quality Specifications and Measurement Guidelines 3.3.1 Overshoot/Undershoot Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage (or below VSS) as shown in Figure 30. The overshoot guideline limits transitions beyond VCC or VSS due to the fast signal edge rates.
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System Bus Signal Quality Specifications Note: 3.3.4 Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration. Activity Factor Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY OTHER clock cycle. Thus, an AF = 0.
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System Bus Signal Quality Specifications The above procedure is similar for undershoot after the undershoot waveform has been converted to look like an overshoot. Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive. 3.3.6 Conformance Determination to Overshoot/Undershoot Specifications The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event.
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System Bus Signal Quality Specifications Table 31. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 1.700 -0.400 0.21 2.10 10.00 1.650 -0.350 0.48 4.80 10.00 1.600 -0.300 1.05 10.00 10.00 1.550 -0.250 2.38 10.00 10.00 1.500 -0.200 10.00 10.00 10.00 1.450 -0.150 10.00 10.00 10.00 1.400 -0.
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System Bus Signal Quality Specifications Table 33. Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups Overshoot/ Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 1.700 -0.400 1.26 12.6 60.00 1.650 -0.350 2.88 28.8 60.00 1.600 -0.300 6.30 60.00 60.00 1.550 -0.250 14.28 60.00 60.00 1.500 -0.200 60.00 60.00 60.00 1.450 -0.150 60.00 60.00 60.00 1.
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Package Mechanical Specifications 4. Package Mechanical Specifications The Mobile Intel Pentium 4 Processor-M is packaged in a 478 pin Micro-FCPGA package. Different views of the package are shown in Figure 31 through Figure 33. Package dimensions are shown in Table 34. Figure 31.
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Package Mechanical Specifications Figure 32. Micro-FCPGA Package Top and Side View SUBSTRATE KEEPOUT ZONE DO NOT CONTACT PACKAGE INSIDE THIS LINE 7 (K1) 8 places 5 (K) 4 places 0.286 A 1.25 MAX (A3) D1 35 (D) Ø 0.32 (B) 478 places A2 E1 35 (E) PIN A1 CORNER 2.03 ± 0.08 (A1) All dimensions in millimeters. Values shown are for reference only.
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Package Mechanical Specifications Table 34. Micro-FCPGA Package Dimensions Symbol Param eter Min M ax Unit A Overall height, top of die to package seating plane 1.81 2.03 mm - Overall height, top of die to PCB surface, including socket(1) 4.69 5.15 mm A1 Pin length 1.95 2.11 mm A2 Die height A3 Pin-side capacitor height 0.854 - mm 1.25 mm B Pin diameter 0.28 0.36 mm D Package substrate length 34.9 35.1 mm E Package substrate width 34.9 35.1 mm Die length 12.
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Package Mechanical Specifications Figure 33. Micro-FCPGA Package - Bottom View 14 (K3) AF AD AB Y V T P M K H F D B AE AC AA W U R 14 (K3) N L J G E C A 1 25X 1.27 (e) 3 2 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 25X 1.27 (e) NOTE: All dimensions in millimeters. Values shown are for reference only. 4.1 Processor Pin-Out Figure 34 shows the top view pinout of the Mobile Intel Pentium 4 Processor-M.
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Package Mechanical Specifications Figure 34. The Coordinates of the Processor Pins as Viewed From the Top of the Package.
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Pin Listing and Signal Definitions 5. Pin Listing and Signal Definitions 5.1 Mobile Intel Pentium 4 Processor-M Pin Assignments Section 5.1 contains the pin list for the Mobile Intel Pentium 4 Processor-M in Table 35 and Table 36. Table 35 is a listing of all processor pins ordered alphabetically by pin name. Table 36 is also a listing of all processor pins but ordered by pin number.
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Pin Listing and Signal Definitions Table 35. Table 35.
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Pin Listing and Signal Definitions Table 35. Pin Name Pin Listing by Pin Name Pin Number Signal Buffer Type Table 35.
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Pin Listing and Signal Definitions Table 35. Pin Name Pin Listing by Pin Name Pin Number Signal Buffer Type Table 35.
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Pin Listing and Signal Definitions Table 35. Pin Name Pin Listing by Pin Name Pin Number Signal Buffer Type Table 35.
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Pin Listing and Signal Definitions Table 35. Pin Name Pin Listing by Pin Name Pin Number Signal Buffer Type Table 35.
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Pin Listing and Signal Definitions Table 35. Pin Name Pin Listing by Pin Name Pin Number Signal Buffer Type Table 35.
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Pin Listing and Signal Definitions Table 35. Pin Listing by Pin Name Pin Number Pin Name Signal Buffer Type Table 36.
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Pin Listing and Signal Definitions Table 36. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 36.
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Pin Listing and Signal Definitions Table 36. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 36.
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Pin Listing and Signal Definitions Table 36. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 36.
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Pin Listing and Signal Definitions Table 36. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 36.
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Pin Listing and Signal Definitions Table 36. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 36.
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Pin Listing and Signal Definitions Table 36.
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Pin Listing and Signal Definitions 5.2 Alphabetical Signals Reference Table 37. Signal Description (Page 1 of 8) Name Type Description Input/ Output A[35:3]# (Address) define a 236-byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Mobile Intel Pentium 4 Processor-M system bus.
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Pin Listing and Signal Definitions Table 37. Signal Description (Page 2 of 8) Name Type Description BINIT# Input/ Output BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
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Pin Listing and Signal Definitions Table 37. Signal Description (Page 3 of 8) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period.
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Pin Listing and Signal Definitions Table 37. Signal Description (Page 4 of 8) Name Type Description DPSLP# Input DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP# must be deasserted and BCLK[1:0] must be running. DRDY# Input/ Output DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus.
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Pin Listing and Signal Definitions Table 37. Signal Description (Page 5 of 8) Name HIT# HITM# IERR# IGNNE# INIT# ITPCLKOUT [1:0] ITP_CLK[1:0] LINT[1:0] LOCK# Type Input/ Output Input/ Output Output Description HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.
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Pin Listing and Signal Definitions Table 37. Signal Description (Page 6 of 8) Name Type Description MCERR# Input/ Output MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: Enabled or disabled. Asserted, if configured, for internal errors along with IERR#.
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Pin Listing and Signal Definitions Table 37. Signal Description (Page 7 of 8) Name SKTOCC# Type Output Description SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this pin to determine if the processor is present. Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state.
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Pin Listing and Signal Definitions Table 37. Signal Description (Page 8 of 8) Name THERMTRIP# Description Output Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135°C.
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Thermal Specifications and Design Considerations 6. Thermal Specifications and Design Considerations In order to achieve proper cooling of the processor, a thermal solution (e.g., heat spreader, heat pipe, or other heat transfer system) must make firm contact to the exposed processor die. The processor die must be clean before the thermal solution is attached or the processor may be damaged.
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Thermal Specifications and Design Considerations and is not representative of the absolute maximum power the processor may dissipate under worst case conditions. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. The maximum junction temperature (TJ) is specified as the hottest location on the die.
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Thermal Specifications and Design Considerations Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction temperature. RT as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor.
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Thermal Specifications and Design Considerations An external signal, PROCHOT# (processor hot) is asserted when the processor die temperature has reached its thermal limit. If the TCC is enabled (note that the TCC must be enabled for the processor to be operating within spec), TCC will be active when the PROCHOT# signal is active. The temperature at which the thermal control circuit activates is not user configurable and is not software visible.
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Configuration and Low Power Features 7. Configuration and Low Power Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Mobile Intel Pentium 4 Processor-M samples its hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, please refer to Table 41. Frequency determination functionality will exist on engineering sample processors which means that samples can run at varied frequencies.
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Configuration and Low Power Features The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Powerdown state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.
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Configuration and Low Power Features While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process a system bus snoop. 7.2.
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Configuration and Low Power Features The clock may be stopped when the processor is in the Deep Sleep state in order to support the ACPI S1 state. The clock may only be stopped after DPSLP# is asserted and must be restarted before DPSLP# is deasserted. To provide maximum power conservation when stopping the clock during Deep Sleep, hold the BLCK0 input at VOL and the BCLK1 input at VOH. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals.
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Debug Tools Specifications 8. Debug Tools Specifications Please refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for information regarding debug tools specifications. 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Mobile Intel Pentium 4 Processor-M systems.