Intel® Xeon® Processor 3400 Series Datasheet - Volume 1 September 2009 Document Number: 322371-001
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Contents 1 Introduction .............................................................................................................. 9 1.1 Processor Feature Details ................................................................................... 11 1.1.1 Supported Technologies .......................................................................... 11 1.2 Interfaces ........................................................................................................ 12 1.2.
3.2 3.3 3.4 3.1.3 3.1.4 3.1.5 Intel® Intel® Intel® Intel® VT-d Objectives ............................................................................30 Intel® VT-d Features ...............................................................................30 Intel® VT-d Features Not Supported..........................................................31 Trusted Execution Technology (Intel® TXT) .................................................31 Hyper-Threading Technology ......................................
7 Electrical Specifications ........................................................................................... 59 7.1 Power and Ground Lands.................................................................................... 59 7.2 Decoupling Guidelines ........................................................................................ 59 7.2.1 Voltage Rail Decoupling........................................................................... 59 7.3 Processor Clocking (BCLK[0], BCLK#[0]) .....
Tables 1-1 Intel® Xeon® Processor 3400 Series Supported Memory Summary .................................12 1-2 Related Documents...................................................................................................18 2-1 Supported DIMM Module Configurations.......................................................................19 2-2 DDR3 System Memory Timing Support .......................................................................20 2-3 System Memory Pre-Charge Power Down Support........
Revision History Revision Number -001 Description Date September 2009 • Initial release § Intel® Xeon® Processor 3400 Series Datasheet, Volume 1 7
Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
Introduction 1 Introduction The Intel® Xeon® processor 3400 series are the next generation of 64-bit, multi-core processors built on 45-nanometer process technology. Based on the low-power/highperformance Intel® Core™2 micro-architecture, the processor is designed for a twochip platform, as opposed to the traditional three-chip platforms (processor, (G)MCH, and ICH).
Introduction Figure 1-1. Intel® Xeon® Processor 3400 Series Platform Diagram Quad Core CPU with Integrated Memory Controller Discrete Graphics (PEG) PCI Express* 1x16 2 Channels (2 UDIMM/Channel) Or (3 RDIMM/Channel) Processor OR PCI Express* 2x 8 OR PCI Express* 4x4 DDR3 DIM Ms DDR3 DIMM s Note: Supported PCI Express configurations vary by SKU. DMI PECI Intel® Management Engine Serial ATA 6 Ports 3 Gb/s USB 2.0 14 Ports Intel® 3400 Series Chipset Intel® HD Audio SMBUS 2.
Introduction 1.1 Processor Feature Details • Four cores • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data second-level cache (L2) for each core • 8 MB shared instruction/data last-level cache (L3), shared among all cores 1.1.1 Supported Technologies • Intel® Virtualization Technology for Directed I/O (Intel® VT-d) • Intel® Virtualization Technology (Intel® VT-x) • Intel® Active Management Technology 6.0 (Intel® AMT 6.
Introduction 1.2 Interfaces 1.2.1 System Memory Support Table 1-1. Intel® Xeon® Processor 3400 Series Supported Memory Summary Platform Intel 3400 and 3420 Chipset Platforms Transfer Rate (MT/s) # of Channels DIMMs/ Channel DDR3: ECC Registered DIMM 1 or 2 Up to 3 800, 1066, 1333 1 DDR3: ECC Unbuffered DIMM 1 or 2 1 or 2 1066, 1333 1 Memory Type Notes Notes: 1. Non-ECC DIMMs are not supported. Mixing of non-ECC and ECC DIMMs is not supported.
Introduction 1.2.2 PCI Express* • The processor PCI Express* port(s) are fully-compliant with the PCI Express Base Specification, Revision 2.0. • Intel® Xeon® processor 3400 series with Intel 3420 Chipset supports: — One 16-lane PCI Express port intended for graphics or I/O. — Two 8-lane PCI Express ports intended for I/O. — Four 4-lane PCI Express ports intended for I/O. • Intel® Xeon® processor 3400 series with Intel 3400 Chipset supports: — Two 8-lane PCI Express ports intended for I/O.
Introduction • Re-issues Configuration cycles that have been previously completed with the Configuration Retry status. • PCI Express reference clock is 100-MHz differential clock. • Power Management Event (PME) functions. • Dynamic lane numbering reversal as defined by the PCI Express Base Specification. • Dynamic frequency change capability (2.5 GT/s - 5.0 GT/s) • Dynamic width capability • Message Signaled Interrupt (MSI and MSI-X) messages. • Polarity inversion. 1.2.
Introduction 1.3 Power Management Support 1.3.1 Processor Core • Full support of ACPI C-states as implemented by the following processor C-states: — C0, C1, C1E, C3, C6 • Enhanced Intel SpeedStep® Technology 1.3.2 System • S0, S1, S4, S5 1.3.3 Memory Controller • Conditional self-refresh • Dynamic power-down 1.3.4 PCI Express* • L0s and L1 ASPM power management capability. — L0s not supported on the Intel Xeon® processor 3400 series when configured as PCI Express 4x4 1.
Introduction 1.6 Terminology Term DDR3 Third generation Double Data Rate SDRAM memory technology DP Display Port* DMA Direct Memory Access DMI Direct Media Interface DTS Digital Thermal Sensor ECC Error Correction Code Enhanced Intel SpeedStep® Technology Technology that provides power management capabilities. Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system.
Introduction Term Description Processor The 64-bit multi-core component (package) Processor Core The term “processor core” refers to Si die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the L3 cache. Rank A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a DIMM. SCI System Control Interrupt.
Introduction 1.7 Related Documents Refer to the following documents for additional information. Table 1-2. Related Documents Document Document Number/ Location Intel® Xeon® Processor 3400 Series Datasheet, Volume 2 http://www.intel.com/Assets/PDF /datasheet/322372.pdf Intel® Xeon® Processor 3400 Series Specification Update http://www.intel.com/Assets/PDF /datasheet/322373.
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. 2.1 System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels. Refer to Section 1.2.1 for details on the type of memory supported.
Interfaces 2.1.2 System Memory Timing Support The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface: • tCL = CAS Latency • tRCD = Activate Command to READ or WRITE Command delay • tRP = PRECHARGE Command Period • CWL = CAS Write Latency • Command Signal modes = 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks.
Interfaces 2.1.3.2 Dual-Channel Mode — Intel® Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology mode. This mode combines the advantages of the Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes. Memory is divided into a symmetric and a asymmetric zone. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached.
Interfaces 2.1.3.2.2 Dual-Channel Asymmetric Mode This mode trades performance for system design flexibility. Unlike the previous mode, addresses start at the bottom of Channel A and stay there until the end of the highest rank in Channel A, and then addresses continue from the bottom of Channel B to the top.
Interfaces 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.1 Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next.
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express. The number of PCI Express controllers available is dependent on the platform: • Intel Xeon® Processor 3400 series with Intel 3400 and 3420 Chipset: 1 x16 PCI Express I/O, 2 x8 PCI Express I/O, or 4 x4 PCI Express I/O are supported. 2.2.
Interfaces Figure 2-4. Packet Flow through the Layers 2.2.1.1 Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer also manages flow control of TLPs. 2.2.1.
Interfaces 2.2.2 PCI Express* Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. . Figure 2-5.
Interfaces 2.2.3.1 PCI Express* Bifurcated Mode When bifurcated, the signals which had previously been assigned to lanes 15:8 of the single x16 Primary port are reassigned to lanes 7:0 of the x8 Secondary port. This assignment applies whether the lane numbering is reversed or not. The controls for the Secondary port and the associated virtual PCI-to-PCI bridge can be found in PCI Device 5. Refer to Table 6-5 for port bifurcation configuration settings and supported configurations.
Interfaces 2.4 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between processor and a PECI master, usually the PCH. The processor implements a PECI interface to: • Allow communication of processor thermal and other information to the PECI master. • Read averaged Digital Thermal Sensor (DTS) values for fan speed control. 2.5 Interface Clocking 2.5.1 Internal Clocking Requirements Table 2-4.
Technologies 3 Technologies 3.1 Intel® Virtualization Technology Intel Virtualization Technology (Intel VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets.
Technologies • Guest Preemption Timer — Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM.
Technologies 3.1.
Technologies 3.3 Intel® Hyper-Threading Technology The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology), which allows an execution core to function as two logical processors. While some execution resources such as caches, execution units, and buses are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers. This feature must be enabled using the BIOS and requires operating system support.
Power Management 4 Power Management This chapter provides information on the following power management topics: • ACPI States • Processor Core • IMC • PCI Express* 4.1 ACPI States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States State Description G0/S0 Full On G1 Suspend-to-RAM (STR). G1/S4 Suspend-to-Disk (STD). All power lost (except wakeup on PCH). G2/S5 Soft off. All power lost (except wakeup on PCH). Total reboot.
Power Management 4.1.4 PCI Express* Link States State Description L0 Full on – Active transfer state. L0s First Active Power Management low power state – Low exit latency. L1 Lowest Active Power Management - Longer exit latency. L3 Lowest power state (power-off) – Longest exit latency. 4.1.5 Interface State Combinations Table 4-2. G, S, and C State Combinations 4.
Power Management 4.2.1 Enhanced Intel® SpeedStep® Technology The following are the key features of Enhanced Intel SpeedStep Technology: • Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.
Power Management Entry and exit of the C-States at the thread and core level are shown in Figure 4-2. Figure 4-2. Thread and Core C-State Entry and Exit C0 MWAIT(C6), P_LVL3 I/O Read MWAIT(C1), HLT MWAIT(C1), HLT (C1E Enabled) C1 MWAIT(C3), P_LVL2 I/O Read C1E C3 C6 While individual threads can request low power C-states, power saving actions only take place once the core C-state is resolved. Core C-states are automatically resolved by the processor.
Power Management 4.2.3 Requesting Low-Power Idle States The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E). However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx.
Power Management 4.2.4.1 Core C0 State The normal operating state of a core where code is being executed. 4.2.4.2 Core C1/C1E State C1/C1E is a low power state entered when all threads within a core execute a HLT or MWAIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.
Power Management 4.2.5 Package C-States The processor supports C0, C1/C1E, C3, and C6 power states. The following is a summary of the general rules for package C-state entry. These apply to all package Cstates unless specified otherwise: • A package C-state request is determined by the lowest numerical core C-state amongst all cores. • A package C-state is automatically resolved by the processor depending on the core idle power states and the status of the platform components.
Power Management Figure 4-3. Package C-State Entry and Exit C0 C3 C1 4.2.5.1 C6 Package C0 The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0. 4.2.5.
Power Management 4.2.5.3 Package C3 State A processor enters the package C3 low power state when: • At least one core is in the C3 state. • The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform. • The processor has requested the C6 state, but the platform only allowed C3. In package C3-state, the L3 shared cache is snoopable. 4.2.5.4 Package C6 State A processor enters the package C6 low power state when: • At least one core is in the C6 state.
Power Management 4.3.2 DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface. There are four SDRAM operations associated with the Clock Enable (CKE) signals, which the SDRAM controller supports. The processor drives four CKE pins to perform these operations. 4.3.2.1 Initialization Role of CKE During power-up, CKE is the only input to the SDRAM that has its level recognized (other than the DDR3 reset pin) once power is applied.
Power Management 4.3.2.4 DRAM I/O Power Management Unused signals should be disabled to save power and reduce electromagnetic interference. This includes all signals associated with an unused memory channel. Clocks can be controlled on a per DIMM basis. Exceptions are made for per DIMM control signals, such as CS#, CKE, and ODT for unpopulated DIMM slots.
Power Management 44 Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
Thermal Management 5 Thermal Management For thermal specifications and design guidelines, refer to the appropriate Thermal and Mechanical Specifications and Design Guidelines (see Section 1.7).
Thermal Management 46 Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
Signal Description 6 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type. Notations Signal Type I Input Pin O Output Pin I/O Bi-directional Input/Output Pin The signal description also includes the type of buffer used for the particular signal. Table 6-1.
Signal Description 6.1 System Memory Interface Table 6-2. Memory Channel A Signal Name 48 Description Direction Type SA_BS[2:0] Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SA_CAS# CAS Control Signal: Used with SA_RAS# and SA_WE# (along with SA_CS#) to define the SDRAM Commands. O DDR3 SA_CK#[1:0] SDRAM Inverted Differential Clock: Channel A SDRAM Differential clock signal-pair complement.
Signal Description Table 6-3. Memory Channel B Signal Name Description Direction Type SB_BS[2:0] Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SB_CAS# CAS Control Signal: Used with SB_RAS# and SB_WE# (along with SB_CS#) to define the SDRAM Commands. O DDR3 SB_CK#[1:0] SDRAM Inverted Differential Clock: Channel B SDRAM Differential clock signal-pair complement.
Signal Description 6.2 Memory Reference and Compensation Table 6-4. Memory Reference and Compensation Signal Name Description SA_DIMM_VREFDQ SB_DIMM_VREFDQ Channel A and B Output DDR3 DIMM DQ Reference Voltage. SM_RCOMP[2:0] System Memory Impedance Compensation. 6.3 Reset and Miscellaneous Signals Table 6-5.
Signal Description Table 6-5. Reset and Miscellaneous Signals (Sheet 2 of 2) Signal Name Description Direction Type RSTIN# Reset In: When asserted this signal will asynchronously reset the processor logic. This signal is connected to the PLTRST# output of the PCH. I CMOS RSVD RESERVED. Must be left unconnected on the board. Intel does not recommend a test point on the board for this land. RSVD_NCTF RESERVED/Non-Critical to Function: pin for package mechanical reliability.
Signal Description 6.5 DMI — Processor to PCH Serial Interface Table 6-7. DMI — Processor to PCH Serial Interface Signal Name Description Direction Type DMI_RX[3:0] DMI_RX#[3:0] DMI input from PCH: Direct Media Interface receive differential pair. I DMI DMI_TX[3:0] DMI_TX#[3:0] DMI output to PCH: Direct Media Interface transmit differential pair. O DMI Direction Type I Diff Clk I Diff Clk O Diff Clk I Diff Clk 6.6 PLL Signals Table 6-8.
Signal Description Table 6-9. Intel® Flexible Display Interface (Sheet 2 of 2) Signal Name Description Direction Type Direction Type GTL Intel® 6.8 FDI_LSYNC[1] Flexible Display Interface Line Sync - Pipe B. Note: This signal is not used by the processor. It is connected to VSS on the package. FDI_TX[3:0] FDI_TX#[3:0] Intel® Flexible Display Interface Transmit Differential Pair - Pipe A.. Note: These signals are not used by the processor. They are connected to VSS on the package.
Signal Description 6.9 Error and Thermal Protection Table 6-11. Error and Thermal Protection Signal Name 54 Description Direction Type CATERR# Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.
Signal Description 6.10 Power Sequencing Table 6-12. Power Sequencing Signal Name 6.11 Description Direction Type SKTOCC# SKTOCC# (Socket Occupied): This signal will be pulled to ground on the processor package. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present. O SM_DRAMPWROK SM_DRAMPWROK processor input: This signal connects to PCH DRAMPWROK. I Asynch CMOS TAPPWRGOOD Power good for ITP.
Signal Description Table 6-13. Processor Core Power Signals (Sheet 2 of 2) Signal Name Description Direction Type I/O CMOS VID[7:0] (Voltage ID) are used to support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator-Down (VRD) 11.1 Design Guidelines for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals become valid.
Signal Description 6.12 Graphics and Memory Core Power Signals Note: The signals noted below as not being used are included for reference to define all LGA 1156 land locations. These signals will be used by future processors that are compatible with LGA 1156 platforms. Table 6-14. Graphics and Memory Power Signals Signal Name Description Direction Type GFX_DPRSLPVR GPU output signal to a VRD11.1 compliant VR. When asserted this signal indicates that the GPU is in render suspend mode.
Signal Description 6.13 Ground and NCTF Table 6-15. Ground and NCTF Signal Name 6.14 Description Direction VSS VSS are the ground pins for the processor and should be connected to the system ground plane. CGC_TP_NCTF Corner Ground Connection: This land may be used to test for connection to ground. A test point may be placed on the board for this land. This land is considered NonCritical to Function. Type GND Processor Internal Pull Up/Pull Down Table 6-16.
Electrical Specifications 7 Electrical Specifications 7.1 Power and Ground Lands The processor has VCC, VTT, VDDQ, VCCPLL, VAXG, and VSS (ground) inputs for onchip power distribution. All power lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop.
Electrical Specifications 7.3 Processor Clocking (BCLK[0], BCLK#[0]) The processor uses a differential clock to generate the processor core(s) operating frequency, memory controller frequency, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by 133 MHz. Clock multiplying within the processor is provided by an internal phase locked loop (PLL), which requires a constant frequency input, with exceptions for Spread Spectrum Clocking (SSC).
Electrical Specifications Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 1 of 3) VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX 0 0 0 0 0 0 0 0 OFF 0 1 0 1 1 0 1 1 1.04375 0 0 0 0 0 0 0 1 OFF 0 1 0 1 1 1 0 0 1.03750 0 0 0 0 0 0 1 0 1.60000 0 1 0 1 1 1 0 1 1.03125 0 0 0 0 0 0 1 1 1.59375 0 1 0 1 1 1 1 0 1.
Electrical Specifications Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 2 of 3) VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX 0 0 1 0 0 1 1 1 1.36875 1 0 0 0 0 0 1 0 0.80000 0 0 1 0 1 0 0 0 1.36250 1 0 0 0 0 0 1 1 0.79375 0 0 1 0 1 0 0 1 1.35625 1 0 0 0 0 1 0 0 0.78750 0 0 1 0 1 0 1 0 1.35000 1 0 0 0 0 1 0 1 0.
Electrical Specifications Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 3 of 3) VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX 0 1 0 0 1 1 1 1 1.11875 1 0 1 0 1 0 1 0 0.55000 0 1 0 1 0 0 0 0 1.11250 1 0 1 0 1 0 1 1 0.54375 0 1 0 1 0 0 0 1 1.10625 1 0 1 0 1 1 0 0 0.53750 0 1 0 1 0 0 1 0 1.10000 1 0 1 0 1 1 0 1 0.
Electrical Specifications 7.
Electrical Specifications Table 7-3.
Electrical Specifications Table 7-3.
Electrical Specifications 7.7 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage.
Electrical Specifications 7.9 DC Specifications The processor DC specifications in this section are defined at the processor pads, unless noted otherwise. See Chapter 8 for the processor land listings and Chapter 6 for signal definitions. Voltage and current specifications are detailed in Table 7-5, and Table 7-6. For platform planning, refer to Table 7-7, which provides VCC static and transient tolerances. This same information is presented graphically in Figure 7-1.
Electrical Specifications Table 7-6. Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Voltage for the memory controller and shared cache defined at the socket motherboard VTT pinfield via. 1.045 1.10 1.155 V 1 Voltage for the memory controller and shared cache defined across VTT_SENSE and VSS_SENSE_VTT. 1.023 1.10 1.117 V 2 VDDQ Processor I/O supply voltage for DDR3 1.425 1.5 1.
Electrical Specifications Table 7-7. VCC Static and Transient Tolerance Voltage Deviation from VID Setting 1, 2, 3 ICC (A) VCC_Max (V) 1.40 mΩ VCC_Typ (V) 1.40 mΩ VCC_Min (V) 1.40 mΩ 0 0.000 -0.019 -0.038 5 -0.007 -0.026 -0.045 10 -0.014 -0.033 -0.052 15 -0.021 -0.040 -0.059 20 -0.028 -0.047 -0.066 25 -0.035 -0.054 -0.073 30 -0.042 -0.061 -0.080 35 -0.049 -0.068 -0.087 40 -0.056 -0.075 -0.094 45 -0.063 -0.082 -0.101 50 -0.070 -0.089 -0.108 55 -0.077 -0.
Electrical Specifications Figure 7-1. VCC Static and Transient Tolerance Loadlines Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 VID - 0.050 VID - 0.063 Vcc Maximum VID - 0.075 Vcc [V] VID - 0.088 VID - 0.100 VID - 0.113 Vcc Minimum VID - 0.125 VID - 0.138 Vcc Typical VID - 0.150 VID - 0.163 VID - 0.175 VID - 0.
Electrical Specifications Table 7-8. Symbol DDR3 Signal Group DC Specifications Parameter Alpha Group Min Typ Max Units Notes1 — 0.43*VDDQ V 2,4 V 3 VIL Input Low Voltage (e,f) — VIH Input High Voltage (e,f) 0.
Electrical Specifications Table 7-9. Symbol Control Sideband and TAP Signal Group DC Specifications Alpha Group Min Typ Max Units Notes1 Input Low Voltage — — 0.64 * VTT V 2 Parameter VIL (m),(n),(p),(qa),(qb),(s) VIH (m),(n),(p),(qa),(qb),(s) Input High Voltage 0.76 * VTT — — V 2,4 VIL (g) Input Low Voltage — — 0.4 * VTT V 2 VIH (g) Input High Voltage 0.75 * VTT — — V 2,4 VIL (ja) Input Low Voltage — — 0.25 * VTT V 2 VIH (ja) Input High Voltage 0.
Electrical Specifications Table 7-10. PCI Express DC Specifications Symbol Alpha Group Parameter Min Typ Max Units Notes1 VTX-DIFF-p-p (ad) Differential peak to peak Tx voltage swing 0.8 — 1.
Electrical Specifications 7.10.1 DC Characteristics The PECI interface operates at a nominal voltage set by VTT. The set of DC electrical specifications shown in Table 7-11 is used with devices normally operating from a VTT interface supply. VTT nominal levels will vary between processor families. All PECI devices will operate at the VTT level determined by the processor installed in the system. For specific nominal VTT levels, refer to Table 7-6. Table 7-11.
Electrical Specifications 76 Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
Processor Land and Signal Information 8 Processor Land and Signal Information 8.1 Processor Land Assignments The processor land-map quadrants are shown in Figure 8-1 through Figure 8-4. Table 8-2 provides a listing of all processor lands ordered alphabetically by pin name. Not all signals are used by the processor. Table 8-1 lists the signals that are not used by the Intel Xeon processor 3400 series. Table 8-1.
Processor Land and Signal Information Figure 8-1.
Processor Land and Signal Information Figure 8-2.
Processor Land and Signal Information Figure 8-3.
Processor Land and Signal Information Figure 8-4.
Processor Land and Signal Information Table 8-2. Table 8-2. Pin Name Pin # Buffer Type Pin Name Dir. DMI_RX[1] Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-2. Pin Name Processor Pin List by Pin Name Table 8-2. Pin # Buffer Type Dir. Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-2. Pin Name Pin # Buffer Type Dir. Table 8-2. Pin Name Processor Pin List by Pin Name Buffer Type Dir.
Processor Land and Signal Information Table 8-2. Pin Name Processor Pin List by Pin Name Table 8-2. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir. Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-2. Pin Name 86 Processor Pin List by Pin Name Table 8-2. Pin # Buffer Type Dir. SA_MA[12] AW11 DDR3 O SB_DM[2] Pin Name SA_MA[13] AU24 DDR3 O SA_MA[14] AT11 DDR3 O SA_MA[15] AR10 DDR3 SA_MA[2] AV15 SA_MA[3] SA_MA[4] SA_MA[5] AY13 SA_MA[6] AV14 SA_MA[7] AW13 SA_MA[8] AU14 SA_MA[9] AW12 SA_ODT[0] AV23 SA_ODT[1] AV24 SA_ODT[2] AW23 SA_ODT[3] SA_RAS# Processor Pin List by Pin Name Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-2. Pin Name SB_DQ[43] Processor Pin List by Pin Name Table 8-2. Pin # Buffer Type Dir. AM32 DDR3 I/O SB_ECC_CB[0] Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-2. Pin Name Pin # Buffer Type Dir. AM39 TAP I VAXG A14 VAXG A15 VAXG Table 8-2.
Processor Land and Signal Information Table 8-2.
Processor Land and Signal Information Table 8-2. Pin Name 90 Processor Pin List by Pin Name Dir. Table 8-2. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Pin # Buffer Type VCC K33 PWR VCC P36 PWR Dir.
Processor Land and Signal Information Table 8-2. Pin Name Processor Pin List by Pin Name Table 8-2. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-2. Pin Name 92 Processor Pin List by Pin Name Dir. Table 8-2.
Processor Land and Signal Information Table 8-2. Pin Name Processor Pin List by Pin Name Pin Name Processor Pin List by Pin Name Pin # Buffer Type Pin # Buffer Type F16 GND VSS J38 GND VSS F2 GND VSS J4 GND VSS F20 GND VSS J7 GND VSS F23 GND VSS J9 GND VSS F26 GND VSS K11 GND GND VSS Dir. Table 8-2.
Processor Land and Signal Information Table 8-2.
Processor Land and Signal Information Table 8-2. Pin Name Processor Pin List by Pin Name Pin # Buffer Type VTT V40 PWR VTT V6 PWR VTT V7 PWR VTT V8 PWR VTT W1 PWR VTT W6 PWR VTT Y33 PWR VTT Y34 PWR VTT Y35 PWR VTT Y36 PWR VTT Y37 PWR VTT Y38 PWR AF39 CMOS VTT_SELECT VTT_SENSE AE35 Analog VTTPWRGOOD AG37 Asynch CMOS Dir.
Processor Land and Signal Information 96 Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
