8th and 9th Generation Intel® Core™ Processor Families Datasheet, Volume 1 of 2 Supporting 8th Generation Intel® Core™ Processor Families, Intel® Pentium® Processors, Intel® Celeron® Processors for U/H/S Platforms, known as Coffee Lake Supporting 9th Generation Intel® Core™ Processor Families H/S Platforms, formerly known as Coffee Lake Refresh April 2019 Revision 003 Document Number: 337344-003
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Contents 1 Introduction ............................................................................................................ 10 1.1 Processor Volatility Statement............................................................................. 12 1.2 Supported Technologies ..................................................................................... 12 1.3 Power Management Support ............................................................................... 13 1.3.
2.5.5 High-Definition Multimedia Interface (HDMI*) ............................................ 2.5.6 Digital Video Interface (DVI) ................................................................... 2.5.7 embedded DisplayPort* (eDP*) ............................................................... 2.5.8 Integrated Audio.................................................................................... 2.5.9 Multiple Display Configurations (Dual Channel DDR) ................................... 2.5.
4.5 4.6 4.7 4.8 4.9 Direct Media Interface (DMI) Power Management................................................... 83 Processor Graphics Power Management ................................................................ 83 4.6.1 Memory Power Savings Technologies ........................................................ 83 4.6.2 Display Power Savings Technologies ......................................................... 83 4.6.3 Processor Graphics Core Power Savings Technologies ...........................
2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 3-1 4-1 4-2 4-3 4-4 5-1 7-1 Example for DMI Lane Reversal Connection ............................................................... 33 Video Analytics Common Use Cases ......................................................................... 38 Gen 9 LP Block Diagram ......................................................................................... 39 Processor Display Architecture (With 3 DDI Ports as an Example).................................
2-35 2-36 2-37 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 Display Bit Per Pixel (BPP) Support .......................................................................... 51 Supported Resolutions for HBR (2.7 Gbps) by Link Width ............................................ 51 Supported Resolutions for HBR2 (5.4 Gbps) by Link Width ....
7-17 7-18 7-19 7-20 7-21 8-1 8-3 8-2 8 Digital Display Interface Group DC Specifications (DP/HDMI*) ....................................129 embedded DisplayPort* (eDP*) Group DC Specifications ............................................130 CMOS Signal Group DC Specifications......................................................................130 GTL Signal Group and Open Drain Signal Group DC Specifications ...............................130 PECI DC Electrical Limits.....................................
Revision History Revision 001 Description Initial Release Release Date April 2018 002 • • • • • • • Added S-Processor 2+2 (35W,65W) Added S-Processor 8+2 (95W,80W,65W,35W) Added 4-Core GT2 95W Removed DC_LL from VCCSA for S SKU Added U-Processor 2+3e Removed S-Processor 83W Xeon Updated Operation System Support for S/H/U Processors October 2018 003 • Added H-Processor 8+2 April 2019 §§ Datasheet, Volume 1 of 2 9
Introduction 1 Introduction The 8th and 9th Gen Intel® Core™ Processor is built on 14-nanometer process technology. The U-Processor Line is offered in a 1-Chip Platform that includes the Intel® 300 Series Chipset Families Platform Controller Hub (PCH) die on the same package as the processor die. Refer Figure 1-2. The U-Processor Line SKUs are offered with On-Package Cache. The H-Processor and S-Processor Lines are offered in a 2-Chip Platform. Refer Figure 1-1.
Introduction Figure 1-1.
Introduction Figure 1-2. U-Processor Line Platform 1.1 Processor Volatility Statement 8th and 9th Gen Intel® Core™ Processor families do not retain any end user data when powered down and/or when the processor is physically removed. Note: Power down refers to state which all processor power rails are off. 1.2 Supported Technologies • Intel® Virtualization Technology (Intel® VT) • Intel® Active Management Technology 11.0 (Intel® AMT 11.
Introduction • Intel® 64 Architecture • Execute Disable Bit • Intel® Turbo Boost Technology 2.
Introduction 1.3.3 Memory Controller Power Management • Disabling Unused System Memory Outputs • DRAM Power Management and Initialization • Initialization Role of CKE • Conditional Self-Refresh • Dynamic Power Down • DRAM I/O Power Management • DDR Electrical Power Gating (EPG) • Power training Refer to Section 4.3 for more information. 1.3.4 Processor Graphics Power Management 1.3.4.
Introduction • External Thermal Sensor (TS-on-DIMM and TS-on-Board) • Render Thermal Throttling • Fan speed control with DTS • Intel Turbo Boost Technology 2.0 Power Control Refer to Chapter 5, “Thermal Management” for more information. 1.5 Package Support The processor is available in the following packages: • A 46 mm x 24 mm BGA package (BGA1528) for U-Processor Line • A 42 mm x 28 mm BGA package (BGA1440) for H-Processor Line • A 37.5 mm x 37.5 mm LGA package (LGA1151) for S-Processor Line 1.
Introduction Table 1-2.
Introduction Table 1-2. Terminology (Sheet 3 of 3) Term Description NCTF Non-Critical to Function. NCTF locations are typically redundant ground or noncritical reserved balls/lands, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. OPC On-Package Cache PCH Platform Controller Hub.
Introduction 1.10 Related Documents Table 1-3. Related Documents Document Document Number / Location Advanced Configuration and Power Interface 3.0 http://www.acpi.info/ LPDDR3 Specification http://www.jedec.org DDR4 Specification http://www.jedec.org High Definition Multimedia Interface specification revision 1.4 http://www.hdmi.org/manufacturer/specification.aspx Embedded DisplayPort* Specification revision 1.4 http://www.vesa.org/vesa.standards/ DisplayPort* Specification revision 1.
Interfaces 2 Interfaces 2.1 System Memory Interface • Two channels of LPDDR3 and DDR4 memory with a maximum of two DIMMs per channel. DDR technologies, number of DIMMs per channel, number of ranks per channel are SKU dependent. • UDIMM, SO-DIMM, and Memory Down support (based on SKU) • Single-channel and dual-channel memory organization modes • Data burst length of eight for all memory organization modes • LPDDR3 I/O voltage of 1.2V • DDR4 I/O Voltage of 1.
Interfaces Table 2-1. Processor DDR Memory Speed Support (Sheet 2 of 2) DDR4 Memory Down [MT/s] DDR4 1DPC [MT/s] DDR4 2DPC [MT/s] LPDDR3 [MT/s] H-Processor Line 6+2 2666 26664 2400 2133 H-Processor Line 8+2 2666 26664 2400 N/A U-Processor Line 2400 2400 N/A 2133 Processor Line Notes: 1. 1DPC refers to when only 1 DIMM slot per Channel is routed. 2DPC refers to when 2 DIMM slots per Channel are routed and are fully populated or partially populated with 1 DIMM only. 2.
Interfaces Table 2-3.
Interfaces Table 2-6.
Interfaces Table 2-8. Table 2-9. DRAM System Memory Timing Support (Sheet 2 of 2) DRAM Device Transfer Rate (MT/s) tCL (tCK) tRCD (tCK) tRP (tCK) CWL (tCK) DPC (SODIMM Only) CMD Mode DDR4 2666 19 19 19 9/10/11/ 12/14/16/ 18 1 or 2 2N DRAM System Memory Timing Support (LPDDR3) DRAM Device Transfer Rate (MT/s) tCL (tCK) tRCD (tCK) tRPpb1 (tCK) tRPab2 (tCK) CWL (tCK) LPDDR3 1866 14 17 17 20 11 LPDDR3 2133 16 20 20 23 13 Notes: 1.
Interfaces Figure 2-1. Intel® Flex Memory Technology Operations Dual-Channel Symmetric Mode (Interleaved Mode) Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum performance on real world applications. Addresses are ping-ponged between the channels after each cache line (64-byte boundary). If there are two requests, and the second request is to an address on the opposite channel from the first, that request can be sent before data from the first request has returned.
Interfaces 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next.
Interfaces Table 2-10.
Interfaces Table 2-11. Interleave (IL) and Non-Interleave (NIL) Modes Pin Mapping (Sheet 2 of 2) IL (DDR4) NIL (DDR4, LPDDR3) Channel Byte Channel Byte DDR1 Byte0 DDR0 Byte2 DDR1 Byte1 DDR0 Byte3 DDR1 Byte2 DDR0 Byte6 DDR1 Byte3 DDR0 Byte7 DDR1 Byte4 DDR1 Byte2 DDR1 Byte5 DDR1 Byte3 DDR1 Byte6 DDR1 Byte6 DDR1 Byte7 DDR1 Byte7 Figure 2-2. Interleave (IL) and Non-Interleave (NIL) Modes Mapping 2.1.
Interfaces 2.1.11 DRAM Reference Voltage Generation The memory controller has the capability of generating the LPDDR3 and DDR4 Reference Voltage (VREF) internally for both read and write operations. The generated VREF can be changed in small steps, and an optimum VREF value is determined for both during a cold boot through advanced training procedures in order to provide the best voltage to achieve the best signal margins. 2.1.
Interfaces Table 2-12.
Interfaces • Power Management Event (PME) functions. • Dynamic width capability. • Message Signaled Interrupt (MSI and MSI-X) messages. • Lane reversal • Full Advance Error Reporting (AER) and control capabilities are supported only on Server SKUs. The following table summarizes the transfer rates and theoretical bandwidth of PCI Express* link. Table 2-13.
Interfaces 2.2.3 PCI Express* Configuration Mechanism The PCI Express* (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-3. PCI Express* Related Register Structures in the Processor PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the conventional PCI specification.
Interfaces • Full RX Equalization and acquisition for: AGC (Adaptive Gain Control), CDR (Clock and Data Recovery), adaptive DFE (decision feedback equalizer) and adaptive CTLE peaking (continuous time linear equalizer). • Full adaptive phase 3 EQ compliant with PCI Express* Gen 3 specification. Refer the PCI Express* Base Specification 3.0 for details on PCI Express* equalization. 2.3 Direct Media Interface (DMI) Note: The DMI interface is only present in 2-Chip platform processors.
Interfaces Figure 2-4. Example for DMI Lane Reversal Connection Notes: 1. DMI Lane Reversal is supported only on CNP PCH-H and not on the Processor. 2. L[7:0] - Processor and PCH DMI Controller Logical Lane Numbers. 3. P[7:0] - Processor and PCH DMI Package Pin Lane Numbers. 2.3.2 DMI Error Flow DMI can only generate SERR in response to errors; never SCI, SMI, MSI, PCI INT, or GPE. Any DMI related SERR activity is associated with Device 0. 2.3.
Interfaces 2.4 Processor Graphics The processor graphics is based on Gen 9 LP (generation 9 Low Power) graphics core architecture that enables substantial gains in performance and lower-power consumption over prior generations. Gen 9 LP architecture supports up to 48 Execution Units (EUs) with On-Package Cache depending on the processor SKU.
Interfaces 2.4.2.1 Hardware Accelerated Video Decode Gen 9 LP implements a high-performance and low-power HW acceleration for video decoding operations for multiple video codecs. The HW decode is exposed by the graphics driver using the following APIs: • Direct3D* 9 Video API (DXVA2) • Direct3D11 Video API • Intel Media SDK • MFT (Media Foundation Transform) filters. Gen 9 LP supports full HW accelerated video decoding for AVC/VC1/MPEG2/HEVC/VP8/ JPEG. Table 2-14.
Interfaces Table 2-15. Hardware Accelerated Video Encode Codec Profile Level Maximum Resolution MPEG2 Main High 1080p AVC/H264 High Main L5.1 2160p(4K) VP8 Unified profile Unified level — JPEG Baseline — 16Kx16K Main L5.1 2160p(4K) Support 8 bits 4:2:0 BT2020 may be obtained the pre/post processing — — HEVC/H265 VP9 Note: Hardware encode for H264 SVC is not supported. 2.4.2.
Interfaces Expected performance: • U-Processor Line: 12x 1080p30 RT (same as previous generation). • H-Processor Line: 18x 1080p30 RT (same as previous generation). • S-Processor Line: 18x 1080p30 RT (same as previous generation). Note: Actual performance depends on Processor Line, video processing algorithms used, content bit rate, and memory frequency. 2.4.3 Switchable/Hybrid Graphics The processor supports Switchable/Hybrid graphics.
Interfaces 2.4.4 Gen 9 LP Video Analytics There is HW assist for video analytics filters such as scaling, convolve 2D/1D, minmax, 1P filter, erode, dilate, centroid, motion estimation, flood fill, cross correlation, Local Binary Pattern (LBP). Figure 2-5.
Interfaces 2.4.5 Gen 9 LP (9th Generation Low Power) Block Diagram Figure 2-6. Gen 9 LP Block Diagram 2.4.6 GT2/3 Graphic Frequency Table 2-17.
Interfaces 2.5 Display Interfaces 2.5.1 DDI Configuration The processor supports single eDP* interface and 2 or 3 DDI interfaces (depends on segment). Table 2-18. DDI Ports Availability Ports Port Name in VBT U-Processor Line2,3 H-Processor Line 2,3 S-Processor Line2,3 DDI0 - eDP Port A Yes Yes Yes DDI1 Port B Yes Yes Yes DDI2 Port C Yes Yes Yes DDI3 Port D No4 Yes Yes DDI4 - eDP/VGA Port E No Yes1 Yes1 Notes: 1. For more information, Refer Section 2.5.
Interfaces Table 2-19. VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary Port U/Y-Processor Line eDP - DDIA (eDP lower x2 lanes, [1:0]) N/A VGA - DDIE2 (DP upper x2 lanes, [3:2]) N/A Notes: 1. Requires a DP to VGA converter. 2. DP-to-VGA converter on the processor ports is supported using external dongle only, display driver software for VGA dongles which configures the VGA port as a DP branch device. Table 2-20.
Interfaces Table 2-23. Embedded DisplayPort* (eDP*)/DDI Ports Availability (Sheet 2 of 2) Ports Port name in VBT U/Y-Processor Line DDI1 Port B Yes DDI2 Port C Yes DDI3 Port D No4 DDI4 - eDP/VGA Port E No 2,3 Notes: 1. Port E is bifurcated from eDP, when VGA is used, needs to use available AUX (if HDMI* is in used). a. For example, DT can use eDP_AUX for VGA converter which is available as free Design but HPD should be used as DDPE_HPD3. 2.
Interfaces 2.5.3 Display Technologies Table 2-26. Display Technologies Support Technology Standard eDP* 1.4 VESA* Embedded DisplayPort* Standard 1.4 DisplayPort* 1.2 VESA DisplayPort* Standard 1.2 VESA DisplayPort* PHY Compliance Test Specification 1.2 VESA DisplayPort* Link Layer Compliance Test Specification 1.2 HDMI* 1.41 High-Definition Multimedia Interface* Specification Version 1.4 Notes: 1. HDMI* 2.0/2.0a support is possible using LS-Pcon converter chip connected to the DP port.
Interfaces Table 2-27. Display Resolutions and Link Bandwidth for Multi-Stream Transport Calculations (Sheet 2 of 2) Pixels per Line Lines Refresh Rate [Hz] Pixel Clock [MHz] Link Bandwidth [Gbps] 3840 2160 30 262.75 7.88 2560 1600 60 268.5 8.06 2880 1800 60 337.5 10.13 3200 2400 60 497.75 14.93 3840 2160 60 533.25 16.00 4096 2160 60 556.75 16.70 4096 2304 60 605 18.15 Notes: 1. All above is related to bit depth of 24. 2.
Interfaces Figure 2-7. Processor Display Architecture (With 3 DDI Ports as an Example) Display is the presentation stage of graphics. This involves: • Pulling rendered data from memory • Converting raw data into pixels • Blending surfaces into a frame • Organizing pixels into frames • Optionally scaling the image to the desired size • Re-timing data for the intended target • Formatting data according to the port output standard 2.5.
Interfaces Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link management and device control. The Hot-Plug Detect (HPD) signal serves as an interrupt request for the sink device. The processor is designed in accordance to VESA* DisplayPort* specification. Refer to Table 2-26. Figure 2-8. DisplayPort* Overview 2.5.
Interfaces Figure 2-9. HDMI* Overview 2.5.6 Digital Video Interface (DVI) The processor Digital Ports can be configured to drive DVI-D. DVI uses TMDS for transmitting data from the transmitter to the receiver, which is similar to the HDMI* protocol except for the audio and CEC. Refer to the HDMI* section for more information on the signals and data transmission.
Interfaces Table 2-28. Processor Supported Audio Formats Over HDMI* and DisplayPort* Audio Formats HDMI* DisplayPort* AC-3 Dolby* Digital Yes Yes Dolby* Digital Plus Yes Yes DTS-HD* Yes Yes LPCM, 192 kHz/24 bit, 8 Channel Yes Yes Dolby* TrueHD, DTS-HD Master Audio* (Lossless Blu-Ray Disc* Audio Format) Yes Yes The processor will continue to support Silent stream.
Interfaces Table 2-29. Maximum Display Resolution (Sheet 2 of 2) Standard U-Processor Line H/S-Processor Line Notes Notes: 1. Maximum resolution is based on implementation of 4 lanes with HBR2 link data rate. 2. bpp - bit per pixel. 3. S-Processor Line and H-Processor Line support up to 4 displays, but only three can be active at the same time. N/A for U-processor line. 4. The resolutions are assumed at max VCCSA. 5.
Interfaces Table 2-32. HDCP Display supported Implications Table Topic DP HDMI*1.4 HDR1 HDCP Solution2 4K@60 No iHDCP 10 bit Legacy Integrated for HDCP1.4 4K@60 Yes iHDCP 10 bit New Integrated for HDCP2.2 HDCP1.4 4K@30 No iHDCP 8 bit Legacy Integrated for HDCP1.4 HDCP2.2 4K@30 No LSPCON 8 bit LSPCON HDCP2.2 required New Integrated for HDCP2.2 HDCP Revision Maximum Resolution HDCP1.4 HDCP2.2 BPC3 Comments HDCP2.2 4K@30 No iHDCP 8 bit HDMI*2.0 HDCP2.
Interfaces 2.5.13 Table 2-35. Display Bit Per Pixel (BPP) Support Display Bit Per Pixel (BPP) Support Technology eDP* 24,30,36 DisplayPort* 24,30,36 HDMI* 2.5.14 Table 2-36. 24,36 Display Resolution per Link Width Supported Resolutions for HBR (2.7 Gbps) by Link Width Link Width Table 2-37. Max Link Bandwidth [Gbps] Max Pixel Clock (theoretical) [MHz] U/H/S-Processor Lines 4 lanes 10.8 360 2880x1800 @ 60 Hz, 24bpp 2 lanes 5.4 180 2048x1280 @ 60 Hz, 24bpp 1 lane 2.
Interfaces • PECI EC Connection. Figure 2-10.
Interfaces Figure 2-11.
Technologies 3 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor. The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site: http://www.intel.com/technology/ 3.
Technologies • More secure: The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system.
Technologies to translate the linear address), the resulting guest-physical address is executable under EPT only if the XS bit is set in every EPT pagingstructure entry used to translate the guest-physical address —The XU and XS bits are used only when translating linear addresses for guest code fetches.
Technologies • DMA remapping: for supporting independent address translations for Direct Memory Accesses (DMA) from devices. • Interrupt remapping: for supporting isolation and routing of interrupts from devices and external interrupt controllers to appropriate VMs. • Reliability: for recording and reporting to system software DMA and interrupt errors that may otherwise corrupt memory or impact VM isolation.
Technologies Intel VT-d functionality, often referred to as an Intel VT-d Engine, has typically been implemented at or near a PCI Express* host bridge component of a computer system. This might be in a chipset component or in the PCI Express functionality of a processor with integrated I/O. When one such VT-d engine receives a PCI Express transaction from a PCI Express bus, it uses the B/D/F number associated with the transaction to search for an Intel VT-d translation table.
Technologies • Intel VT-d superpage – support of Intel VT-d superpage (2 MB, 1 GB) for default Intel VT-d engine (that covers all devices except IGD). IGD Intel VT-d engine does not support superpage and BIOS should disable superpage in default Intel VT-d engine when iGfx is enabled. Note: Intel VT-d Technology may not be available on all SKUs. 3.2 Security Technologies 3.2.
Technologies For the above features, BIOS should test the associated capability bit before attempting to access any of the above registers. For more information, refer to the Intel® Trusted Execution Technology Measured Launched Environment Programming Guide Note: Intel TXT Technology may not be available on all SKUs. 3.2.
Technologies 3.2.5 Execute Disable Bit The Execute Disable Bit allows memory to be marked as non executable when combined with a supporting operating system. If code attempts to run in nonexecutable memory, the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can, thus, help improve the overall security of the system.
Technologies 3.2.9 Intel® Memory Protection Extensions (Intel® MPX) Intel® MPX provides hardware accelerated mechanism for memory testing (heap and stack) buffer boundaries in order to identify buffer overflow attacks. An Intel MPX enabled compiler inserts new instructions that tests memory boundaries prior to a buffer access. Other Intel MPX commands are used to modify a database of memory regions used by the boundary checker instructions.
Technologies • Supported protected memory sizes: — Supports 32, 64 and 128MB. For more information, refer to the Intel® SGX website at: https://software.intel.com/en-us/sgx Intel® SGX specifications and functional descriptions are included in the Intel® 64 Architectures Software Developer’s Manual, Volume 3. Available at: http://www.intel.com/products/processor/manuals 3.2.11 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Refer to Section 3.1.2 Intel VT-d for detail. 3.
Technologies • The number of processor IA cores operating in the C0 state. • The estimated processor IA core current consumption and ICCMax register settings. • The estimated package prior and present power consumption and turbo power limits. • The package temperature. • Sustained turbo residencies at high voltages and temperature. Any of these factors can affect the maximum frequency for a given workload.
Technologies 3.3.5 Intel® 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides key mechanisms for interrupt delivery. This extension is primarily intended to increase processor addressability.
Technologies • The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new operating system and a new BIOS are both needed, with special support for x2APIC mode. • The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendible for future Intel platform innovations. Note: Intel x2APIC Technology may not be available on all SKUs.
Power Management 4 Power Management This chapter provides information on the following power management topics: • Advanced Configuration and Power Interface (ACPI) States • Processor IA Core Power Management • Integrated Memory Controller (IMC) Power Management • PCI Express* Power Management • Direct Media Interface (DMI) Power Management • Processor Graphics Power Management Notes: • The PCI Express* and DMI interfaces are present only on H and S-Processor Line.
Power Management Figure 4-1.
Power Management Figure 4-2. Processor Package and IA Core C-States 4.1 Advanced Configuration and Power Interface (ACPI) States Supported This section describes the ACPI states supported by the processor. Table 4-1. System States State Description G0/S0 Full On G1/S3-Cold Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor). G1/S4 Suspend-to-Disk (STD). All power lost (except wake-up on PCH). G2/S5 Soft off. All power lost (except wake-up on PCH).
Power Management Table 4-2. Processor IA Core / Package State Support State C0 Description Active mode, processor executing code. C1 AutoHALT processor IA core state (package C0 state). C1E AutoHALT processor IA core state with lowest frequency and voltage operating point (package C0 state). C2 All processor IA cores in C3 or deeper. Memory path open. Temporary state before Package C3 or deeper.
Power Management Table 4-6. 4.
Power Management 4.2.1.2 Intel® Speed Shift Technology Intel Speed Shift Technology is an energy efficient method of frequency control by the hardware rather than relying on OS control. OS is aware of available hardware P-states and request a desired P-state or it can let Hardware determine the P-state. The OS request is based on its workload requirements and awareness of processor capabilities.
Power Management 4.2.3 Requesting Low-Power Idle States The primary software interfaces for requesting low-power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E). However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx.
Power Management A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. Refer the Intel 64 and IA-32 Architectures Software Developer’s Manual for more information. While a processor IA core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E, Refer Section 4.2.5.
Power Management This feature is disabled by default. BIOS should enable it in the PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by this register. 4.2.5 Package C-States The processor supports C0, C2, C3, C6, C7, C8, C9, and C10 package states. The following is a summary of the general rules for package C-state entry.
Power Management Figure 4-4. Package C-State Entry and Exit Package C0 This is the normal operating state for the processor. The processor remains in the normal state when at least one of its processor IA cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low-power state. Individual processor IA cores may be in deeper power idle states while the package is in C0 state.
Power Management Package C6 State A processor enters the package C6 low-power state when: • At least one processor IA core is in the C6 state. • The other processor IA cores are in a C6 or deeper power state, and the processor has been granted permission by the platform. • The platform has not granted a package C7 or deeper request but has allowed a C6 package state. In package C6 state, all processor IA cores have saved their architectural state and have had their voltages reduced to zero volts.
Power Management InstantGo InstantGo is a platform state. On display time out the OS requests the processor to enter package C10 and platform devices at RTD3 (or disabled) in order to attain low power in idle. Dynamic LLC Sizing When all processor IA cores request C7 or deeper C-state, internal heuristics dynamically flushes the LLC. Once the processor IA cores enter a deep C-state, depending on their MWAIT sub-state request, the LLC is either gradually flushed Nways at a time or flushed all at once.
Power Management 4.3 Integrated Memory Controller (IMC) Power Management The main memory is power managed during normal operation and in low-power ACPI C-states. 4.3.1 Disabling Unused System Memory Outputs Any system memory (SM) interface signal that goes to a memory in which it is not connected to any actual memory devices (such as SODIMM connector is unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM signals are: • Reduced power consumption.
Power Management better than APD, but less than DLL-off. Power consumption is defined by IDD2P. Exiting this mode is defined by tXP. The difference from APD mode is that when waking-up, all page-buffers are empty.) The LPDDR does not have a DLL. As a result, the power savings are as good as PPD/DDL-off but will have lower exit latency and higher performance. The CKE is determined per rank, whenever it is inactive. Each rank has an idle counter.
Power Management When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh, the processor IA core flushes pending cycles and then enters SDRAM ranks that are not used by the processor graphics into self-refresh. The CKE signals remain LOW so the SDRAM devices perform self-refresh. The target behavior is to enter self-refresh for package C3 or deeper power states as long as there are no memory requests to service. Table 4-8. Targeted Memory State Conditions State 4.3.2.
Power Management In C7 or deeper power state, the processor internally gates VCCIO for all non-critical state to reduce idle power. In S3 or C-state transitions, the DDR does not go through training mode and will restore the previous training information. 4.3.4 Power Training BIOS MRC performing Power Training steps to reduce DDR I/O power while keeping reasonable operational margins, still ensuring platform operation.
Power Management 4.5 Direct Media Interface (DMI) Power Management • Active power management support using L1 state. Note: The PCI Express* and DMI interfaces are present only in 2-Chip platform processors. 4.6 Processor Graphics Power Management 4.6.1 Memory Power Savings Technologies 4.6.1.
Power Management in Lux, (current ambient light illuminance), the new backlight setting can be adjusted through BLC. The converse applies for a brightly lit environment. Intel Automatic Display Brightness increases the backlight setting. 4.6.2.3 Smooth Brightness The Smooth Brightness feature is the ability to make fine grained changes to the screen brightness.
Power Management 4.6.3 Processor Graphics Core Power Savings Technologies 4.6.3.1 Intel® Graphics Dynamic Frequency Intel® Turbo Boost Technology 2.0 is the ability of the processor IA cores and graphics (Graphics Dynamic Frequency) cores to opportunistically increase frequency and/or voltage above the guaranteed processor and graphics frequency for the given part.
Power Management 4.8 Voltage Optimization Voltage Optimization opportunistically provides reduction in power consumption, that is, a boost in performance at a given PL1. Over time the benefit is reduced. There is no change to base frequency or turbo frequency. During system validation and tuning, this feature should be disabled to reflect processor power and performance that is expected over time. This feature is available on selected SKUs. 4.
Thermal Management 5 Thermal Management 5.1 Processor Thermal Management The thermal solution provides both component-level and system-level thermal management. To allow optimal operation and long-term reliability of Intel processorbased systems, the system/processor thermal solution should be designed so that the processor: • Bare Die Parts: Remains below the maximum junction temperature (TjMAX) specification at the maximum thermal design power (TDP).
Thermal Management • Applications are expected to run closer to TDP more often as the processor will attempt to maximize performance by taking advantage of estimated available energy budget in the processor package. • The processor may exceed the TDP for short durations to utilize any available thermal capacitance within the thermal solution. The duration and time of such operation can be limited by platform runtime configurable registers within the processor.
Thermal Management • Turbo Time Parameter (Tau): An averaging constant used for PL1 exponential weighted moving average (EWMA) power calculation. Note: Implementation of Intel® Turbo Boost Technology 2.0 only requires configuring PL1, PL1 Tau, and PL2. Note: PL3 and PL4 are disabled by default. Figure 5-1. Package Power Control 5.1.3.2 Platform Power Control The processor supports Psys (Platform Power) to enhance processor power management.
Thermal Management • PsysPL1 Tau: An averaging constant used for PsysPL1 exponential weighted moving average (EWMA) power calculation. • The Psys signal and associated power limits / Tau are optional for the system designer and disabled by default. • The Psys data will not include power consumption for charging. 5.1.3.3 Turbo Time Parameter (Tau) Turbo Time Parameter (Tau) is a mathematical parameter (units of seconds) that controls the Intel® Turbo Boost Technology 2.0 algorithm.
Thermal Management Table 5-1. Configurable TDP Modes Mode Description Base The average power dissipation and junction temperature operating condition limit, specified in Table 5-2 and Table 5-5 for the SKU Segment and Configuration, for which the processor is validated during manufacturing when executing an associated Intelspecified high-complexity workload at the processor IA core frequency corresponding to the configuration and SKU.
Thermal Management 5.1.5 Thermal Management Features Occasionally the processor may operate in conditions that are near to its maximum operating temperature. This can be due to internal overheating or overheating within the platform. In order to protect the processor and the platform from thermal failure, several thermal management features exist to reduce package power consumption and thereby temperature in order to remain within normal operating limits.
Thermal Management be subtracted from the TjMAX value and used as a new max temperature set point for Adaptive Thermal Monitoring. This will have the same behavior as in prior products to have TCC activation and Adaptive Thermal Monitor to occur at this lower target silicon temperature.
Thermal Management • If the P-state target frequency is lower than the processor IA core optimized target frequency, the processor will transition to the P-state operating point. 5.1.5.1.3 Clock Modulation If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor event, the Adaptive Thermal Monitor will utilize clock modulation.
Thermal Management point. When a package DTS indicates that it has reached the TCC activation (a reading of 0x0, except when the TCC activation offset is changed), the TCC will activate and indicate an Adaptive Thermal Monitor event. A TCC activation will lower both processor IA core and graphics core frequency, voltage, or both. Changes to the temperature can be detected using two programmable thresholds located in the processor thermal MSRs.
Thermal Management 5.1.5.5 Voltage Regulator Protection Using PROCHOT# PROCHOT# may be used for thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and assert PROCHOT# and, if enabled, activate the TCC when the temperature limit of the VR is reached.
Thermal Management interrupt, if enabled. For more details on the interrupt mechanism, refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual or appropriate processor family BIOS Specification (Refer Related Documents section). 5.1.5.10 On-Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption using clock modulation.
Thermal Management DDR4 temperature may be acquired through an on-board thermal sensor (TS-onBoard), retrieved by an embedded controller and reported to the processor through the PECI 3.1 interface. This methodology is known as PECI injected temperature. This is a method of Closed Loop Thermal Management (CLTM). The following notes apply only to Table 5-2, Table 5-4 and Table 5-5.
Thermal Management 5.2 H/U-Processor Line Thermal and Power Specifications Table 5-2. TDP Specifications (H/U-Processor Line) Segment and Package HProcessor Line BGA Processor IA Cores, Graphics Configuration and TDP Configuration Processor IA Core Frequency Base 2.0 GHz to 2.9 GHz 6-Core GT2 45W Configurable TDP-Down 1.6 GHz to 2.4GHz LPM 0.8 GHz Base 2.3 GHz to 3.0 GHz 4-Core GT2 45W UProcessor Line BGA UProcessor Line BGA Note: 4-Core GT3 28W with OPC 2-Core GT3 28W with OPC 1.
Thermal Management Table 5-4. Junction Temperature Specifications Segment Symbol Package Turbo Parameter Temperature Range TDP Specification Temperature Range Min Max Min Max Units Notes H-Processor Line BGA Tj Junction temperature limit 0 100 35 100 ºC 1, 2 U-Processor Line + OPC BGA Tj Junction temperature limit 0 100 35 100 ºC 1, 2 Notes: 1. The thermal solution needs to ensure that the processor temperature does not exceed the TDP Specification Temperature. 2.
Thermal Management Table 5-5. TDP Specifications (S-Processor Line) (Sheet 2 of 2) Segment and Package Processor IA Cores, Graphics Configuration and TDP Processor IA Core Frequency Base 3.6 GHz LFM 0.8 GHz Base 3.7 GHz 1.05 GHz 58 LFM 0.8 GHz 0.35 GHz N/A 3.1 GHz to 3.9 GHz 1.05 GHz to 1.1 GHz 54 0.8 GHz 0.
Thermal Management Table 5-6. Low Power and TTV Specifications (S-Processor Line) (Sheet 2 of 2) Processor IA Cores, Graphics Configuration and TDP TTV TDP (W) 2-Core GT2/GT1 35W 6,7 Min TCASE (°C) Max TTV TCASE (°C) 0 66 35 Notes: 1. The package C-state power is the worst case power in the system configured as follows: a. Memory configured for DDR4 2400 and populated with two DIMMs per channel. b. DMI and PCIe links are at L1 2. Specification at DTS = 50 °C and minimum voltage loadline. 3.
Thermal Management Table 5-7. Segment and Package Package Turbo Specifications (S-Processor Lines) (Sheet 2 of 2) Processor IA Cores, Graphics, Configuration and TDP 4-Core GT2 62W Parameter Min. SProcessor Line 2-Core GT2/GT1 54W 6-Core GT2 35W 2-Core GT2/GT1 35W Table 5-8. Segment Max Units Power Limit 1 Time (PL1 Tau) 0.1 1 8 S Power Limit 1 (PL1) N/A 62 N/A W N/A PPL1* 1.25 N/A W Power Limit 2 (PL2) 2-Core GT2/GT1 58W Hardware Default Power Limit 1 Time (PL1 Tau) 0.
Thermal Management Table 5-9.
Signal Description 6 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The notations in the following table are used to describe the signal type. The signal description also includes the type of buffer used for the particular signal (Refer the following table). Table 6-1.
Signal Description Table 6-2. LPDDR3 Memory Interface (Sheet 2 of 2) Description Dir. Buffer Type Link Type DDR0_CKE[3:0] DDR1_CKE[3:0] Clock Enable: (1 per rank) These signals are used to: • Initialize the SDRAMs during power-up. • Power-down SDRAM ranks. • Place all SDRAM ranks into and out of selfrefresh during STR. O LPDDR3 SE U and H -Processor Line DDR0_CS#[1:0] DDR1_CS#[1:0] Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state.
Signal Description Table 6-3. DDR4 Memory Interface (Sheet 2 of 2) Signal Name Description DDR0_CS#[3:0][1:0] DDR1_CS#[3:0][1:0] Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank. Dir. O Buffer Type DDR4 Link Type Availability SE [1:0] applicable for All Processor Lines. [3:2] applicable only in S and H-Processor Line processors O DDR4 SE [0,1] applicable for All Processor Lines.
Signal Description Table 6-4. System Memory Reference and Compensation Signals Signal Name DDR_RCOMP[2:0] Description System Memory Resistance Compensation: On-Package Cache resistance Compensation from processor: Note: Unconnected for Processors without OPC. OPC_RCOMP Note: OPCE_RCOMP On-Package Cache resistance Compensation from OPC: Unconnected for Processors without OPC. System Memory Power Gate Control: When signal is high – platform memory VTT regulator is enable, output high.
Signal Description 6.4 Reset and Miscellaneous Signals Table 6-7. Reset and Miscellaneous Signals Signal Name CFG[19:0] Description Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. Intel recommends placing test points on the board for CFG pins. • CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted: — 1 = (Default) Normal Operation; No stall. — 0 = Stall. • CFG[1]: Reserved configuration lane.
Signal Description 6.5 embedded DisplayPort* (eDP*) Signals Table 6-8. embedded DisplayPort* Signals Signal Name Description Dir. Buffer Type Link Type Availability eDP_TXP[3:0] eDP_TXN[3:0] embedded DisplayPort* Transmit: differential pair. O eDP Diff All Processor Lines eDP_AUXP eDP_AUXN embedded DisplayPort* Auxiliary: Half-duplex, bidirectional channel consist of one differential pair.
Signal Description 6.7 Processor Clocking Signals Table 6-10. Processor Clocking Signals Signal Name Description Dir. Buffer Type Link Type BCLKP BCLKN 100 MHz Differential bus clock input to the processor I Diff CLK24P CLK24N 24 MHz Differential bus clock input to the processor I Diff PCI_BCLKP PCI_BCLKN 100 MHz Clock for PCI Express* logic I Diff 6.8 Availability H and S-Processor Line Testability Signals Table 6-11. Testability Signals Description Dir.
Signal Description 6.9 Error and Thermal Protection Signals Table 6-12. Error and Thermal Protection Signals Description Dir. Buffer Type Link Type CATERR# Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this signal for non-recoverable machine check errors or other unrecoverable internal errors.
Signal Description Table 6-13. Power Sequencing Signals (Sheet 2 of 2) Signal Name Description Dir. Buffer Type Link Type PROC_DETECT# /SKTOCC# Processor Detect / Socket Occupied: Pulled down directly (0 Ohms) on the processor package to the ground. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present.
Signal Description Table 6-14. Processor Power Rails Signals (Sheet 2 of 2) Dir. Buffer Type Link Type Vcc_SENSE N/A Power — All Processor Lines VccGT_SENSE N/A Power — All Processor Lines Signal Name Description VccIO_SENSE Availability N/A Power — All Processor Lines N/A Power — All Processor Lines VccOPC_SENSE N/A Power — Processors w/ OnPackage Cache VccEOPIO_SENSE N/A Power — Processors w/ OnPackage Cache Dir.
Signal Description Table 6-16. GND, RSVD, and NCTF Signals Signal Name 6.13 Description Vss Processor ground node Vss_NCTF Non-Critical To Function: These signals are for package mechanical reliability. RSVD Reserved: All signals that are RSVD should not be connected on the board. RSVD_NCTF Reserved Non-critical To Function: RSVD_NCTF should not be connected on the board. RSVD_TP Test Point: Intel recommends to route each RSVD_TP to an accessible test point.
Electrical Specifications 7 Electrical Specifications 7.1 Processor Power Rails Table 7-1.
Electrical Specifications Individual processor VID values may be set during manufacturing so that two devices at the same processor IA core frequency may have different default VID settings. This is shown in the VID range values in Section 7.2. The processor provides the ability to operate while transitionally to an adjacent VID and its associated voltage. This will represent a DC shift in the loadline. 7.
Electrical Specifications Table 7-2.
Electrical Specifications Table 7-2. Symbol DC_LL (SProcessors ) Processor IA core (Vcc) Active and Idle Mode DC Voltage and Current Specifications (Sheet 3 of 3) Parameter Min Typ Max Unit Note1 S-Processor Line 8-Core GT2/GT0, (95W) — — 1.6 m 10, 13, 14 S-Processor Line 6-Core GT2/GT0 — — 2.1 m 10, 13, 14 S-Processor Line - 4-Core GT2/GT0 — — 2.1 m 10, 13, 14 S-Processor Line 2-Core GT2/GT1 — — 2.
Electrical Specifications Table 7-3.
Electrical Specifications Table 7-3. Symbol Processor Graphics (VccGT) Supply DC Voltage and Current Specifications (Sheet 3 of 3) Parameter Segment U-4-Core GT3+OPC U-2-Core GT3+OPC H- 6/4-Core GT2 S-8-Core GT2/GT0, S-6Core GT2/GT0 S-4-Core GT2/GT0 S-2-Core GT2/GT1 DC_LL VccGT Loadline slope AC_LL (UHSProcessors) AC Loadline T_OVS_MA X Max Overshoot time — V_OVS_MA X Max Overshoot — UHS-Processor Line Min Typ Max Unit Note1 — — — — — — — — — — — — — — 2 2 2.7 3.1 3.1 3.1 3.
Electrical Specifications Table 7-4. Memory Controller (VDDQ) Supply DC Voltage and Current Specifications (Sheet 2 of 2) Symbol IccMAX_VDDQ (DDR4) Parameter Segment Min Typ Max Unit Note1 U H S — — 3.3 3.3 3.3 A 2 Max Current for VDDQ Rail (DDR4) Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2.
Electrical Specifications Table 7-5. Symbol System Agent (VccSA) Supply DC Voltage and Current Specifications (Sheet 2 of 2) Parameter Segment Min Typ Max Unit Note1, 2 Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits. 3.
Electrical Specifications Table 7-7. VCCOPC ,VCCEOPIOVoltage Levels ZVM# State MSM# State VCCOPC 0 N/A 0 1 N/A 1.0 0 x 0 1 1 1.0 VccOPC VccEOPIO Table 7-8. Units V V Processor OPC (VccOPC), Processor EOPIO (VccEOPIO) Supply DC Voltage and Current Specifications Symbol Parameter VccOPC Voltage for the On-Package Cache. VccEOPIO Voltage for the EOPIO interface TOB OPIO, OEOPIO Segment Processor Line w/OPC Note1, Min Typ Max Unit — 1.
Electrical Specifications Table 7-9. Processor OPC (VccOPC_1p8) Supply DC Voltage and Current Specifications (Sheet 2 of 2) Symbol Parameter Segment Min Typ Max Unit Note1,2 Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
Electrical Specifications 7.2.1.9 VccPLL DC Specifications Table 7-12. Processor PLL (VccPLL) Supply DC Voltage and Current Specifications Symbol VccPLL Parameter PLL supply voltage (DC + AC specification) Segment Min Typ Max All with Intel® 300 Series Chipset Families PCH 1 1.05 1.
Electrical Specifications Table 7-13. Processor PLL_OC (VccPLL_OC) Supply DC Voltage and Current Specifications (Sheet 2 of 2) Symbol Parameter Segment Min Typ Max Un it Notes1,2 Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2.
Electrical Specifications Table 7-14. LPDDR3 Signal Group DC Specifications (Sheet 2 of 2) H and U -Processor Line Symbol Parameter Unit Min Typ Note Max Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4.
Electrical Specifications Table 7-15. DDR4 Signal Group DC Specifications (Sheet 2 of 2) USH-Processor Line Symbol Parameter Min DDR_RCOMP[0] Typ ODT resistance compensation DDR_RCOMP[1] Data resistance compensation DDR_RCOMP[2] Command resistance compensation Units Notes1 6 6 6 Max RCOMP values are memory topology dependent. Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
Electrical Specifications Table 7-17. Digital Display Interface Group DC Specifications (DP/HDMI*) (Sheet 2 of 2) Symbol ZTX-DIFF-DC Parameter DC Differential Tx Impedance Min Typ Max Units 80 100 120 Notes1 Notes: 1. VccIO depends on segment. 2. VOL and VOH levels depends on the level chosen by the Platform. 7.2.2.5 embedded DisplayPort* (eDP*) DC Specification Table 7-18.
Electrical Specifications Table 7-20. GTL Signal Group and Open Drain Signal Group DC Specifications (Sheet 2 of 2) Symbol Min Max Units Notes1 Vcc * 0.72 — V 2, 4, 5, 6 Parameter VIH Input High Voltage (TAP, except PROC_TCK, PROC_TRST#) VIL Input Low Voltage (PROC_TCK,PROC_TRST#) — Vcc * 0.3 V 2, 5, 6 VIH Input High Voltage (PROC_TCK,PROC_TRST#) Vcc * 0.3 — V 2, 4, 5, 6 VHYSTERESIS Hysteresis Voltage Vcc * 0.
Electrical Specifications Table 7-21. PECI DC Electrical Limits (Sheet 2 of 2) Symbol Definition and Conditions Min Max Units Notes1 Notes: 1. VccST supplies the PECI interface. PECI behavior does not affect VccST min/max specifications. 2. The leakage specification applies to powered devices on the PECI bus. 3. The PECI buffer internal pull up resistance measured at 0.75* VccST.
Package Mechanical Specifications 8 Package Mechanical Specifications 8.1 Package Mechanical Attributes The U and H-Processor Line use a Flip Chip technology available in a Ball Grid Array (BGA) package. The S-Processor Line uses a Flip Chip technology available in Land Grid Array (LGA). The following table provides an overview of the mechanical attributes of the package. 8.2 Package Loading Specifications Table 8-1.
Package Mechanical Specifications Table 8-2. Package Loading Specifications Maximum Static Normal Load U-Processor Line H-Processor Line Limit Minimum PCB Thickness Assumptions Notes 67 N (15 lbf) 0.8 mm 1, 2, 3 67 N (15 lbf) 1.0 mm 1, 2, 3 111 N (25 lbf) 1.0 mm 1, 2, 3, 4 Notes: 1. The thermal solution attach mechanism should not induce continuous stress to the package. It may only apply a uniform load to the die to maintain a thermal interface.
