R Mobile Intel® Celeron® Processor (0.18µ and 0.13µ) Specification Update November 2006 Version 054 Notice: The mobile Intel® Celeron® processor (0.18µ and 0.13µ) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
R INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
R Contents Revision History................................................................................................................... 4 Preface ................................................................................................................................ 7 Summary of Changes........................................................................................................ 13 Identification Information ..........................................................................
R Revision History Revision Number 4 Description Date -001 Initial release -002 Revised Errata M38, M43, and M47. Added Erratum M53. Added new Specification Clarification M1. -003 Updated the Preface with new references; Updated “Intel Celeron Processor Mobile Module Markings” section; Updated Identification Information for BGA2, micro-PGA2 packages, and mobile modules; Updated Erratum M34; Added Erratum M54; Added Documentation Change M5; Added Specification Clarifications M2, M3.
R Revision Number Description Date -019 Updated Summary of Changes; Added Erratum M68 and M69; Added Documentation Change M18. August 2001 -020 Updated list of referenced documents in the preface; Updated the Celeron® mark to a registered trademark; Added micro-FCPGA and micro-FCBGA package marking diagrams for Mobile Intel Celeron Processor (0.18µ and 0.13µ) to general information section; Added identification information for Mobile Intel Celeron Processor (0.18µ and 0.
R Revision Number Description Date -040 Added errata M77-79 October 2004 -041 Added errata M80-82 November 2004 Updated errata M79 -042 Added errata M83-84 December 2004 -043 Updated erratum M68 March 2005 -044 Updated processor identification table April 2005 Added specification clarification M2 -045 Added errata M85 -046 Added erratum M86 and updated processor identification table. October 2005 -047 Added erratum M87 and M88.
R Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
R Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number. Errata are design defects or errors. Errata may cause the processor’s behavior to deviate from published specifications.
R Figure 2. Mobile Intel® Celeron® Processor (BGA2) Markings FPO Package Designator S-spec FFFFFFFF SXXX KC ZZZ/CCC Cache Speed INTEL M C ‘YY 2D Matrix (Supplier Lot ID + SER#) Legal (YY = Year) Figure 3. Mobile Intel® Celeron® Processor 0.
R Figure 4. Mobile Intel® Celeron® Processor 0.18µ (Micro-FCBGA) Markings FPO# S-spec# FFFFFFFF SXXXX PRODUCT DETAIL INTEL M C ‘YY 2D Matrix Legal Requirements (supplier Lot ID + SER#) Figure 5. Mobile Intel® Celeron® Processor 0.
R Figure 6. Mobile Intel® Celeron® Processor 0.13µ (Micro-FCBGA) Markings Figure 7. Intel® Celeron® Processor Mobile Module at 650 MHz, 600 MHz, 550 MHz, 500 MHz and 450 MHz The Product Tracking Code (PTC) determines the Intel assembly level of the module.
R Example: PMN70001201AA The PTC will consist of 13 characters as identified in the above example and can be broken down as follows: AABCCCDDEEEFF Definition: AA - Processor Module = PM B CCC DD EEE FF Celeron® Processor (.18μ) Mobile Module (MMC-2) = N Speed Identity = 700, 650, 600, 550, 500 or 450, etc.
R Summary of Changes The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to the Intel Mobile Celeron processor. Intel intends to fix some of the errata in a future stepping of the component and to account for the other outstanding issues through documentation or specification changes as noted.
R S = 64-bit Intel® Xeon™ processor with 800 MHz system bus T = Mobile Intel® Pentium® 4 processor – M U = Unannounced 64-bit Intel® Xeon™ processor MP V = Mobile Intel® Celeron® processor on 0.
MA2 BB0 PB0 MB0 BC0 PC0 MC0 BD0 PD0 FBDO FPDO FBA1 FPA1 FBB1 FPB1 Plans X X X X X X X X X X X X X X X X X NoFix LBER may be corrupted after some events M12 X X X X X X X X X X X X X X X X X NoFix BTMs may be corrupted during simultaneous L1 cache line replacement M13 X X X X X X X X X X X X X X X X X NoFix Near CALL to ESP creates unexpected EIP address M14 X X X X X X X X X X X X X X X X X No Fix Memory type undefined
FPB1 X X FPA1 M32 FBB1 X X FBA1 Plans FPDO M31 PD0 X BA2 X BD0 Processor will erroneously report a BIST failure X MC0 Fixed X PC0 X X X BC0 Performance counters include streaming SIMD extensions L1 prefetch PB0 Fixed MB0 X BB0 Machine check exception may occur due to improper line eviction in the IFU PA2 Fixed MA2 ERRATA M30 NO.
MA2 BB0 PB0 MB0 BC0 PC0 MC0 BD0 PD0 FBDO FPDO FBA1 FPA1 FBB1 FPB1 Plans X X X X X X X X X X X X X X X X X NoFix MOVD, CVTSI2SS, or PINSRW Following Zeroing Instruction Can Cause Incorrect Result M49 X X X X X X X X X X X X X X X X X NoFix FLUSH# assertion following STPCLK# may prevent CPU clocks from stopping M50 X X X Fixed Intermittent failure to assert ADS# during processor power-on M51 X X X Fixed Floating-point exception signal may be deferr
PA2 BB0 PB0 MB0 BC0 PC0 MC0 BD0 PD0 FBDO FPDO FBA1 FPA1 FBB1 FPB1 Plans X X X X X X X X X X X X X X X X X NoFix Wrong ESP Register Values During a Fault in VM86 Mode M66 X X X X X X X X X X X X X X X X X NoFix APIC ICR Write May Cause Interrupt Not to be Sent When ICR Delivery Bit Pending NoFix Processor Incorrectly Samples NMI Interrupt after RESET# Deassertion When Processor APIC is HardwareDisabled Fix The Instruction Fetch Unit (IFU) May Fetch Inst
Plans FPB1 FBB1 FPA1 FBA1 FPDO PD0 FBDO BD0 PC0 MC0 BC0 PB0 MB0 BB0 MA2 PA2 BA2 NO.
BD0 PD0 FBDO FPDO FBA1 X X X X X X X BB0 PB0 MB0 BC0 PC0 MC0 BD0 PD0 FBDO FPDO FBA1 FPA1 X FPB1 X FBB1 X Plans MC0 X FPB1 PC0 X ERRATA NoFix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Plans BC0 X FPA1 PB0 MB0 X FBB1 BB0 X PA2 MA2 PA2 X X BA2 NO. M94 MA2 NO.
R Identification Information The mobile Intel® Celeron® processor (0.18µ and 0.13µ) can be identified by the following values: Family1 Model 0110 1000 2 Brand ID 3 00000001 NOTE: 1. The Family corresponds to bits [11:8] of the EDX register after Reset, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2.
R S-Spec Product Stepping CPU Signature Speed (MHz) Core/Bus Integrated L2 Size (Kbytes) Package Notes SL5DR BD0 068Ah 500/100 128 BGA2 3 SL5V5 BD0 068Ah 600/100 128 BGA2 4 SL5DS BD0 068Ah 600/100 128 BGA2 3 SL582 BD0 068Ah 600/100 128 BGA2 1 SL53V BD0 068Ah 700/100 128 BGA2 2 SL53U BD0 068Ah 750/100 128 BGA2 2 SL57X BD0 068Ah 800/100 128 BGA2 2 SL57Y BD0 068Ah 850/100 128 BGA2 2 SL5LG PD0 068Ah 300/100 128 BGA2 1,6 SL544 PD0 068Ah 40
R Table 2. Identification information for Mobile Intel® Celeron® Processor (0.
R 4. 5. S. VID[4:0] = 10001; VCC_CORE = 0.95V VID[4:0] = 11000; VCC_CORE = 1.40V Supported by the Embedded Intel Architecture Division. Refer to Document # 273804-001 Table 4. Intel® Celeron® Processor (0.
R Errata M1. WBINVD May Lock Write Out Buffer Problem: The FP Data Operand Pointer is the effective address of the operand associated with the last noncontrol floating-point instruction executed by the machine.
R Case 2: In the second breakpoint reporting failure case, if a MOVSS or POPSS instruction with a data breakpoint is followed by a store to memory which: a. Crosses a 4-Kbyte page boundary, OR b. Causes the page table Access or Dirty (A/D) bits to be modified,the breakpoint information for the MOVSS or POPSS will be lost. Previous processors retain this information under these boundary conditions.
R M4. Double ECC Error on Read May Result in BINIT# Problem: For this erratum to occur, the following conditions must be met: • Machine Check Exceptions (MCEs) must be enabled. • A dataless transaction (such as a write invalidate) must be occurring simultaneously with a transaction which returns data (a normal read). • The read data must contain a double-bit uncorrectable ECC error.
R Implication: Inexact-result exceptions are commonly masked or ignored by applications, as it happens frequently, and produces a rounded result acceptable to most applications. The PE bit of the FPU status word may not always be set upon receiving an inexact-result exception. Thus, if these exceptions are unmasked, a floating-point error exception handler may not recognize that a precision exception occurred. Note that this is a “sticky” bit, i.e.
R Status: For the steppings affected see the Summary of Changes at the beginning of this section. M9. Machine Check Exception Handler May Not Always Execute Successfully Problem: An MCE may not always result in the successful execution of the MCE handler. However, asynchronous MCEs usually occur upon detection of a catastrophic system condition that would also hang the processor.
R M12. BTMs May Be Corrupted During Simultaneous L1 Cache Line Replacement Problem: When Branch Trace Messages (BTMs) are enabled and such a message is generated, the BTM may be corrupted when issued to the bus by the L1 cache if a new line of data is brought into the L1 data cache simultaneously.
R M15. FP Data Operand Pointer May Not Be Zero After Power On or Reset Problem: The FP Data Operand Pointer, as specified, should be reset to zero upon power on or Reset by the processor. Due to this erratum, the FP Data Operand Pointer may be nonzero after power on or Reset.
R In the example, EAX is forced to contain 0 by the XOR or SUB instructions. Since the four types of the MOVSX or IMUL instructions and the CBW instruction modify only bits 15:8 of EAX by sign extending the lower 8 bits of EAX, bits 31:16 of EAX should always contain 0. This implies that when MOVD copies EAX to MM0, bits 31:16 of MM0 should also be 0. Under certain scenarios, bits 31:16 of MM0 are not 0, but are replicas of bit 15 (the 16th bit) of AX.
R Workaround: Code which performs loads from memory that has side-effects can effectively workaround this behavior by using simple integer-based load instructions when accessing side-effect memory and by ensuring that all code is written such that a code segment limit violation cannot occur as a part of reading from sideeffect memory. Status: For the steppings affected see the Summary of Changes at the beginning of this section. M18.
R V86 mode before continuing. If the exception did occur in V86 mode, the exception may be directed to the general-protection exception handler. Status: For the steppings affected see the Summary of Changes at the beginning of this section. M21. Upper Four PAT Entries Not Usable With Mode B or Mode C Paging Problem: The Page Attribute Table (PAT) contains eight entries, which must all be initialized and considered when setting up memory types for the mobile processor.
R M24. SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment Selector” to SS and CS Registers Problem: According to the processor specification, attempting to load a null segment selector into the CS and SS segment registers should generate a General Protection Fault (#GP). Although loading a null segment selector to the other segment registers is allowed, the processor will generate an exception when the segment register holding a null selector is used to access memory.
R Status: For the steppings affected see the Summary of Changes at the beginning of this section. M27. Misaligned Locked Access to APIC Space Results in Hang Problem: When the processor’s APIC space is accessed with a misaligned locked access a machine check exception is expected. However, the processor’s machine check architecture is unable to handle the misaligned locked access. If this erratum occurs the processor will hang.
R erroneously causes the eviction of a line from the IFU at a time when the processor is expecting the line to still be present. If the MCE for this particular IFU event is disabled, execution will continue normally. Implication: While this erratum may occur on a system with any number of mobile processors, the probability of occurrence increases with the number of processors. If this erratum does occur, a machine check exception will result.
R M34. Cache Coherency May Be Lost If Snoop Occurs During Cache Line Invalidation Problem: There exists a two cycle window during a cache line invalidation (due to a WBINVD instruction or FLUSH# pin assertion) during which a processor performing a snoop of that line will not see the line in the cache. In addition, when this erratum occurs, the processor invalidating the line will not write back the data in that line. Implication: If this erratum occurs, cache coherency and data will be lost.
R a corresponding bus transaction, causing the processor to hang (livelock). The exact circumstances are complex, and include the relative timing of internal processor functions with the snoop request from a bus agent. Implication: This erratum may occur on a system with any number of processors. However, the probability of occurrence increases with the number of processors. If this erratum does occur, the system will hang with DBSY# asserted. At this point, the system requires a hard reset.
R M41. L2_DBUS_BUSY Performance Monitoring Counter Will Not Count Writes Problem: The L2_DBUS_BUSY (22H) performance monitoring counter is intended to count the number of cycles during which the L2 data bus is in use. For some steppings of the processor, the L2_DBUS_BUSY counter will not be incremented during write cycles and therefore will only reflect the number of L2 data bus cycles resulting from cache reads. Implication: The L2_DBUS_BUSY event counts only L2 read cycles.
R Software using unsynchronized XMC to modify the instruction byte stream of a processor may see unexpected instruction execution from the processor that is executing the modified code. Implication: In this case, the phrase "unexpected execution behavior" encompasses the generation of most of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide including a General Protection Fault (GPF).
R Status: For the steppings affected see the Summary of Changes at the beginning of this section. M47. Noise Sensitivity Issue on Processor SMI# Pin Problem: Post silicon characterization has demonstrated a greater than expected sensitivity to noise on the processor's SMI# input, which may result in spurious SMI# interrupts. Implication: BIOS/SMM code that is capable of handling spurious SMI events will report a spurious SMI#, but should not be negatively impacted by this erratum.
R 1. XOR EAX, EAX or SUB EAX, EAX 2.
R Status: For the steppings affected see he Summary of Changes at the beginning of this section. M49. FLUSH# Assertion Following STPCLK# May Prevent CPU Clocks From Stopping Problem: If FLUSH# is asserted after STPCLK# is asserted, the cache flush operation will not occur until after STPCLK# is de-asserted. Furthermore, the pending flush will prevent the processor from entering the Sleep state, since the flush operation must complete prior to the processor entering the Sleep state.
R 2. The memory accessing instruction is immediately followed by a waiting floating-point or MMX technology instruction. 3. The waiting floating-point or MMX technology instruction retires during a one-cycle window that coincides with a sequence of internal events related to instruction cache line eviction. Implication: The floating-point exception will not be signaled until the next waiting floating-point/MMX technology instruction.
R Problem: A small window of time exists in which internal timing conditions in the processor cache logic may result in the eviction of an L2 cache line marked in the invalid state. Implication: There are three possible implications of this erratum: 1. The processor may provide incorrect L2 cache line data by evicting an invalid line. 2. A BNR# (Block Next Request) stall may occur on the system bus. 3.
R M57. Intermittent Power-on Failure due to Uninitialized Processor Internal Nodes Problem: If there is no clock source supplied to the processor’s PICCLK pin, the processor may drive an incorrect address for the reset vector at power-on due to uninitialized processor internal nodes. In this scenario when ADS# is asserted, it is possible that the processor drives either the SMI or NMI vector addresses, rather than the reset vector address.
R Implication: When the OS recovers from the double fault handler, the processor will no longer be in VM86 mode. Workaround: None identified Status: For the steppings affected see the Summary of Changes at the beginning of this section. M61.
R M64. Machine Check Exception may Occur When Interleaving Code Between Different Memory Types Problem: A small window of opportunity exists where code fetches interleaved between different memory types may cause a machine check exception. A complex set of micro-architectural boundary conditions is required to expose this window. Implication: Interleaved instruction fetches between different memory types may result in a machine check exception.
R Workaround: Software should always poll the Delivery Status bit in the APIC ICR and ensure that it is '0’ (Idle) before writing a new value to the ICR. Status: For the steppings affected see the Summary of Changes at the beginning of this section. M67.
R Workaround: Do not use boundary scan when DPSLP# is asserted low. Status: For the steppings affected, see the Summary of Changes at the beginning of this section. M71. Under Some Complex Conditions, the Instructions in the Shadow of a JMP FAR may be Unintentionally Executed and Retired Problem: If all of the following events happen in sequence it is possible for the system or application to hang or to execute with incorrect data. 1.
R M73. Lock Data Access that Spans Two Pages May Cause the System to Hang Problem: An instruction with lock data access that spans across two pages may, given some rare internal conditions, hang the system. Implication: When this erratum occurs, the system may hang. Intel has not observed this erratum with any commercially available software or system. Workaround: A lockable data access should always be aligned. Status: For the steppings affected, see the Summary Tables of Changes. M74.
R Workaround: There is no workaround for single step operation in commercially available software. For debug activities on custom software, the POPF and POPFD instructions could be immediately followed by a NOP instruction to facilitate correct execution Status: For the steppings affected, see the Summary Tables of Changes M77.
R M80. Page with PAT (Page Attribute Table) Set to USWC (Uncacheable Speculative Write Combine) While Associated MTRR (Memory Type Range Register) is UC (Uncacheable) May Consolidate to UC Problem: For a page whose PAT memory type is USWC while the relevant MTRR memory type is UC, the consolidated memory type may be treated as UC (rather than WC as specified in IA-32 Intel® Architecture Software Developer's Manual)..
R Implication: When this erratum occurs, the values for FPUDataPointer in the saved floating point image or floating point environment structure may appear to be random values. Executing any non-control FP instruction with memory operand will initialize the FPUDataPointer. Intel has not observed this erratum with any commercially available software.
R M87. The Processor May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. M88.
R M90. Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid. The corresponding data if sent out as a BTM on the system bus will also be incorrect. Note: This issue would only occur when one of the 3 above mentioned debug support facilities are used.
R Status: For the steppings affected, see the Summary Tables of Changes M93. The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception Problem: DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap Flag, bit 8) of the EFLAGS Register is set, and a #DB (Debug Exception) occurs due to one of the following: • DR7 GD (General Detect, bit 13) being bit set; • INT1 instruction; • Code breakpoint the DR6 BS (Single Step, bit 14) flag may be incorrectly set.
R Specification Changes There are no specification changes.
R Specification Clarifications The Specification Clarifications listed in this section apply to: • Mobile Intel® Celeron® Processor in BGA2 and Micro-PGA2 Packages at 900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz, Low voltage 600 MHz, Low voltage 500 MHz, Low voltage 400A MHz, Ultra Low Voltage 600MHz and Ultra Low Voltage 500 MHz datasheet (Order Number 283654-003) • Mobile Intel® Celeron® Processor (0.
R 6. PDSLP is Deep Sleep power. M2. SPECIFICATION CLARIFICATION WITH RESPECT TO TIME STAMP COUNTER In the “Debugging and Performance Monitoring” section of the IA-32 Intel® Architecture Software Developers Manual Software Developer’s Manual Volume 3: System Programming Guide, the Time Stamp Counter definition has been updated to include support for the future processors.
R NOTE To determine average processor clock frequency, Intel recommends the use of Performance Monitoring logic to count processor core clocks over the period of time for which the average is required. See Section 15.10.9 and Appendix A in this manual for more information. The RDTSC instruction reads the time-stamp counter and is guaranteed to return a monotonically increasing unique value whenever executed, except for a 64-bit counter wraparound.
R • Time-stamp counter — Measures clock cycles in which the physical processor is not in deep sleep. These ticks cannot be measured on a logical-processor basis. • Time-stamp counter — Some processor models permit clock cycles to be measured when the physical processor is not in deep sleep (by using the time-stamp counter and the RDTSC instruction). Note that such sticks cannot be measured on a per-logical-processor basis. See Section 10.8 for detail on processor capabilities.
R Documentation Changes There are no Documentation Changes for this month.
