Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2 Quad Mobile Processor, Intel® Core™2 Extreme Mobile Processor, Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Intel® Celeron® Processor on 45-nm Process Specification Update November 2008 Document Number: 320121-004
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Contents Preface ...............................................................................................................................5 Identification Information ......................................................................................................7 Summary Tables of Changes ................................................................................................12 Errata .......................................................................................................
Revision History Document Number Revision Version 320121 001 1.0 Initial release 320121 002 1.0 • Updated Title • Updated Identification Information • Updated Affected Documents • Added Erratum AZ62, AZ63, AZ64,AZ65, AZ66 4 Description 320121 003 1.0 • Added Erratum AZ66-74 320121 004 1.
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata, and specification clarifications and changes. This document is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Document Title Document Number/Location Volume 3A: System Programming Guide Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume 3B: System Programming Guide 253669 IA-32 Intel® Architecture Optimization Reference Manual 248966 Intel Processor Identification and the CPUID Instruction Application Note (AP-485) 241618 Intel® 64 and IA-32 Architectures Application Note TLBs, PagingStructure Caches, and Their Invalidation 317080 NOTE: Contact your Intel representative for the
Identification Information Identification Information Component Identification via Programming Interface Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2 Quad Mobile Processor, Intel® Core™2 Extreme Mobile Processor, Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Intel® Celeron® Processor on 45nm Process stepping can be identified by the following register contents: Reserved Extended Family1 Extended Model2 Reserved Processor Type3 Family Code4 Model Number
Identification Information Component Marking Information The processor stepping can be identified by the following component markings: Figure 1.
Identification Information FSB Freq. (MHz) IDAT Freq.(GHz) L2 Cache(MB) Notes SLAQH T9500 m-FCPGA C-0 000010676h 2.6/1.2/0.8 800 2.8 35 6 2,3,4 SLAPW T9500 m-FCBGA C-0 000010676h 2.6/1.2/0.8 800 2.8 35 6 2,3,4 SLAQG T9300 m-FCPGA C-0 000010676h 2.5/1.2/0.8 800 2.7 35 6 2,3,4 SLAPV T9300 m-FCBGA C-0 000010676h 2.5/1.2/0.8 800 2.7 35 6 2,3,4 SLAPU T8300 m-FCBGA C-0 000010676h 2.4/1.2/0.8 800 2.6 35 3 2,3,4 SLAUU T8100 m-FCPGA C-0 000010676h 2.
CPUID FSB Freq. (MHz) IDAT Freq.(GHz) HFM TDP (W) L2 Cache(MB) Notes SLB4M P8400 m-FCBGA M-0 000010676h 2.26/1.6/0.8 1066 2.40 25 3 6,11,12 SLB3Q P8400 m-FCPGA M-0 000010676h 2.26/1.6/0.8 1066 2.40 25 3 26,8,9 SL3BV P8600 m-FCBGA C-0 000010676h 2.40/1.6/0.8 1066 2.53 25 3 6,11,12 SL3BU P8400 m-FCBGA C-0 000010676h 2.26/1.6/0.8 1066 2.40 25 3 6,11,12 SLB48 X9100 m-FCPGA C-0 000010676h 3.06/1.6/0.
Identification Information 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc core core core core core core core core core core core core core VID=0.90-1.25/0.850-1.100 V [HFM/LFM] VID=0.65-0.85 [C4] VID=0.90-1.30 [IDAT] VID=0.900-1.2125/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM] VID=0.900-1.275 [IDAT] VID=0.900-1.175/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM] VID=0.90-1.25 [IDAT] VID=0.775-1.100/0.80-0.975 V [HFM/LFM]; 0.750-0.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed CPU steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Note: Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates: A = Dual-Core Intel® Xeon® processor 7000 sequence C = Intel® Celeron® processor D = Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® Dual-Core processor AO = Quad-Core Intel® Xeon® processor 3200 Series AP = Dual-Core Intel® Xeon® processor 3000 Series AQ = Intel® Pentium® Dual-Core Desktop Processor E2000 Sequence AR = Intel® Celeron® processor 500 series AS = Intel® Xeon® processor 7200, 7300 series AT = Intel® Celeron® processor 200 series AU = Intel® Celeron® Dual Core processor T1400 AV = Intel® Core™2 Extreme processor QX9000 sequence and In
Summary Tables of Changes Errata Number Steppings Status ERRATA C-0 M-0 E-0 AZ1 X X X No Fix EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB Shootdown AZ2 X X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions AZ3 X X X No Fix Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads AZ4 X X X No Fix Non-Temporal Data Store May be Observed in Wrong Program Order AZ5 X X X No Fix Page Access Bit May
Summary Tables of Changes Number Steppings Status ERRATA X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation X X No Fix Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate X X X No Fix Returning to Real Mode from SMM with EFLAGS.
Summary Tables of Changes Number Steppings Status ERRATA X No Fix Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violations X X No Fix VM Exit Caused by a SIPI Results in Zero Being Saved to the Guest RIP Field in the VMCS X X X No Fix NMIs May Not Be Blocked by a VM-Entry Failure AZ45 X X X Plan Fix Partial Streaming Load Instruction Sequence May Cause the Processor to Hang AZ46 X X X Plan Fix Self/Cross Modifying Code May Not be Detect
Summary Tables of Changes Number Steppings C-0 M-0 E-0 Status ERRATA AZ63 X No Fix INIT Incorrectly Resets IA32_LSTAR MSR AZ64 X No Fix When a CPUID instruction is executed, the returned EAX, EBX, ECX, and/or EDX may be incorrect.
Errata Errata AZ1. EFLAGS Discrepancy on a Page Fault after a Multiprocessor TLB Shootdown Problem: This erratum may occur when the processor executes one of the following read-modifywrite arithmetic instructions and a page fault occurs during the store of the memory operand: ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, ROL/ROR, SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, and XADD.
Errata AZ2.
Errata AZ5. Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault Problem: If code segment limit is set close to the end of a code page, then due to this erratum the memory page Access bit (A bit) may be set for the subsequent page prior to general protection fault on code segment limit. Implication: When this erratum occurs, a non-accessed page which is present in memory and follows a page that contains the code segment limit may be tagged as accessed.
Errata AZ7. Storage of PEBS Record Delayed Following Execution of MOV SS or STI Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based Sampling), overflow of the counter results in storage of a PEBS record in the PEBS buffer. The information in the PEBS record represents the state of the next instruction to be executed following the counter overflow.
Errata AZ10. Performance Monitoring Event MISALIGN_MEM_REF May Over Count Problem: Performance monitoring event MISALIGN_MEM_REF (05H) is used to count the number of memory accesses that cross an 8-byte boundary and are blocked until retirement. Due to this erratum, the performance monitoring event MISALIGN_MEM_REF also counts other memory accesses. Implication: The performance monitoring event MISALIGN_MEM_REF may over count.
Errata AZ13. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memory-based APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g.
Errata AZ15. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations Problem: Under certain conditions as described in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A section “Out-of-Order Stores for String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings.
Errata AZ17. Address Reported by Machine-Check Architecture (MCA) on Single-bit L2 ECC Errors May Be Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is logged in the MCA address register (MCi_ADDR). Under some scenarios, the address reported may be incorrect. Implication: Software should not rely on the value reported in MCi_ADDR, for Single-bit L2 ECC errors. Workaround: None identified.
Errata AZ20. EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after Shutdown Problem: When the processor is going into shutdown due to an RSM inconsistency failure, EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be asserted. This may be observed if the processor is taken out of shutdown by NMI#. Implication: A processor that has been taken out of shutdown may have an incorrect EFLAGS, CR0 and CR4. In addition the EXF4 signal may still be asserted.
Errata AZ22. Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate Problem: The INST_RETIRED performance monitor may miscount retired instructions as follows: • Repeat string and repeat I/O operations are not counted when a hardware interrupt is received during or after the last iteration of the repeat flow. • VMLAUNCH and VMRESUME instructions are not counted. • HLT and MWAIT instructions are not counted.
Errata AZ24. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early Problem: In 64-bit Mode CMPSB, LODSB, or SCASB executed with a repeat prefix and count greater than or equal to 248 may terminate early. Early termination may result in one of the following.
Errata AZ26. Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced before Higher Priority Interrupts Problem: Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag) instruction are serviced immediately after the STI instruction is executed.
Errata AZ29. Split Locked Stores May Not Trigger the Monitoring Hardware Problem: Logical processors normally resume program execution following the MWAIT, when another logical processor performs a write access to a WB cacheable address within the address range used to perform the MONITOR operation.
Errata AZ32. General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit Problem: In 32-bit mode, memory accesses to flat data segments (base = 00000000h) that occur above the 4G limit (0ffffffffh) may not signal a #GP fault. Implication: When such memory accesses occur in 32-bit mode, the system may not issue a #GP fault. Workaround: Software should ensure that memory accesses in 32-bit mode do not occur above the 4G limit (0ffffffffh).
Errata AZ35. B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint Problem: B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly cleared when the following sequence happens: 1. POP instruction to SS (Stack Segment) selector; 2. Next instruction is FP (Floating Point) that gets FP assist followed by code breakpoint. Implication: B0-B3 bits in DR6 may not be properly cleared. Workaround: None identified.
Errata AZ38. Instruction Fetch May Cause a Livelock during Snoops of the L1 Data Cache Problem: A livelock may be observed in rare conditions when instruction fetch causes multiple level one data cache snoops. Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AZ39.
Errata AZ40. A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations Problem: Under certain conditions, as described in the Software Developers Manual section “Outof-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors”, the processor may perform REP MOVS or REP STOS as write combining stores (referred to as “fast strings”) for optimal performance. FXSAVE may also be internally implemented using write combining stores.
Errata AZ42. Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violations Problem: Memory type aliasing occurs when a single physical page is mapped to two or more different linear addresses, each with different memory types. Memory type aliasing with a cacheable memory type and WC (write combining) may cause the processor to perform incorrect operations leading to memory ordering violations for WC operations.
Errata AZ44. NMIs May Not Be Blocked by a VM-Entry Failure Problem: The Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B: System Programming Guide, Part 2 specifies that, following a VM-entry failure during or after loading guest state, “the state of blocking by NMI is what it was before VM entry.
Errata AZ46. Self/Cross Modifying Code May Not be Detected or May Cause a Machine Check Exception Problem: If instructions from at least three different ways in the same instruction cache set exist in the pipeline combined with some rare internal state, self-modifying code (SMC) or crossmodifying code may not be detected and/or handled.
Errata AZ49. RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Problem: Problem: RSM instruction execution, under certain conditions triggered by a complex sequence of internal processor micro-architectural events, may lead to processor hang, or unexpected instruction execution results.
Errata AZ51.
Errata AZ53. Short Nested Loops That Span Multiple 16-Byte Boundaries May Cause a Machine Check Exception or a System Hang Problem: Under a rare set of timing conditions and address alignment of instructions in a short nested loop sequence, software that contains multiple conditional jump instructions and spans multiple 16-byte boundaries, may cause a machine check exception or a system hang. Implication: Due to this erratum, a machine check exception or a system hang may occur.
Errata AZ55. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints until after execution of the following instruction. This is intended to allow the sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an invalid stack during interrupt handling.
Errata AZ57. A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS Problem: If a fault occurs during delivery of a software interrupt (INTn) in virtual-8086 mode when virtual mode extensions are in effect and that fault causes a VM exit, incorrect data may be saved into the VMCS. Specifically, information about the software interrupt may not be reported in the IDT-vectoring information field.
Errata AZ59. IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected.
Errata AZ61. Entry May Fail When Attempting to Set IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN Problem: If bit 14 (FREEZE_WHILE_SMM_EN) is set in the IA32_DEBUGCTL field in the guest-state area of the VMCS, VM entry may fail as described in Section “VM-Entry Failures During or After Loading Guest State” of Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide, Part 2. (The exit reason will be 80000021H and the exit qualification will be zero.
Errata AZ63. INIT Incorrectly Resets IA32_LSTAR MSR Problem: In response to an INIT reset initiated either via the INIT# pin or an IPI (Inter Processor Interrupt), the processor should leave MSR values unchanged. Due to this erratum IA32_LSTAR MSR (C0000082H), which is used by the iA32e SYSCALL instruction, is being cleared by an INIT reset.
Errata AZ66. XRSTOR Instruction May Cause Extra Memory Reads Problem: An XRSTOR instruction will cause non-speculative accesses to XSAVE memory area locations containing the FCW/FSW and FOP/FTW Floating Point registers even though the 64-bit restore mask specified in the EDX:EAX register pair does not indicate to restore the x87 FPU state. Implication: Page faults, data breakpoint triggers, etc. may occur due to the unexpected nonspeculative accesses to these memory locations.
Errata AZ69. Enabling PECI via the PECI_CTL MSR Incorrectly Writes CPUID_FEATURE_MASK1 MSR Problem: Writing PECI_CTL MSR (Platform Environment Control Interface Control Register) will not update the PECI_CTL MSR (5A0H), instead it will write to the VMM Feature Flag Mask MSR (CPUID_FEATURE_MASK1, 478H). Implication: Due to this erratum, PECI (Platform Environment Control Interface) will not be enabled as expected by the software.
Errata AZ72. Store Ordering Violation When Using XSAVE Problem: The store operations done as part of the XSAVE instruction may cause a store ordering violation with older store operations. The store operations done to save the processor context in the XSAVE instruction flow, when XSAVE is used to store only the SSE context, may appear to execute before the completion of older store operations.
Errata AZ75. B0-B3 Bits in DR6 for Non-Enabled Breakpoints May be Incorrectly Set Problem: Some of the B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may be incorrectly set for non-enabled breakpoints when the following sequence happens: 1. MOV or POP instruction to SS (Stack Segment) selector; 2. Next instruction is FP (Floating Point) that gets FP assist 3. Another instruction after the FP instruction completes successfully 4.
Specification Changes Specification Changes There are no specification changes for this specification update revision.
Specification Clarifications Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: • AZ1. Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System Programming Guide Clarification of Translation Lookaside Buffers (TLBS) Invalidation Section 10.
Specification Clarifications Intel collateral will continue to show the correct and full processor number (with the first letter ‘S’ or letter ‘X’). Table 1.
Documentation Changes Documentation Changes There are no documentation changes for this specification update revision.
