Intel® CoreTM i7-660UE, i7-620LE/ UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Datasheet Addendum August 2010 Document Number: 323178-003
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Contents 1 Introduction and Features Summary ......................................................................... 8 1.1 Introduction ....................................................................................................... 8 1.2 Interfaces ........................................................................................................ 10 1.2.1 System Memory Support ......................................................................... 10 1.2.2 PCI Express* ....................
6.3 6.2.10 SBUSN6 - Secondary Bus Number.............................................................92 6.2.11 SUBUSN6 - Subordinate Bus Number ........................................................93 6.2.12 IOBASE6 - I/O Base Address ....................................................................93 6.2.13 IOLIMIT6 - I/O Limit Address ...................................................................94 6.2.14 SSTS6 - Secondary Status .................................................................
Figures 1 2 3 4 5 6 7 8 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series on the Intel® CoreTM i7 processor based low-power platform .................................................................................................... 9 Intel® Flex Memory Technology Operation................................................................... 17 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes ..................
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 IOLIMIT6 - I/O Limit Address Register .........................................................................94 SSTS6 - Secondary Status Register.............................................................................95 MBASE6 - Memory Base Address Register ....................................................................96 MLIMIT6 - Memory Limit Address Register ...
Revision History Date Revision January 2010 001 • Initial release of this document. April 2010 002 • • Added information for the Intel® Celeron® Processor P4500 and P4505 Series. Corrected first bullet in Section 2.1.1 to “No support for mixed ECC and non-ECC DIMM configurations.
Introduction and Features Summary 1 Introduction and Features Summary 1.1 Introduction This Datasheet Addendum is a supplement to the Intel® CoreTM i7-600, i5-500 and i3300 Mobile Processor Series Datasheet.
Introduction and Features Summary Figure 1.
Introduction and Features Summary 1.2 Interfaces 1.2.1 System Memory Support • One or two channels of DDR3 memory with a maximum of one DIMM per channel • Single- and dual-channel memory organization modes • Data burst length of eight for all memory organization modes • Memory DDR3 data transfer rates of 800 and 1066 MT/s • 64-bit wide channels (72-bit wide including ECC) • DDR3 I/O Voltage of 1.
Introduction and Features Summary 1.3 Package The Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel Celeron Processor P4505, U3405 Series are available on a 34 x 28 mm BGA package (BGA1288). Note: Although the BGA1288 package is shared with Intel® CoreTM i7-640UM/LM, i7-620M/ UM/LM, i5-540M, i5-520M/UM and i5-430M Processor Series they are not ball-out compatible.
Introduction and Features Summary 1.4 Terminology Term Description BLT Block Level Transfer CRT Cathode Ray Tube DDR3 Third generation Double Data Rate SDRAM memory technology DP DisplayPort* DMA Direct Memory Access DMI Direct Media Interface DTS Digital Thermal Sensor ECC Error Correction Code eDP* Intel Embedded DisplayPort* ® DPST Intel® Display Power Saving Technology Enhanced Intel SpeedStep® Technology Technology that provides power management capabilities to laptops.
Introduction and Features Summary Term 1.5 Description PEG PCI Express* Graphics. External Graphics using PCI Express Architecture. A high-speed serial interface whose configuration is software compatible with the existing PCI specifications. Processor The 64-bit, single-core or multi-core component (package) Processor Core The term “processor core” refers to Si die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache.
Introduction and Features Summary Table 2. PCH Documents Document Number/ Location Document Intel® 5 Series Chipset and Intel® 3400 Series Chipset Datasheet Table 3. http://www.intel.com Public Specifications Document Number/ Location Document Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/ PCI Local Bus Specification 3.0 http://www.pcisig.com/ specifications PCI Express Base Specification 2.0 http://www.pcisig.com DDR3 SDRAM Specification http://www.jedec.
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. 2.1 System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two, independent, 64-bit wide channels each accessing one DIMM. It supports: — ECC and non-ECC un-buffered DIMMs. No support for mixed ECC and non-ECC DIMM configurations.
Interfaces Table 4. Raw Card Version D E F 2.1.
Interfaces 2.1.3.2 Dual-Channel Mode - Intel® Flex Memory Technology Mode The IMC supports Intel® Flex Memory Technology Mode. This mode combines the advantages of the Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes. Memory is divided into a symmetric and a asymmetric zone. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached.
Interfaces This mode is used when Intel® Flex Memory Technology is disabled and both Channel A and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being different. Figure 3. Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes Dual Channel Interleaved (memory sizes must match) Dual Channel Asymmetric (memory sizes can differ) CL CL CH. B Top of Memory CH. A Top of Memory CH. B CH.B-top DRB CH. A CH. B CH. A CH. B CH. A 2.1.
Interfaces interfering with the current request allowing for concurrent issuing of requests. This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol. 2.1.5.2 Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate, Precharge, and Read/Write commands normally used, as long as the inserted commands do not affect the currently executing command.
Interfaces Figure 4. PCI Express* Related Register Structures in the Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series PCI Express Device Port 0 PCI Express Device Port 1 PCI-PCI Bridge representing root PCI Express port (Device 1) PCI Compatible Host Bridge Device (Device 0) PCI-PCI Bridge representing root PCI Express port (Device 6) DMI 2.2.
Signal Description 3 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type: Notations Signal Type I Input Pin O Output Pin I/O Bi-directional Input/Output Pin The signal description also includes the type of buffer used for the particular signal: Table 6.
Signal Description Table 7. Memory Channel A (Sheet 2 of 2) Signal Name Description Direction/Buffer Type SA_RAS# RAS Control Signal: Used with SA_CAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands. O DDR3 SA_CAS# CAS Control Signal: Used with SA_RAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands. O DDR3 SA_DM[7:0] Data Mask: These signals are used to mask individual bytes of data in the case of a partial write and to interrupt burst writes.
Signal Description Table 8. Memory Channel B (Sheet 1 of 2) Signal Name Description Direction/Buffer Type Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SB_WE# Write Enable Control Signal: Used with SB_RAS# and SB_CAS# (along with SB_CS#) to define the SDRAM Commands. O DDR3 SB_RAS# RAS Control Signal: Used with SB_CAS# and SB_WE# (along with SB_CS#) to define the SRAM Commands.
Signal Description Table 8. Memory Channel B (Sheet 2 of 2) Signal Name Description Direction/Buffer Type SB_ODT[1:0] On Die Termination: Active Termination Control. O DDR3 3.2 Reset and Miscellaneous Signals Table 9. Reset and Miscellaneous Signals Signal Name SM_DRAMRST# Description DDR3 DRAM Reset: Reset signal from processor to DRAM devices. One for all channels of DIMMs.
Electrical Specifications 4 Electrical Specifications 4.1 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 10. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have OnDie Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board. Table 10.
Electrical Specifications Table 11. Symbol DDR3 Signal Group DC Specifications (Sheet 2 of 2) Parameter Input High Voltage VIH Alpha Group Min (e,f) 0.57*VDDQ Typ VOL Output Low Voltage (c,d,e,f) (VDDQ / 2)* (RON / (RON+RVTT_TERM)) VOH Output High Voltage (c,d,e,f) VDDQ - ((VDDQ / 2)* (RON/ (RON+RVTT_TERM)) Max Units Notes1,9 V 3 5 V 4,5 NOTES: 1. 2. 3. 4. 5. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Processor Ball and Signal Information 5 Processor Ball and Signal Information 5.1 Processor Ball Assignments • Table 12 provides a listing of all processor pins ordered alphabetically by ball name for the Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series package respectively.
Processor Ball and Signal Information Figure 5.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ballmap (Top View, Upper-Right Quadrant) Figure 6.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ballmap (Top View, Lower-Left Quadrant) Figure 7.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ballmap (Top View, Lower-Right Quadrant) Figure 8.
Processor Ball and Signal Information Table 12. Pin Name 323178-003 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Table 12.
Processor Ball and Signal Information Table 12.
Processor Ball and Signal Information Table 12. Pin Name Pin # Buffer Type Dir PEG_TX[0] L40 PCIe O PEG_TX[1] N38 PCIe O PEG_TX[2] N32 PCIe PEG_TX[3] B39 PCIe Table 12.
Processor Ball and Signal Information Table 12. Pin Name 35 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 323178-003 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 37 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 323178-003 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 39 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 323178-003 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 41 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 323178-003 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 43 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 323178-003 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 45 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 323178-003 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 47 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12. Pin Name 323178-003 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Name Pin # Buffer Type Dir Table 12.
Processor Ball and Signal Information Table 12.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13. Pin # 323178-003 Pin Name Buffer Type Dir GND Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13. Pin # 51 Pin Name Buffer Type Dir Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13. Pin # 323178-003 Pin Name Buffer Type Dir Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13. Pin # 53 Pin Name Buffer Type Dir Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13. Pin # 323178-003 Pin Name Buffer Type Dir Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13. Pin # 55 Pin Name Buffer Type Dir Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13. Pin # 323178-003 Pin Name Buffer Type Dir Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13. Pin # 57 Pin Name Buffer Type Dir Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13. Pin # 323178-003 Pin Name Buffer Type Dir Table 13.
Processor Ball and Signal Information Table 13. Pin # 59 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Pin Name Buffer Type Dir Table 13.
Processor Ball and Signal Information Table 13. Pin # 323178-003 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Pin Name Buffer Type BN1 VSS GND BN4 SB_DQS#[1] DDR3 Dir I/O Table 13.
Processor Ball and Signal Information Table 13. Pin # 61 Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Pin Name Buffer Type Dir Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13. Pin # 323178-003 Pin Name Buffer Type Dir Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13. Pin # 63 Pin Name Buffer Type Dir Table 13.
Processor Ball and Signal Information Table 13. Pin # Pin Name Buffer Type Dir Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Ball and Signal Information Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Ball List by Ball Number Table 13.
Processor Configuration Registers 6 Processor Configuration Registers This chapter is an Addendum to the Intel® CoreTM i7-600, i5-500 and i3-300 Mobile Processor Series Datasheet. Contained in this chapter is any register information that is specific to the Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series.
Processor Configuration Registers Table 14. Register Terminology (Sheet 2 of 2) Item Description RW1C-S Read/Write 1 to Clear/Sticky bit(s). These bits can be read. Internal events may set this bit. A software write of 1 clears (sets to 0) the corresponding bit(s) and a write of 0 has no effect. Bits are not cleared by "warm" reset, but is reset with a cold/complete reset (for PCI Express related bits a cold reset is “Power Good Reset” as defined in the PCI Express Base spec).
Processor Configuration Registers 6.1.1 DEVEN - Device Enable B/D/F/Type: 0/0/0/PCI Address Offset: 54-57h Default Value: 0000010Bh Access: RW-L; RO; RW Size: 32 bits BIOS Optimal Default 000000h Allows for enabling/disabling of PCI devices and functions that are within the processor. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register. All the bits in this register are Intel TXT Lockable. Table 15.
Processor Configuration Registers 6.1.2 ERRSTS - Error Status B/D/F/Type: 0/0/0/PCI Address Offset: C8-C9h Default Value: 0000h Access: RO; RW1C-S; Size: 16 bits This register is used to report various error conditions via the SERR DMI messaging mechanism. An SERR DMI message is generated on a zero to one transition of any of these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is enabled and generated.
Processor Configuration Registers Table 16. Error Status Register (Sheet 2 of 2) Bit Access Default Value RST/ PWR Description 1 RW1C-S 0b Core Multiple-bit DRAM ECC Error Flag (DMERR): If this bit is set to 1, a memory read data transfer had an uncorrectable multiple-bit error. When this bit is set, the column, row, bank, and rank that caused the error, and the error syndrome, are logged in the ECC Error Log register in the channel where the error occurred.
Processor Configuration Registers Table 17. Error Command Registers Bit Access Default Value RST/ PWR Description 15:12 RO 000b Core Reserved 11 RW 0b Core SERR on Processor Thermal Sensor Event (TSESERR): 1: The Processor generates a DMI SERR special cycle when bit 11 of the ERRSTS is set. The SERR must not be enabled at the same time as the SMI for the same thermal sensor event. 0: Reporting of this condition via SERR messaging is disabled.
Processor Configuration Registers 6.1.4 SMICMD - SMI Command B/D/F/Type: 0/0/0/PCI Address Offset: CC-CDh Default Value: 0000h Access: RO, RW; Size: 16 bits This register enables various errors to generate an SMI DMI special cycle. When an error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively. Note that one and only one message type can be enabled. Table 18.
Processor Configuration Registers 6.1.5 Table 19. C0WRDATACTRL - Channel 0 Write Data Control B/D/F/Type: 0/0/0/MCHBAR Address Offset: 24D-24Fh Default Value: 004111h Access: RW Size: 24 bits BIOS Optimal Default 00h Channel 0 Write Data Control Registers Bit Access Default Value RST/ PWR Description 23:16 RW 00h Core ECC bit invert vector (C0sd_cr_eccbitinv): This vector operates individually for every ECC bit in the selected 64b ECC block, during write to DRAM.
Processor Configuration Registers 6.1.6 COECCERRLOG - Channel 0 ECC Error Log B/D/F/Type: 0/0/0/MCHBAR Address Offset: 280-287h Default Value: 0000000000000000h Access: RO-P; RO Size: 64 bits This register is used to store the error status information in ECC enabled configurations, along with the error syndrome and the rank/bank/row/column address information of the address block of main memory of which an error (single bit or multibit error) has occurred.
Processor Configuration Registers Table 20. Channel 0 ECC Error Registers (Sheet 2 of 2) Bit Access Default Value RST/ PWR 0 RO-P 0b Core Description Correctable Error Status (CERRSTS): This bit is set when a correctable single-bit error occurs on a memory read data transfer. When this bit is set, the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors, until this bit is cleared.
Processor Configuration Registers 6.1.7 Table 21. C1WRDATACTRL - Channel 1 Write Data Control B/D/F/Type: 0/0/0/MCHBAR Address Offset: 64D-64Fh Default Value: 004111h Access: RW Size: 24 bits BIOS Optimal Default 00h Channel 1 Write Data Control Registers Bit Access Default Value RST/ PWR Description 23:16 RW 00h Core ECC bit invert vector (C1sd_cr_eccbitinv): This vector operates individually for every ECC bit in the selected 64b ECC block, during write to DRAM.
Processor Configuration Registers Table 22. 6.2 Channel 1 ECC Error Registers Bit Access Default Value RST/ PWR 63:48 RO-V-S 0000h Core Error Column Address (ERRCOL): Row address of the address block of main memory of which an error (single bit or multibit error) has occurred.
Processor Configuration Registers Reserved and Preserved: 1. Reserved for future RW implementations; software must preserve value read for writes to bits. 2. Reserved and Zero: Reserved for future R/WC/S implementations; software must use 0 for writes to bits. Unless explicitly documented as Reserved and Zero, all bits marked as reserved are part of the Reserved and Preserved type, which have historically been the typical definition for Reserved.
Processor Configuration Registers Table 23.
Processor Configuration Registers Table 23.
Processor Configuration Registers 6.2.1 VID6 - Vendor Identification B/D/F/Type: 0/6/0/PCI Address Offset: 0-1h Default Value: 8086h Access: RO Size: 16 bits This register combined with the Device Identification register uniquely identify any PCI device. Table 24. VID6 - Vendor Identification Register Bit Access Default Value RST/ PWR 15:0 RO 8086h Core Description Vendor Identification (VID6) PCI standard identification for Intel. 6.2.
Processor Configuration Registers 6.2.3 PCICMD6 - PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: Table 26. Bit 0/6/0/PCI 4-5h 0000h RO; RW 16 bits PCICMD6 - PCI Command Register (Sheet 1 of 2) Access Default Value RST/ PWR Description 15:11 RO 00h Core Reserved 10 RW 0b Core INTA Assertion Disable (INTAAD) 0 = This device is permitted to generate INTA interrupt messages. 1 = This device is prevented from generating interrupt messages.
Processor Configuration Registers Table 26. PCICMD6 - PCI Command Register (Sheet 2 of 2) Bit Access Default Value RST/ PWR 6 RW 0b Core Description Parity Error Response Enable (PERRE) Controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set. 0 = Master Data Parity Error bit in PCI Status register CANNOT be set. 1 = Master Data Parity Error bit in PCI Status register CAN be set. 5 RO 0b Core VGA Palette Snoop (VGAPS) Not Applicable or Implemented.
Processor Configuration Registers 6.2.4 PCISTS6 - PCI Status B/D/F/Type: 0/6/0/PCI Address Offset: 6-7h Default Value: 0010h Access: RO; RWC Size: 16 bits This register reports the occurrence of error conditions associated with primary side of the “virtual” Host-PCI Express bridge embedded within the processor. Table 27. PCISTS6 - PCI Status Register (Sheet 1 of 2) Bit Access Default Value RST/ PWR 15 RO 0b Core Description Detected Parity Error (DPE) Not Applicable or Implemented.
Processor Configuration Registers Table 27. PCISTS6 - PCI Status Register (Sheet 2 of 2) Bit Access Default Value RST/ PWR 5 RO 0b Core 4 RO 1b Core Description 66-/60-MHz Capability (CAP66) Not Applicable or Implemented. Hard wired to 0. Capabilities List (CAPL) Indicates that a capabilities list is present. Hard wired to 1. 3 RO 0b Core INTA Status (INTAS) Indicates that an interrupt message is pending internally to the device.
Processor Configuration Registers 6.2.5 RID6 - Revision Identification B/D/F/Type: 0/6/0/PCI Address Offset: 8h Default Value: 10h Access: RO Size: 8 bits This register contains the revision number of the processor Device 6. These bits are read only and writes to this register have no effect. Table 28.
Processor Configuration Registers 6.2.7 CL6 - Cache Line Size B/D/F/Type: Address Offset: Default Value: Access: Size: Table 30. 0/6/0/PCI Ch 00h RW 8 bits CL6 - Cache Line Size Register Bit Access Default Value RST/ PWR 7:0 RW 00h Core Description Cache Line Size (Scratch pad) Implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no impact on any PCI Express device functionality. 6.2.
Processor Configuration Registers 6.2.9 PBUSN6 - Primary Bus Number B/D/F/Type: 0/6/0/PCI Address Offset: 18h Default Value: 00h Access: RO Size: 8 bits This register identifies that this “virtual” Host-PCI Express bridge is connected to PCI Bus 0. Table 32. PBUSN6 - Primary Bus Number Register Bit Access Default Value RST/ PWR 7:0 RO 00h Core Description Primary Bus Number (BUSN) Configuration software typically programs this field with the number of the bus on the primary side of the bridge.
Processor Configuration Registers 6.2.11 SUBUSN6 - Subordinate Bus Number B/D/F/Type: 0/6/0/PCI Address Offset: 1Ah Default Value: 00h Access: RW Size: 8 bits This register identifies the subordinate bus (if any) that resides at the level below PCI Express-G. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express-G. Table 34.
Processor Configuration Registers Table 35. IOBASE6 - I/O Base Address Register Bit Access Default Value RST/ PWR 7:4 RW Fh Core Description I/O Address Base (IOBASE) Corresponds to A[15:12] of the I/O addresses passed by bridge 1 to PCI Express-G. BIOS must not set this register to 00h otherwise 0CF8h/0CFCh accesses is forwarded to the PCI Express hierarchy associated with this device. 3:0 RO 6.2.
Processor Configuration Registers 6.2.14 SSTS6 - Secondary Status B/D/F/Type: 0/6/0/PCI Address Offset: 1E-1Fh Default Value: 0000h Access: RWC; RO Size: 16 bits SSTS6 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., PCI Express-G side) of the “virtual” PCI-to-PCI bridge embedded within processor. Table 37.
Processor Configuration Registers 6.2.15 MBASE6 - Memory Base Address B/D/F/Type: 0/6/0/PCI Address Offset: 20-21h Default Value: FFF0h Access: RO; RW Size: 16 bits This register controls the CPU to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =
Processor Configuration Registers 6.2.16 MLIMIT6 - Memory Limit Address B/D/F/Type: 0/6/0/PCI Address Offset: 22-23h Default Value: 0000h Access: RO; RW Size: 16 bits This register controls the CPU to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =
Processor Configuration Registers 6.2.
Processor Configuration Registers 6.2.
Processor Configuration Registers 6.2.19 PMBASEU6 - Prefetchable Memory Base Address Upper B/D/F/Type: 0/6/0/PCI Address Offset: 28-2Bh Default Value: 00000000h Access: RW Size: 32 bits The functionality associated with this register is present in the PEG design implementation.
Processor Configuration Registers 6.2.20 PMLIMITU6 - Prefetchable Memory Limit Address Upper B/D/F/Type: 0/6/0/PCI Address Offset: 2C-2Fh Default Value: 00000000h Access: RW Size: 32 bits The functionality associated with this register is present in the PEG design implementation.
Processor Configuration Registers 6.2.21 CAPPTR6 - Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: 0/6/0/PCI 34h 88h RO 8 bits The capabilities pointer provides the address offset to the location of the first entry in this device's linked list of capabilities. Table 44.
Processor Configuration Registers 6.2.23 INTRPIN6 - Interrupt Pin B/D/F/Type: 0/6/0/PCI Address Offset: 3Dh Default Value: 01h Access: RO Size: 8 bits This register specifies which interrupt pin this device uses. Table 46. INTRPIN6 - Interrupt Pin Register Bit Access Default Value RST/ PWR 7:0 RO 01h Core Description Interrupt Pin (INTPIN) As a single function device, the PCI Express device specifies INTA as its interrupt pin. 01h=INTA. 6.2.
Processor Configuration Registers Table 47. BCTRL6 - Bridge Control Register (Sheet 2 of 2) Bit Access Default Value RST/ PWR 5 RO 0b Core Description Master Abort Mode (MAMODE) Does not apply to PCI Express. Hard wired to 0. 4 RW 0b Core VGA 16-bit Decode (VGA16D) Enables the PCI-to-PCI bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of alias addresses every 1 KB.
Processor Configuration Registers 6.2.25 PM_CAPID6 - Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: Table 48. 0/6/0/PCI 80-83h C8039001h RO 32 bits PM_CAPID6 - Power Management Capabilities Register Bit Access Default Value RST/ PWR 31:27 RO 19h Core Description PME Support (PMES) This field indicates the power states in which this device may indicate PME wake via PCI Express messaging. D0, D3hot & D3cold.
Processor Configuration Registers 6.2.26 PM_CS6 - Power Management Control/Status B/D/F/Type: Address Offset: Default Value: Access: Size: Table 49. 0/6/0/PCI 84-87h 00000008h RO; RW-S; RW 32 bits PM_CS6 - Power Management Control/Status Register Bit Access Default Value RST/ PWR Description 31:16 RO 0000h Core Reserved 15 RO 0b Core PME Status (PMESTS) Not Applicable or Implemented. Hard wired to 0. Indicates that this device does not support PMEB generation from D3cold.
Processor Configuration Registers Table 49. PM_CS6 - Power Management Control/Status Register Bit Access Default Value RST/ PWR 1:0 RW 00b Core Description Power State (PS) Indicates the current power state of this device and can be used to set the device into a new power state. If software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. 00: D0 01: D1 (Not supported in this device.
Processor Configuration Registers 6.2.27 SS_CAPID - Subsystem ID and Vendor ID Capabilities B/D/F/Type: 0/6/0/PCI Address Offset: 88-8Bh Default Value: 0000800Dh Access: RO Size: 32 bits This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. However, it is necessary because Microsoft will test for its presence. Table 50.
Processor Configuration Registers 6.2.29 MSI_CAPID - Message Signaled Interrupts Capability ID B/D/F/Type: 0/6/0/PCI Address Offset: 90-91h Default Value: A005h Access: RO Size: 16 bits When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0] @ 7Fh).
Processor Configuration Registers Table 53. MC - Message Control Register (Sheet 2 of 2) Bit Access Default Value RST/ PWR 6:4 RW 000b Core Description Multiple Message Enable (MME) System software programs this field to indicate the actual number of messages allocated to this device. This number is equal to or less than the number actually requested. The encoding is the same as for the MMC field below.
Processor Configuration Registers 6.2.31 MA - Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: Table 54. 0/6/0/PCI 94-97h 00000000h RO; RW 32 bits MA - Message Address Register Bit Access Default Value RST/ PWR 31:2 RW 00000000h Core Description Message Address (MA) Used by system software to assign an MSI address to the device. The device handles an MSI by writing the padded contents of the MD register to this address.
Processor Configuration Registers 6.2.33 PEG_CAPL - PCI Express-G Capability List B/D/F/Type: 0/6/0/PCI Address Offset: A0-A1h Default Value: 0010h Access: RO Size: 16 bits Enumerates the PCI Express capability structure. Table 56. PEG_CAPL - PCI Express-G Capability List Register Bit Access Default Value RST/ PWR 15:8 RO 00h Core Description Pointer to Next Capability (PNC) This value terminates the capabilities list.
Processor Configuration Registers Table 57. PEG_CAP - PCI Express-G Capabilities Register Bit Access Default Value RST/ PWR 3:0 RO 2h Core Description PCI Express Capability Version (PCIECV) hard wired to 2h to indicate compliance to the PCI Express Capabilities Register Expansion ECN. 6.2.35 DCAP - Device Capabilities B/D/F/Type: 0/6/0/PCI Address Offset: A4-A7h Default Value: 00008000h Access: RO Size: 32 bits Indicates PCI Express device capabilities. Table 58.
Processor Configuration Registers 6.2.36 DCTL - Device Control B/D/F/Type: 0/6/0/PCI Address Offset: A8-A9h Default Value: 0000h Access: RO; RW Size: 16 bits Provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register. Table 59.
Processor Configuration Registers Table 59. DCTL - Device Control Register (Sheet 2 of 2) Bit Access Default Value RST/ PWR 1 RW 0b Core Description Non-Fatal Error Reporting Enable (NERE) When set, enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting.
Processor Configuration Registers Table 60. DSTS - Device Status Register Bit Access Default Value RST/ PWR 2 RWC 0b Core Description Fatal Error Detected (FED) When set this bit indicates that fatal error(s) were detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. When Advanced Error Handling is enabled, errors are logged in this register regardless of the settings of the uncorrectable error mask register.
Processor Configuration Registers Table 61. LCAP - Link Capabilities Register (Sheet 2 of 3) Bit Access Default Value RST/ PWR 21 RO 1b Core Description Link Bandwidth Notification Capability (LBNC) A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch downstream ports supporting Links wider than x1 and/or multiple Link speeds.
Processor Configuration Registers Table 61. LCAP - Link Capabilities Register (Sheet 3 of 3) Bit Access Default Value RST/ PWR 17:15 RW-O 010b Core Description L1 Exit Latency (L1ELAT) Indicates the length of time this Port requires to complete the transition from L1 to L0.
Processor Configuration Registers 6.2.39 LCTL - Link Control B/D/F/Type: 0/6/0/PCI Address Offset: B0-B1h Default Value: 0000h Access: RO; RW; RW-SC Size: 16 bits Allows control of PCI Express link. Table 62.
Processor Configuration Registers Table 62. LCTL - Link Control Register (Sheet 2 of 3) Bit Access Default Value RST/ PWR 7 RW 0b Core Description Extended Synch (ES) 0 = Standard Fast Training Sequence (FTS). 1 = Forces the transmission of additional ordered sets when exiting the L0s state and when in the Recovery state. This mode provides external devices (e.g., logic analyzers) monitoring the Link time to achieve bit and symbol lock before the link enters L0 and resumes communication.
Processor Configuration Registers Table 62. LCTL - Link Control Register (Sheet 3 of 3) Bit Access Default Value RST/ PWR 1:0 RW 00b Core Description Active State PM (ASPM) Controls the level of active state power management supported on the given link. 00: Disabled 01: L0s Entry Supported 10: L1 Entry Enabled 11: L0s and L1 Entry Supported Note: “L0s Entry Enabled” indicates the Transmitter entering L0s is supported.
Processor Configuration Registers Table 63. LSTS - Link Status Register (Sheet 2 of 3) Bit Access Default Value RST/ PWR 14 RWC 0b Core Description Link Bandwidth Management Status (LBWMS) This bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status: A link retraining initiated by a write of 1b to the Retrain Link bit has completed.
Processor Configuration Registers Table 63. LSTS - Link Status Register (Sheet 3 of 3) Bit Access Default Value RST/ PWR 3:0 RO 0h Core Description Current Link Speed (CLS) This field indicates the negotiated Link speed of the given PCI Express Link.Defined encodings are: 0001b 2.5 GT/s PCI Express Link All other encodings are reserved. The value in this field is undefined when the Link is not up. 6.2.
Processor Configuration Registers Table 64. SLOTCAP - Slot Capabilities Register (Sheet 2 of 2) Bit Access Default Value RST/ PWR 14:7 RW-O 00h Core Description Slot Power Limit Value (SPLV) In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. If this field is written, the link sends a Set_Slot_Power_Limit message.
Processor Configuration Registers Table 65. SLOTCTL - Slot Control Register (Sheet 2 of 3) Bit Access Default Value RST/ PWR 12 RO 0b Core Description Reserved for Data Link Layer State Changed Enable (DLLSCE) If the Data Link Layer Link Active capability is implemented, when set to 1b, this field enables software notification when Data Link Layer Link Active field is changed.
Processor Configuration Registers Table 65. SLOTCTL - Slot Control Register (Sheet 3 of 3) Bit Access Default Value RST/ PWR 7:6 RO 00b Core Description Reserved for Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.
Processor Configuration Registers 6.2.43 SLOTSTS - Slot Status B/D/F/Type: 0/6/0/PCI Address Offset: BA-BBh Default Value: 0000h Access: RO; RWC Size: 16 bits PCI Express Slot related registers allow for the support of Hot Plug. Table 66. SLOTSTS - Slot Status Register (Sheet 1 of 2) Bit Access Default Value RST/ PWR 15:9 RO 0000000b Core Description Reserved and Zero For future R/WC/S implementations; software must use 0 for writes to bits.
Processor Configuration Registers Table 66. SLOTSTS - Slot Status Register (Sheet 2 of 2) Bit Access Default Value RST/ PWR 5 RO 0b Core Description Reserved for MRL Sensor State (MSS) This register reports the status of the MRL sensor if it is implemented.
Processor Configuration Registers 6.2.44 RCTL - Root Control B/D/F/Type: 0/6/0/PCI Address Offset: BC-BDh Default Value: 0000h Access: RO; RW Size: 16 bits Allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link.
Processor Configuration Registers 6.2.45 RSTS - Root Status B/D/F/Type: 0/6/0/PCI Address Offset: C0-C3h Default Value: 00000000h Access: RO; RWC Size: 32 bits Provides information about PCI Express Root Complex specific parameters. Table 68. RSTS - Root Status Register Bit Access Default Value RST/ PWR 31:18 RO 0000h Core Description Reserved and Zero (RSVD) For future R/WC/S implementations; software must use 0 for writes to bits.
Processor Configuration Registers Table 69. LCTL2 - Link Control 2 Register (Sheet 2 of 3) Bit Access Default Value RST/ PWR 12 RW-S 0b Core Description Compliance De-emphasis (ComplianceDeemphasis): This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. Encodings: 1b -3.5 dB 0b -6 dB When the Link is operating at 2.5 GT/s, the setting of this bit has no effect. Components that support only 2.
Processor Configuration Registers Table 69. LCTL2 - Link Control 2 Register (Sheet 3 of 3) Bit Access Default Value RST/ PWR 6 RW-S 0b Core Description Selectable De-emphasis (selectabledeemphasis): Encodings: 1b) -3.5dB 0b -6 dB Default value is implementation specific, unless a specific value is required for a selected form factor or platform. When the Link is operating at 2.5GT/s speed, the setting of this bit has no effect. Components that support only the 2.
Processor Configuration Registers Table 70. 0 LSTS2 - Link Status 2 Register (Sheet 2 of 2) RO 0b Core Current De-emphasis Level (CURDELVL): Current De-emphasis Level – 1b -3.5 dB 0b -6 dB When the Link is operating at 2.5 GT/s speed, this bit is 0b. 6.2.48 PEGLC - PCI Express-G Legacy Control B/D/F/Type: 0/6/0/PCI Address Offset: EC-EFh Default Value: 00000000h Access: RO; RW Size: 32 bits Controls functionality that is needed by Legacy (non-PCI Express aware) OS's during run time. Table 71.
Processor Configuration Registers 6.3 PCI Device 6 - Extended Configuration Table 72.
Processor Configuration Registers Size: 32 bits Describes the configuration of PCI Express Virtual Channels associated with this port. Table 74.
Processor Configuration Registers Table 75. PVCCAP2 - Port VC Capability Register 2 Bit Access Default Value RST/PWR 31:24 RO 00h Core Description VC Arbitration Table Offset (VCATO): Indicates the location of the VC Arbitration Table. This field contains the zero-based offset of the table in DQWORDS (16 bytes) from the base address of the Virtual Channel Capability Structure. A value of 0 indicates that the table is not present (due to fixed VC priority).
Processor Configuration Registers Table 77. VC0RCAP - VC0 Resource Capability (Sheet 2 of 2) Bit Access Default Value RST/PWR 22:16 RO 00h Core Reserved for Maximum Time Slots 15 RO 0b Core Reject Snoop Transactions (RSNPT): Description Reject Snoop Transactions (RSNPT): 0: Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC.
Processor Configuration Registers Table 78. VC0RCTL - VC0 Resource Control Bit Access Default Value RST/PWR 31 RO 1b Core Description VC0 Enable (VC0E): For VC0 this is hard wired to 1 and read only as VC0 can never be disabled. 30:27 RO 0h Core Reserved 26:24 RO 000b Core VC0 ID (VC0ID): Assigns a VC ID to the VC resource. For VC0 this is hard wired to 0 and read only.
Processor Configuration Registers Table 79. VC0RSTS - VC0 Resource Status Bit Access Default Value RST/PWR 15:2 RO 0000h Core Reserved and Zero 1 RO 1b Core VC0 Negotiation Pending (VC0NP): Description 0: The VC negotiation is complete. 1: The VC resource is still in the process of negotiation (initialization or disabling). This bit indicates the status of the process of Flow Control initialization.
