Intel® Celeron® Dual-Core T1x00 Processors Datasheet For Platforms Based on Mobile Intel® 965 Express Chipset Family October 2008 Document Number: 319734 - 002
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Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 8 1.2 References ......................................................................................................... 9 2 Low Power Features ................................................................................................ 11 2.
Figures 1 2 3 4 5 6 Package-Level Low-Power States ................................................................................11 Core Low-Power States .............................................................................................12 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) .................30 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) .................31 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ...............
Revision History Revision Number Description Date -001 • Initial Release April 2008 -002 • Corrected incorrect listing of BGA CPUs October 2008 § Datasheet 5
Datasheet
Introduction 1 Introduction The Intel® Celeron® Dual-Core processor for Mobile Intel® 965 Express Chipset family-based systems is the first Celeron processor to be a dual-core processor. Built on 65-nanometer process technology, it is based on the Intel® Core™2 microarchitecture. The Celeron Dual-Core processor supports the Mobile Intel® 965 Express Chipset and Intel® 82801HBM ICH8M Controller-Hub Based Systems.
Introduction 1.1 Terminology Term 8 Definition # A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Document Document Number Intel® Celeron® Dual-Core T1x00 Processors Specification Update for Platforms Based on Mobile Intel® 965 Express Chipset Family See http:// www.intel.com/design/ mobile/specupdt/ 319734.
Introduction 10 Datasheet
Low Power Features 2 Low Power Features 2.1 Clock Control and Low Power States The processor supports the C1/AutoHALT, C1/MWAIT, C2, and C3 core low-power states, along with their corresponding package-level states for power management. These package states include Normal, Stop Grant, Stop Grant Snoop, Sleep, and Deep Sleep. The processor’s central power management logic enters a package low-power state by initiating a P_LVLx (P_LVL2, P_LVL3) I/O read to the (G)MCH.
Low Power Features Figure 2.
Low Power Features 2.1.1.3 C1/MWAIT Powerdown State C1/MWAIT is a low-power state entered when the processor core executes the MWAIT instruction. Processor behavior in the C1/MWAIT state is identical to the C1/AutoHALT state except that there is an additional event that can cause the processor core to return to the C0 state: the Monitor event. See the Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 2A/2B: Instruction Set Reference for more information. 2.1.1.
Low Power Features Specification T45). When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP# (AC Specification T75). While in the Stop-Grant state, the processor services snoops and latch interrupts delivered on the FSB. The processor latches SMI#, INIT# and LINT[1:0] interrupts and services only upon return to the Normal state. The PBE# signal may be driven when the processor is in Stop-Grant state.
Low Power Features 2.1.2.5 Deep Sleep State Deep Sleep state is a very low-power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings.
Low Power Features 16 Datasheet
Electrical Specifications 3 Electrical Specifications 3.1 Power and Ground Pins For clean, on-chip power distribution, the processor has a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.
Electrical Specifications Table 2. 18 Voltage Identification Definition (Sheet 2 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 0 1 0 1 1 0 1.2250 0 0 1 0 1 1 1 1.2125 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.
Electrical Specifications Table 2. Datasheet Voltage Identification Definition (Sheet 3 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.
Electrical Specifications Table 2. 3.4 Voltage Identification Definition (Sheet 4 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 1 1 0 1 0 0 0.0500 1 1 1 0 1 0 1 0.0375 1 1 1 0 1 1 0 0.0250 1 1 1 0 1 1 1 0.0125 1 1 1 1 0 0 0 0.0000 1 1 1 1 0 0 1 0.0000 1 1 1 1 0 1 0 0.0000 1 1 1 1 0 1 1 0.0000 1 1 1 1 1 0 0 0.0000 1 1 1 1 1 0 1 0.0000 1 1 1 1 1 1 0 0.0000 1 1 1 1 1 1 1 0.
Electrical Specifications 3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the appropriate chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3. Table 3. 3.
Electrical Specifications Table 4. FSB Pin Groups Signal Group Signals1 Type AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#3, DPWR# Signals AGTL+ Source Synchronous I/O Synchronous to assoc.
Electrical Specifications 3.8 CMOS Signals CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for more than four BCLKs in order for the processor to recognize them. See Section 3.10 for the DC specifications for the CMOS signal groups. 3.
Electrical Specifications 3.10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and signal pin assignments. Table 6 through Table 8 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages.
Electrical Specifications Table 6. DC Voltage and Current Specifications Symbol Parameter VCC VCC of the Processor Core VCC,BOOT Default VCC Voltage for Initial Power Up VCCP AGTL+ Termination Voltage VCCA PLL Supply Voltage ICCDES ICC for processors Recommended Design Targets: Min Typ Max Unit Notes 0.95 1.15 1.30 V 1, 2 V 2, 8 1.20 1.00 1.05 1.10 V 1.425 1.5 1.575 V 36 A ICC for processors ICC Processor Number T1400 IAH, ISGNT 5 A Frequency Die Variant 1.
Electrical Specifications Table 7. FSB Differential BCLK Specifications Symbol Parameter VCROSS Crossing Voltage ΔVCROSS Range of Crossing Points VSWING Differential Output Swing ILI Cpad Input Leakage Current Pad Capacitance Min Typ 0.3 Max Unit Notes1 0.55 V 2, 7, 8 140 mV 2, 7, 5 mV 6 300 -5 0.95 1.2 +5 µA 3 1.45 pF 4 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
Electrical Specifications Table 8. AGTL+ Signal Group DC Specifications Symbol VCCP GTLREF RCOMP RODT Parameter I/O Voltage Typ Max Unit 1.00 1.05 1.10 V V 6 27.78 Ω 10 Ω 11 Reference Voltage Compensation Resistor Notes1 Min 2/3 VCCP 27.23 Termination Resistor 27.5 55 VIH Input High Voltage GTLREF+0.10 VCCP VCCP+0.10 V 3,6 VIL Input Low Voltage -0.10 0 GTLREF-0.10 V 2,4 VOH Output High Voltage VCCP-0.
Electrical Specifications Table 9. CMOS Signal Group DC Specifications Symbol VCCP Parameter I/O Voltage Min Typ Max Unit 1.00 1.05 1.10 V Notes1 VIH Input High Voltage 0.7*VCCP VCCP VCCP+0.1 V 2 VIL Input Low Voltage CMOS -0.10 0.00 0.3*VCCP V 2 VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2 VOL Output Low Voltage -0.10 0 0.1*VCCP V 2 IOH Output High Current 1.5 4.1 mA 5 IOL Output Low Current 1.5 4.
Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information 4.1 Package Mechanical Specifications The processor is available in 4-MB and 2-MB, 478-pin Micro-FCPGA packages. The package mechanical dimensions, keep-out zones, processor mass specifications, and package loading specifications are shown in Figure 3 through Figure 6. The mechanical package pressure specifications are in a direction normal to the surface of the processor.
Package Mechanical Specifications and Pin Information Figure 3. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) h Bottom View Top View Front View Side View & ' %( ! "# $% $ ) P Detail A 30 + ,- 1--1 .0.2 1/ * * * * 1 1 1 1 1 1 )1.
Package Mechanical Specifications and Pin Information Figure 4. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) "# $ %& ' Side View ( ( $ %& ' Top View ø0.305±0.25 ø0.406 M C A B ø0.
Package Mechanical Specifications and Pin Information Figure 5. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) Bottom View Top View Front View Side View & ' %( ! "# $% $ ) P Detail A 32 + , 1--1 .0.2 1/ * * , .
Package Mechanical Specifications and Pin Information Figure 6. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) "# $ %& ' Side View ( ( $ %& ' Top View ø0.305±0.25 ø0.406 M C A B ø0.254 M C ! ! ! ! 4.2 Bottom View Processor Pinout and Pin List Table 11 shows the top view pinout of the Intel Celeron Dual-Core processor.
Package Mechanical Specifications and Pin Information Table 11.
Package Mechanical Specifications and Pin Information Table 12.
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Package Mechanical Specifications and Pin Information Table 13. Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name (Sheet 3 of 16) Pin Number Signal Buffer Type Direction BR0# F1 Common Clock Input/ Output BSEL[0] B22 CMOS Output BSEL[1] B23 CMOS Output BSEL[2] C21 CMOS COMP[0] R26 COMP[1] Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name (Sheet 5 of 16) Pin Number Signal Buffer Type Direction D[37]# T22 Source Synch Input/ Output D[38]# U25 Source Synch D[39]# U23 D[40]# Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name (Sheet 7 of 16) Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name (Sheet 9 of 16) Pin Number Signal Buffer Type VCC AA13 Power/Other VCC AA15 VCC Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name (Sheet 11 of 16) Pin Number Signal Buffer Type VCC E12 Power/Other VCC E13 VCC Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name (Sheet 13 of 16) Pin Number Signal Buffer Type VSS AC14 Power/Other VSS AC16 VSS Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name (Sheet 15 of 16) Pin Number Signal Buffer Type VSS F16 Power/Other VSS F19 VSS F22 Pin Name Table 13.
Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number (Sheet 2 of 17) Pin Number Signal Buffer Type VSS A8 Power/Other VCC A9 VCC A10 Pin Name Table 14.
Package Mechanical Specifications and Pin Information Table 14.
Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number (Sheet 6 of 17) Pin Number Signal Buffer Type Direction VID[2] AE5 CMOS Output PSI# AE6 CMOS VSSSENSE AE7 Power/Other Pin Name Table 14.
Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number (Sheet 8 of 17) Pin Number Signal Buffer Type Direction BSEL[0] B22 CMOS Output BSEL[1] B23 CMOS Output VSS B24 Pin Name Table 14.
Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number (Sheet 10 of 17) Pin Number Signal Buffer Type VCC E12 Power/Other VCC E13 VSS Table 14.
Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number (Sheet 12 of 17) Pin Number Signal Buffer Type VSS H6 Power/Other VSS H21 Power/Other D[12]# H22 Source Synch Pin Name Direction Input/ Output Input/ Output D[15]# H23 Source Synch VSS H24 Power/Other DINV[0]# H25 Source Synch Input/ Output Table 14.
Package Mechanical Specifications and Pin Information Table 14.
Package Mechanical Specifications and Pin Information Table 14.
Package Mechanical Specifications and Pin Information 4.3 Alphabetical Signals Reference Table 15. Signal Description (Sheet 1 of 7) Name A[35:3]# A20M# Type Description Input/ Output A[35:3]# (Address) define a 236-byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB.
Package Mechanical Specifications and Pin Information Table 15. Name Signal Description (Sheet 2 of 7) Type Description BSEL[2:0] Output BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency.
Package Mechanical Specifications and Pin Information Table 15. Name Signal Description (Sheet 3 of 7) Type Description DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent inverts the data bus signals if more than half the bits, within the covered group, would change level in the next cycle.
Package Mechanical Specifications and Pin Information Table 15. Name FERR#/PBE# Signal Description (Sheet 4 of 7) Type Output Description FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating point when the processor detects an unmasked floatingpoint error.
Package Mechanical Specifications and Pin Information Table 15. Name LINT[1:0] Signal Description (Sheet 5 of 7) Type Description Input LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Intel® Pentium® processor. Both signals are asynchronous.
Package Mechanical Specifications and Pin Information Table 15. Name Signal Description (Sheet 6 of 7) Type Description RESET# Input Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents deasserts their outputs within two clocks.
Package Mechanical Specifications and Pin Information Table 15. Name Signal Description (Sheet 7 of 7) Type Description Output The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor stops all execution when the junction temperature exceeds approximately 125 °C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin.
Package Mechanical Specifications and Pin Information 60 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features.
Thermal Specifications and Design Considerations 5.1.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal diode, with its collector shorted to ground. The thermal diode can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard or a stand-alone measurement kit.
Thermal Specifications and Design Considerations Table 18. Thermal Diode Parameters Using Diode Model Symbol IFW Parameter Min Typ Max Unit Notes 200 µA 1 Ω 2, 3, 5 Forward Bias Current 5 n Diode Ideality Factor 1.000 1.009 1.050 RT Series Resistance 2.79 4.52 6.24 2, 3, 4 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias.
Thermal Specifications and Design Considerations Table 19. Thermal Diode Parameters Using Transistor Model Symbol Parameter Min IFW Forward Bias Current IE Emitter Current nQ Transistor Ideality 5 5 0.997 Beta RT Typ 1.001 0.3 Series Resistance 2.79 4.52 Max Unit Notes 200 μA 1,2 200 μA 1 1.005 3,4,5 0.760 3,4 6.24 Ω 3,6 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 18. 3.
Thermal Specifications and Design Considerations If the ntrim value used to calculate the Toffset differs from the ntrim value used to in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset can be adjusted by calculating nactual and then recalculating the offset using the ntrim as defined in the temperature sensor manufacturer’s datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 20. Table 20. 5.1.
Thermal Specifications and Design Considerations Intel Thermal Monitor 1 and 2 can co-exist within the processor. If both Intel Thermal Monitor 1 and 2 bits are enabled in the auto-throttle MSR, Intel Thermal Monitor 2 takes precedence over Intel Thermal Monitor 1.
Thermal Specifications and Design Considerations Unlike traditional thermal devices, the DTS will output a temperature relative to the maximum supported operating temperature of the processor (TJ,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the DTS will always be at or below TJ,max. Catastrophic temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the DTS MSR.
Thermal Specifications and Design Considerations When PROCHOT# is driven by an external agent, if only Intel Thermal Monitor 1 is enabled on both cores, then both processor cores will have their core clocks modulated. If Intel Thermal Monitor 2 is enabled on both cores, then both processor cores will enter the lowest programmed Intel Thermal Monitor 2 performance state.
