Intel® Celeron® D Processor 300Δ Sequence Specification Update – On 65 nm Process in the 775-land LGA Package August 2008 Revision 010 Document Number: 311827-010
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Contents Preface............................................................................................................................. 5 Summary Tables of Changes................................................................................................ 7 Identification Information .................................................................................................. 12 Errata ............................................................................................................
Revision History Revision Description Date -001 • Initial release of the Intel® Celeron® D Processor 300 Sequence Specification Update May 2006 Out of Cycle -002 • Added Erratum AD23, AD24 and AD25. June 2006 -003 • Added RTT Specification Change July 2006 -004 • Added D step information. Aug 2006 Out Of Cycle • Added information for processor number 360 005 • Added Specification change AD1. -006 • Added information for processor number 347.
Preface Preface This document is an update to the specifications contained in the documents listed the following Affected Documents/Related Documents table. It is a compilation device and document errata and specification clarifications and changes, and intended for hardware system manufacturers and for software developers applications, operating system, and tools.
Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number. QDF Number is a several digit code that is used to distinguish between engineering samples. These processors are used for qualification and early design validation.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes 8 E= Intel® Pentium® III processor F= Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor I= Dual-Core Intel® Xeon® processor 5000 series J= 64-bit Intel® Xeon® processor MP with 1MB L2 cache K= Mobile Intel® Pentium® III processor L= Intel® Celeron® D processor M= Mobile Intel® Celeron® processor N= Intel® Pentium® 4 processor O= Intel® Xeon® processor MP P= Intel ® Xeon® processor Q= Mobile Intel® Pentium® 4 processor supporting Hyper-
Summary Tables of Changes AJ = Quad-Core Intel® Xeon® processor 5300 series AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor Q6000 sequence AL = Dual-Core Intel® Xeon® processor 7100 series AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® dual-core processor AO = Quad-Core Intel® Xeon® processor 3200 series AP = Dual-Core Intel® Xeon® processor 3000 series AQ = Intel® Pentium® dual-core desktop processor E2000 sequence AR = Int
Summary Tables of Changes Steppings Number Plans ERRATA B1 C1 D0 AD1 X X X No Fix Memory Aliasing of Pages as Uncacheable Memory Type and Write Back (WB) May Hang the System AD2 X X X No Fix Data Breakpoints on the High Half of a Floating Point Line Split may not be Captured AD3 X X X No Fix Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR Registers AD4 X X X No Fix FXRSTOR May Not Restore Non-canonical Effective Addresses on Processors with Intel® Extended Memory 64 Tech
Summary Tables of Changes Steppings AD20 X X X No Fix Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations AD21 X X X No Fix Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue AD22 X X X No Fix The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is not set when Multiple Un-correctable Machine Check Errors Occur at the Same Time AD23 X X X No Fix Processor May Fault When the Upp
Identification Information Identification Information Figure 1. Intel® Celeron® D Processor 300 sequence Package supporting 775_VR_CONFIG_05A Specifications (Top Markings for C1 stepping) Figure 2.
Identification Information Component Identification Information The Intel® Celeron® D Processor on 65 nm process can be identified by the following values: Family1 Model2 1111b 0110b NOTES: 1. 2. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.
Errata Errata AD1. Memory Aliasing of Pages as Uncacheable Memory Type and Write Back (WB) May Hang the System Problem: When a page is being accessed as either Uncacheable (UC) or Write Combining (WC) and WB, under certain bus and memory timing conditions, the system may loop in a continual sequence of UC fetch, implicit writeback, and Request For Ownership (RFO) retries. Implication: This erratum has not been observed in any commercially available operating system or application.
Errata AD4. Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR Registers Problem: When an access is made to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an expected #GP fault may not happen. Implication: A read of the MSR_LASTBRANCH_0_FROM_LIP MSR register may not cause a #GP fault. Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes. AD5.
Errata Implication: If software sets such invalid physical address in those tables, the processor does not generate a page fault (#PF) upon access to that virtual address, and the access results in an incorrect read or write. If BIOS provides only valid physical address ranges to the operating system, this erratum will not occur. Workaround: BIOS must provide valid physical address ranges to the operating system. Status: F006Fr the steppings affected, see the Summary Tables of Changes. AD8.
Errata AD10. Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS Instruction with Fast Strings Enabled Problem: Under limited circumstances while executing a REP MOVS/STOS string instruction, with fast strings enabled, it is possible for the value in CR2 to be changed as a result of an interim paging event, normally invisible to the user. Any higher priority architectural event that arrives and is handled while the interim paging event is occurring may see the modified value of CR2.
Errata AD13. Two Correctable L2 Cache Errors in Close Proximity May Cause a System Hang Problem: If two correctable L2 cache errors are detected in close proximity to each other, a livelock may occur as a result of the processor being unable to resolve this condition. Implication: When this erratum occurs, the processor may livelock and result in a system hang. Intel has only observed this erratum while injecting cache errors in simulation. Workaround: None identified.
Errata AD16. Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set.
Errata AD19.
Errata AD21. Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Problem: Software which is written so that multiple agents can modify the same shared unaligned memory location at the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boundary.
Errata Status: For the steppings affected, see the Summary Tables of Changes. AD24. The Processor May Issue Front Side Bus Transactions up to 6 Clocks after RESET# Is Asserted Problem: The processor may issue transactions beyond the documented 3 Front Side Bus (FSB) clocks and up to 6 FSB clocks after RESET# is asserted in the case of a warm reset. A warm reset is where the chipset asserts RESET# when the system is running.
Errata § Specification Update 23
Specification Changes Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Celeron® D Processor 300 Sequence – On 65nm Process in the 775-Land Package Datasheet All Specification Changes will be incorporated into a future version of the appropriate Celeron® D processor documentation. AD1.
Specification Clarifications Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel® Celeron® D Processor 300 Sequence – On 65nm Process in the 775-Land Package Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate Celeron® D processor documentation.
Documentation Changes Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Celeron® D Processor 300 Sequence – On 65nm Process in the 775-Land Package Datasheet All Documentation Changes will be incorporated into a future version of the appropriate Celeron® D processor documentation.
