Intel® Celeron® Processor 550 Datasheet Addendum Addendum for Intel Celeron Processor 500 Series Datasheet For Platforms Based on Mobile Intel® 965 Express Chipset Family January 2008 Document Number: 319219-001
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Contents 1 Introduction .............................................................................................................. 5 1.1 Terminology ....................................................................................................... 6 1.2 References .........................................................................................................6 2 Package Mechanical Specifications and Pin Information ............................................ 7 2.
Revision History Document Number 319219 Description Date Initial Release January 2008 § 4
Introduction 1 Introduction This document is an addendum to the datasheet for the Intel® Celeron® processor 500 series for platforms based on Mobile Intel® 965 Express Chipset family. It is based on the new Intel® Core™ microarchitecture. In this document, the Celeron processor 500 series will be referred to as the Celeron processor, or simply the processor. This document adds the 479-pin uFCBGA packaging diagrams that are supported for Intel embedded customers.
Introduction 1.1 Terminology Term 1.2 Definition # A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted.
Package Mechanical Specifications and Pin Information 2 Package Mechanical Specifications and Pin Information 2.1 Package Mechanical Specifications The Celeron processor 550 series will have two variants, both may be available in a 478-pin Micro-FCPGA (not shown in this addendum, see Intel Celeron Processor 500 Series Datasheet for reference) or 479-pin Micro-FCBGA package (illustrated in this addendum).
Package Mechanical Specifications and Pin Information Figure 1. 1 MB Configured Micro-FCBGA Processor Package Drawing (1 of 2) ' ' ' ' #' # Top View Bottom View !!" M Front View Detail B $ !% & Side View $( )% *+",- ,% .
Package Mechanical Specifications and Pin Information Figure 2.
Package Mechanical Specifications and Pin Information Figure 3. 1 MB Micro-FCBGA Processor Package Drawing (1 of 2) ' ' ' ' #' # Top View Bottom View !!" M Front View Detail B $ !% & Side View $( )% *+",- ,% .
Package Mechanical Specifications and Pin Information Figure 4.
Package Mechanical Specifications and Pin Information 12
