Mobile Intel® Celeron® Processor on .13 Micron Process in Micro-FCPGA Package Specification Update October 2005 Notice: The mobile Intel® Celeron® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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R Contents Revision History............................................................................................................................4 Preface .........................................................................................................................................6 Summary of Changes...................................................................................................................8 Identification Information .................................................
R Revision History Revision Number 4 Description Date -001 Initial Release June 2002 -002 Updated Identification Information table. August 2002 -003 Updated Documentation Change summary by removing old items that have been incorporated into the Software Developer’s Manual; Added errata V30-V32; Added Documentation Changes V3-V24.
R -027 Updated Related Documents table July 2005 -028 Added errata V50 and updated Processor Identification Table.
R Preface This document is an update to the specifications contained in the document listed in the following Affected/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
R Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number. Errata are design defects or errors. Errata may cause the mobile Intel Pentium 4 processor-m’s behavior to deviate from published specifications.
R Summary of Changes The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Intel Pentium 4 processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted.
R L = Intel ® Celeron ® D processor M = Mobile Intel ® Celeron ® processor N = Intel ® Pentium ® 4 processor O = Intel ® Xeon™ processor MP P = Intel ® Xeon™ processor Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on 90-nm process technology R = Intel® Pentium® 4 processor on 90 nm process S = 64-bit Intel® Xeon™ processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) T = Mobile Intel® Pentium® 4 processor-M V = Mobile Intel® Celeron® processor on .
R Steppings NO.
R Steppings NO.
R Identification Information The mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA package can be identified by the following values: 1 Family Model 1111 0010 2 Brand ID 3 00001000 4 5 1111 0010 00001111 NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after Reset, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2.
R Table 1. Mobile Intel® Celeron® Processor Identification Information S-Spec Product Stepping L2 Cache Size (bytes) CPU Signature Core Frequency Bus Frequency Voltage Package Notes SL6FM B0 256 K 0F24h 1.4 GHz 400 MHz 1.3 V Micro-FCPGA 1 SL6FN B0 256 K 0F24h 1.5 GHz 400 MHz 1.3 V Micro-FCPGA 1 SL6M4 C1 256 K 0F27h 1.4 GHz 400 MHz 1.3 V Micro-FCPGA SL6M5 C1 256 K 0F27h 1.5 GHz 400 MHz 1.3 V Micro-FCPGA SL6J2 C1 256 K 0F27h 1.6 GHz 400 MHz 1.
R Component Marking Information ® ® Figure 1. Mobile Intel Celeron Processor on .
R Errata V1. I/O Restart in SMM may Fail after Simultaneous Machine Check Exception (MCE) Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the processor will signal a Machine Check Exception (MCE). If the instruction is directed at a device that is powered down, the processor may also receive an assertion of SMI#.
R V3. Transaction Is Not Retried after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, it will not be retried. Implication: When this erratum occurs, locked transactions will unexpectedly not be retried. Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes. V4.
R V6. The Processor Signals Page-Fault Exception (#PF) Instead of Alignment Check Exception (#AC) on an Unlocked CMPXCHG8B Instruction Problem: If a Page-Fault Exception (#PF) and Alignment Check Exception (#AC) both occur for an unlocked CMPXCHG8B instruction, then #PF will be flagged. Implication: Software that depends on the Alignment Check Exception (#AC) before the Page-Fault Exception (#PF) will be affected since #PF is signaled in this case.
R V9. The IA32_MC1_STATUS Register May Contain Incorrect Information for Correctable Errors Problem: When a speculative load operation hits the L2 cache and receives a correctable error, the IA32_MC1_STATUS register may be updated with incorrect information. The IA32_MC1_STATUS register should not be updated for speculative loads. Implication: When this erratum occurs, the IA32_MC1_STATUS register will contain incorrect information for correctable errors.
R V11. Machine Check Architecture Error Reporting and Recovery May Not Work As Expected Problem: When the processor detects errors it should attempt to report and/or recover from the error. In the situations described below, the processor does not report and/or recover from the error(s) as intended. When a transaction is deferred during the snoop phase and subsequently receives a Hard Failure response, the transaction should be removed from the bus queue so that the processor may proceed.
R may latch invalid information. - If RESET# is asserted, then de-asserted, and reasserted, before the processor has cleared the MCA registers, then the information in the MCA registers may not be reliable, regardless of the state or state transitions of PWRGOOD. - If MCERR# is asserted by one processor and observed by another processor, the observing processor does not log the assertion of MCERR#.
R V13. EMON Event Counting of x87 Loads May Not Work As Expected Problem: If a performance counter is set to count x87 loads and floating point exceptions are unmasked, the FPU Operand Data Pointer (FDP) may become corrupted. Implication: When this erratum occurs, the FPU Operand Data Pointer (FDP) may become corrupted. Workaround: This erratum will not occur with floating point exceptions masked. If floating point exceptions are unmasked, then performance counting of x87 loads should be disabled.
R V17. Multiple Accesses to the Same S-State L2 Cache Line and ECC Error Combination May Result in Loss of Cache Coherency Problem: When a Read for Ownership (RFO) cycle has a 64 bit address match with an outstanding read hit on a line in the L2 cache which is in the S-state AND that line contains an ECC error, the processor should recycle the RFO until the ECC error is handled.
R V20. Associated Counting Logic Must Be Configured When Using Event Selection Control (ESCR) MSR Problem: ESCR MSRs allow software to select specific events to be counted, with each ESCR usually associated with a pair of performance counters. ESCRs may also be used to qualify the detection of at-retirement events that support precise-event-based sampling (PEBS). A number of performance metrics that support PEBS require a 2nd ESCR to tag uops for the qualification of at-retirement events.
R V23. BPM[5:3]# and GHI# VIL Does Not Meet Specification Problem: The VIL for BPM[5:3]# and GHI# is specified as 0.9 * GTLREF [V]. Due to this erratum the VIL for these signals is 0.9 * GTLREF - .075 [V]. Implication: The processor requires a lower input voltage than specified to recognize a low voltage on the BPM[5:3]# and GHI# signals. Workaround: When intending to drive the BPM[5:3]# or GHI# signals low, ensure that the system provides a voltage lower than 0.9 * GTLREF - .075 [V].
R V26. L2 Cache May Contain Stale Data in the Exclusive State Problem: If a cacheline (A) is in Modified (M) state in the write-combining (WC) buffers and in the Invalid (I) state in the L2 cache and its adjacent sector (B) is in the Invalid (I) state and the following scenario occurs: 1. A read to B misses in the L2 cache and allocates cacheline B and its associated second-sector prefetch into an almost full bus queue, 2.
R V28. Erroneous BIST Result Found in EAX Register after Reset Problem: The processor may show an erroneous BIST (built-in self test) result in the EAX register bit 0 after reset. Implication: When this erratum occurs, an erroneous BIST failure will be reported in the EAX register bit 0, however this failure can be ignored since it is not accurate. Workaround: It is possible for BIOS to workaround this issue by masking off bit 0 in the EAX register where BIST results are written.
R V32. CPUID Instruction Returns Incorrect Number of ITLB Entries Problem: When CPUID is executed with EAX = 2 it should return a value of 51h in EAX[15:8] to indicate that the Instruction Translation Lookaside Buffer (ITLB) has 128 entries. Due to this erratum, the processor returns 50h (64 entries). Implication: Software may incorrectly report the number of ITLB entries. Operation of the processor is not affected. Workaround: None identified.
R V35. Parity Error in the L1 Cache may Cause the Processor to Hang Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the processor may hang while trying to evict the line. Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any commercially available software. Workaround: None. Status: For the steppings affected, see the Summary Tables of Changes. V36.
R V38. Changes to CR3 Register do not Fence Pending Instruction Page Walks Problem: When software writes to the CR3 register, it is expected that all previous/outstanding code, data accesses and page walks are completed using the previous value in CR3 register. Due to this erratum, it is possible that a pending instruction page walk is still in progress, resulting in an access (to the PDE portion of the page table) that may be directed to an incorrect memory address.
R V41. A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May Cause an Incorrect Address to Be Reported to the #GP Exception Handler Problem: If a 16-bit application executes a branch instruction that causes an address wrap to a target address outside of the code segment, the address of the branch instruction should be provided to the general protection exception handler.
R V44. Memory Aliasing of Pages as Uncacheable Memory Type and Write Back (WB) May Hang the System Problem: When a page is being accessed as either Uncacheable (UC) or Write Combining (WC) and WB, under certain bus and memory timing conditions, the system may loop in a continual sequence of UC fetch, implicit writeback, and Request For Ownership (RFO) retries. Implication: This erratum has not been observed in any commercially available operating system or application.
R V47.
R V49. Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS Instruction with Fast Strings Enabled Problem: Under limited circumstances, while executing a REP MOVS/STOS string instruction with fast strings enabled, it is possible for the value in CR2 to be changed as a result of an interim paging event, normally invisible to the user. Any higher priority architectural event that arrives and is handled while the interim paging event is occurring may see the modified value of CR2.
R Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Mobile Intel® Celeron® Processor on .13 Micron Process in Micro-FCPGA Package Datasheet (Document Number 251308) All Specification Clarifications will be incorporated into a future version of the appropriate mobile Intel Celeron processor on 0.13 micron process in Micro-FCPGA Package documentation. V1.
R RESET, the counter will increment even when the processor is halted by the HLT instruction or the external STPCLK# pin. Note that the assertion of the external DPSLP# pin may cause the time-stamp counter to stop.
R Technology is enabled, both logical processors must be halted for performance-monitoring counters to be powered down. • The processor is asleep as a result of being halted or because of a power-management scheme. There are different levels of sleep. In the some deep sleep levels, the time-stamp counter stops counting. There are three ways to count processor clock cycles to monitor performance.
R Specification Changes The Specification Changes listed in this section apply to the following documents: • Mobile Intel® Celeron® Processor on .13 Micron Process in Micro-FCPGA Package Datasheet (Document Number 251308) All Specification Changes will be incorporated into a future version of the appropriate mobile Intel Celeron processor on 0.13 micron process in Micro-FCPGA package documentation. V1.
R V2. BR0# Maximum Hold Time Specification Change The BR0# maximum hold time has changed to 2 BCLKs. This change will be shown in the “System Bus AC Specifications (Reset Conditions)” table and “System Bus Reset and Configuration Timings” figure of the Mobile Intel® Celeron® Processor on .13 Micron Process in Micro-FCPGA Package Datasheet. This change will be incorporated in the next revision of the datasheet. Currently it states: Table 21.
R The following figure will be modified to reflect this change: Figure 12.
R Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Mobile Intel® Celeron® Processor on .13 Micron Process in Micro-FCPGA Package Datasheet (Document Number 251308) Note: Documentation changes for IA-32 Intel® Architecture Software Developer’s Manual volumes 1, 2, and 3 are posted in a separate document IA-32 Intel® Architecture Software Developer’s Manual Documentation Changes. This document has been posted to http://developer.intel.
