Specification Update

ManualsBrandsIntel ManualsOtherIntel Celeron Processor 733 MHz, 128K Cache, 66 MHz FSB

Mobile Intel







Celeron







Processor at 466 MHz, 433 MHz,

400 MHz, 366 MHz, 333 MHz,

300 MHz, and 266 MHz

Specification Update

Release Date: December 2002

Order Number: 244444-039

The Mobile Intel

Celeron

processor at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, and 266 MHz may

contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current

characterized errata are documented in this Specification Update.

Summary of content (65 pages)

PAGE 1
  Mobile Intel Celeron Processor at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, and 266 MHz Specification Update Release Date: December 2002 Order Number: 244444-039 The Mobile Intel® Celeron® processor at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, and 266 MHz may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
PAGE 2
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, and 266 MHz SPECIFICATION UPDATE Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
PAGE 3
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE CONTENTS REVISION HISTORY....................................................................................................................................... ii PREFACE........................................................................................................................................................ v GENERAL INFORMATION...............................................
PAGE 4
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, and 266 MHz SPECIFICATION UPDATE REVISION HISTORY Date of Revision Version Description January 1999 -001 This document is the first Specification Update for the Intel® Mobile Celeron® processor. March 1999 -002 Updated the Documentation Changes and Specifications Clarifications sections. Changed S-Spec Definition. April 1999 -003 Added Erratum H43.
PAGE 5
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE REVISION HISTORY Date of Revision Version Description March 2000 -013 Updated the General Information markings. Updated Preface document reference. Revised Erratum H48 and added Erratum H53. April 2000 -014 Updated the Preface with new references; Updated the Intel Celeron Processor Mobile Module Markings section. June 2000 -015 Added Erratum H54.
PAGE 6
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, and 266 MHz SPECIFICATION UPDATE REVISION HISTORY Date of Revision Version Description July 2002 -034 Updated Summary of Changes; Removed old items that have been added to the Software Developers Manual; Added Documentation Change H4, H5, H6, H7, H8, H9, H10, H11, H12, and H13.
PAGE 7
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE PREFACE This document is an update to the specifications contained in the following documents: • P6 Family of Processors Hardware Developer’s Manual (Order Number 244001) • Intel® Mobile Celeron® Processor in Micro-PGA and BGA Package at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz and 266 MHz datasheet (Order Number 245112) • Intel® Celeron® Processor Mobile Module: Mobile Mo
PAGE 8
PAGE 9
Specification Update for the Mobile Intel® Celeron® Processor at 466 MHz, 433 MHz,400 MHz, 366 MHz, 333 MHz, 300 MHz, and 266 MHz
PAGE 10
PAGE 11
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE GENERAL INFORMATION Mobile Intel® Celeron® Processor in Micro-PGA Package S-spec# FPO# FFFFFFFF SXXXX KP ZZZ/CCC Package Designator Cache Speed INTEL M C ‘YY 2D Matrix (supplier Lot ID + SER#) Legal Requirements (YY = Year) 1
PAGE 12
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Mobile Intel® Celeron® Processor in BGA1 Package FPO Package Designator S-spec FFFFFFFF SXXX KC ZZZ/CCC Cache Speed INTEL M C ‘YY 2D Matrix (Supplier Lot ID + SER#) 2 Legal (YY = Year)
PAGE 13
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Intel® Celeron® Processor Mobile Module Markings The Product Tracking Code (PTC) determines the Intel assembly level of the module.
PAGE 14
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Intel® Celeron® Processor Mobile Module (MMC-1) 4
PAGE 15
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Intel® Celeron® Processor Mobile Module (MMC-2) 5
PAGE 16
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE IDENTIFICATION INFORMATION The Mobile Intel® Celeron® processor or the Intel® Celeron® Processor Mobile Module can be identified by the following values: Family1 266, 300, 333, 366 , 400, 433, 466 MHz Model 62 Brand ID 0110 0110 00h (not supported) NOTES: 1.
PAGE 17
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Mobile Intel® Celeron® Processor Identification Information S-Spec Product Steppings CPU Signature Speed (MHz) Core/Bus SL23X mcbA0 066Ah SL23Y mcbA0 066Ah Package Notes 233/66 Integrated L2 Size (Kbytes) 128 BGA 1 266/66 128 BGA 1 SL3AH mcbA0 066Ah 300/66 128 BGA 1 SL3C8 mcbA0 066Ah 333/66 128 BGA 1 SL3C7 mcbA0 066Ah 366/66 128 BGA 1 SL3DQ mcbA0 0
PAGE 18
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Intel® Celeron® Processor Mobile Module Identification Information PTC Product Steppings CPU Signature Speed (MHz) Core/Bus PMH26601001AA cmmA0 066Ah PMH30001001AA cmmA0 PMH33301001AA PMH36601001AA Package Notes 266/66 Integrated L2 Size (Kbytes) 128 MMC-1 1 066Ah 300/66 128 MMC-1 1 cmmA0 066Ah 333/66 128 MMC-1 1 cmmA0 066Ah 366/66 128 MMC-1 1 PMH40001001AA
PAGE 19
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE SUMMARY OF CHANGES The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Mobile Intel® Celeron® processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted.
PAGE 20
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE SUMMARY OF ERRATA NO.
PAGE 21
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE SUMMARY OF ERRATA NO.
PAGE 22
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE SUMMARY OF ERRATA NO.
PAGE 23
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE SUMMARY OF ERRATA NO. mcbA0 mcpA0 cmmA0 Plans ERRATA H66 X X X NoFix Under some complex conditions, the instructions in the Shadow of a JMP FAR may be Unintentionally Executed and Retired H67 X X X NoFix Processor Does not Flag #GP on Non-zero Write to Certain MSRs SUMMARY OF DOCUMENTATION CHANGES NO.
PAGE 24
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE ERRATA H1. FP Data Operand Pointer May Be Incorrectly Calculated After FP Access Which Wraps 64-Kbyte Boundary in 16-Bit Code Problem: The FP Data Operand Pointer is the effective address of the operand associated with the last noncontrol floating-point instruction executed by the machine.
PAGE 25
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H2.
PAGE 26
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H3. Code Fetch Matching Disabled Debug Register May Cause Debug Exception Problem: The bits L0-3 and G0-3 enable breakpoints local to a task and global to all tasks, respectively. If one of these bits is set, a breakpoint is enabled, corresponding to the addresses in the debug registers DR0 - DR3. If at least one of these breakpoints is enabled, any of these registers are disabled (e.g.
PAGE 27
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H5. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is not exactly representable in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally set by the processor.
PAGE 28
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H7. I/O Restart in SMM May Fail After Simultaneous MCE Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the Intel Mobile Celeron processor will signal a machine check exception (MCE).
PAGE 29
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H10. MCE Due to L2 Parity Error Gives L1 MCACOD.LL Problem: If a Cache Reply Parity (CRP) error, Cache Address Parity (CAP) error, or Cache Synchronous Error (CSER) occurs on an access to the Mobile Intel Celeron processor’s L2 cache, the resulting Machine Check Architectural Error Code (MCACOD) will be logged with ‘01’ in the LL field.
PAGE 30
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H13. Potential Early Deassertion of LOCK# During Split-Lock Cycles Problem: During a split-lock cycle there are four bus transactions: 1st ADS# (a partial read), 2nd ADS# (a partial read), 3rd ADS# (a partial write), and the 4th ADS# (a partial write).
PAGE 31
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H15. Reporting of Floating-Point Exception May Be Delayed Problem: The Mobile Intel Celeron processor normally reports a floating-point exception for an instruction when the next floating-point or MMX™ technology instruction is executed.
PAGE 32
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H17. Built-in Self Test Always Gives Nonzero Result Problem: The Built-in Self Test (BIST) of the Mobile Intel Celeron processor does not give a zero result to indicate a passing test. Regardless of pass or fail status, bit 6 of the BIST result in the EAX register after running BIST is set.
PAGE 33
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE 3. If there is an unmasked floating-point exception pending, then the store could happen prior to the triggered unmasked floating-point exception. 4. If CR0.TS = 1 (Task Switched bit), then the store could happen prior to the triggered Device Not Available (DNA) exception.
PAGE 34
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Workaround: Bus agents must consider transaction type to determine the validity of the Memory Type field for a transaction. Status: For the steppings affected see the Summary of Changes at the beginning of this section. H22.
PAGE 35
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H23. MOVD Following Zeroing Instruction Can Cause Incorrect Result Problem: An incorrect result may be calculated after the following circumstances occur: 1. A register has been zeroed with either a SUB reg, reg instruction or an XOR reg, reg instruction 2.
PAGE 36
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE 1. Rather than using the MOVSX-MOVD or CBW-MOVD pairing to handle one variable at a time, use the sign extension capabilities (PSRAW, etc.) within MMX technology for operating on multiple variables. This would result in higher performance as well. 2.
PAGE 37
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Workaround: Hardware and software developers who write device drivers for custom hardware that may have a side-effect style of design should use simple loads and simple stores to transfer data to and from the device. Then, the memory location will simply be read twice with no additional implications.
PAGE 38
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H28. Mixed Cacheability of Lock Variables Is Problematic in MP Systems Problem: This errata only affects multiprocessor systems where a lock variable address is marked cacheable in one processor and uncacheable in any others. The processors which have it marked uncacheable may stall indefinitely when accessing the lock variable.
PAGE 39
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE L2 Cache SMBALERT# Thermal Sensor SMBCLK SMBDATA Processor Core 3 SMBCLK SMBDATA SMBALERT# SMBALERT# South Bridge THRM# Micro-Controller SMBCLK SMBDATA Figure 1. An Example of Microcontroller Driven Thermal Management Implication: There is no system impact from this erratum if temperature polling is used for processor thermal management.
PAGE 40
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Figure 2.
PAGE 41
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Figure 3. Workaround Flowchart: SMI#-Driven System Status: For the steppings affected see the Summary of Changes at the beginning of this section.
PAGE 42
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H30. MOV With Debug Register Causes Debug Exception Problem: When in V86 mode, if a MOV instruction is executed on debug registers, a general-protection exception (#GP) should be generated, as documented in the Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide, Section 15.2.
PAGE 43
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H32. Incorrect Memory Type May be Used When MTRRs Are Disabled Problem: If the Memory Type Range Registers (MTRRs) are disabled without setting the CR0.
PAGE 44
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H34. Data Breakpoint Exception in a Displacement Relative Near Call May Corrupt EIP Problem: If a misaligned data breakpoint is programmed to the same cache line as the memory location where the stack push of a near call is performed and any data breakpoints are enabled, the processor will update the stack and ESP appropriately, but may skip the code at the destination of the call.
PAGE 45
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H37. RDMSR or WRMSR To Invalid MSR Address May Not Cause GP Fault Problem: The RDMSR and WRMSR instructions allow reading or writing of MSRs (Model Specific Registers) based on the index number placed in ECX. The processor should reject access to any reserved or unimplemented MSRs by generating #GP(0).
PAGE 46
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H39. PRELOAD Followed by EXTEST Does Not Load Boundary Scan Data Problem: According to the IEEE 1149.1 Standard, the EXTEST instruction would use data “typically loaded onto the latched parallel outputs of boundary-scan shift-register stages using the SAMPLE/PRELOAD instruction prior to the selection of the EXTEST instruction.
PAGE 47
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H42. Resume Flag May Not Be Cleared After Debug Exception Problem: The Resume Flag (RF) is normally cleared by the processor after executing an instruction which causes a debug exception (#DB). In the process of determining whether the RF needs to be cleared after executing the instruction, the processor uses an internal register containing stale data.
PAGE 48
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H44. Internal Cache Protocol Violation May Cause System Hang Problem: An Mobile Intel Celeron processor based system may hang due to an internal cache protocol violation. During multiple transactions targeted at the same cacheline, there exists a small window of time such that the processor's internal timings align to create a livelock situation.
PAGE 49
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H46. Machine Check Exception May Occur Due to Improper Line Eviction in the IFU Problem: The Mobile Intel Celeron processor is designed to signal an unrecoverable Machine Check Exception (MCE) as a consistency checking mechanism.
PAGE 50
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H48.
PAGE 51
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H50. Deadlock May Occur Due To Illegal-Instruction/Page-Miss Combination Problem: Intel's 32-bit Instruction Set Architecture (ISA) utilizes most of the available op-code space; however some byte combinations remain undefined and are considered illegal instructions. Intel processors detect the attempted execution of illegal instructions and signal an exception.
PAGE 52
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H52. Floating-Point Exception Condition May Be Deferred Problem: A floating-point instruction that causes a pending floating-point exception (ES=1) is normally signaled by the processor on the next waiting FP/MMX™ technology instruction. In the following set of circumstances, the exception may be delayed or the FSW register may contain a wrong value: 1.
PAGE 53
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H53.
PAGE 54
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H55. Selector for The LTR/LLDT Register May Get Corrupted Problem: The internal selector portion of the respective register (TR, LDTR) may get corrupted if, during a small window of LTR or LLDT system instruction execution, the following sequence of events occur: 1. Speculative write to a segment register that might follow the LTR or LLDT instruction 2.
PAGE 55
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H58. Memory Aliasing with Inconsistent A and D Bits May Cause Processor Deadlock Problem: In the event that software implements memory aliasing by having two Page Directory Entries(PDEs) point to a common Page Table Entry (PTE) and the Accessed and Dirty bits for the two PDEs are allowed to become inconsistent the processor may become deadlocked.
PAGE 56
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H61. Machine Check Exception may Occur When Interleaving Code Between Different Memory Types Problem: A small window of opportunity exists where code fetches interleaved between different memory types may cause a machine check exception. A complex set of micro-architectural boundary conditions is required to expose this window.
PAGE 57
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H64. Processor Incorrectly Samples NMI Interrupt after RESET# Deassertion When Processor APIC is Hardware-Disabled Problem: When the processor APIC is hardware-disabled the processor may incorrectly interpret the NMI signal as an NMI interrupt, instead of a frequency strap value, starting six bus clocks after RESET# is deasserted.
PAGE 58
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H66. Under some complex conditions, the instructions in the Shadow of a JMP FAR may be Unintentionally Executed and Retired Problem - If all of the following events happen in sequence it is possible for the system or application to hang or to execute with incorrect data. 1.
PAGE 59
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H67. Processor Does not Flag #GP on Non-zero Write to Certain MSRs Problem - When a non-zero write occurs to the upper 32 bits of SYSENTER_EIP_MSR or SYSENTER_ESP_MSR, the processor should indicate a general protection fault by flagging #GP. Due to this erratum, the processor does not flag #GP.
PAGE 60
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE DOCUMENTATION CHANGES The Documentation Changes listed in this section applies to the following documents: • P6 Family of Processors Hardware Developer’s Manual • Intel® Mobile Celeron® Processor in Micro-PGA and BGA Package at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz and 266 MHz datasheet • Intel® Celeron® Processor Mobile Module: Mobile Module Connector 1 (MMC-1) at 400
PAGE 61
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Table 2.4. Mobile Celeron Processor CPUID EAX[31:0] Reserved[ 31:14] Type [13:12] Family [11:8] X 0 6 Model [7:4] 6 Stepping [3:0] A-C After the L2 cache is initialized, the CPUID cache/TLB descriptors will be the values shown in Table 2.5. Table 2.5.
PAGE 62
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE SPECIFICATION CLARIFICATIONS The Specification Clarifications listed in this section apply to the following documents: • P6 Family of Processors Hardware Developer’s Manual • Intel® Mobile Celeron® Processor in Micro-PGA and BGA Package at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz and 266 MHz datasheet • Intel® Celeron® Processor Mobile Module: Mobile Module Connector 1 (MM
PAGE 63
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE H3.
PAGE 64
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE SPECIFICATION CHANGES The Specification Changes listed in this section apply to the following documents: • P6 Family of Processors Hardware Developer’s Manual • Intel® Mobile Celeron® Processor in Micro-PGA and BGA Package at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz and 266 MHz datasheet • Intel® Celeron® Processor Mobile Module: Mobile Module Connector 1 (MMC-1) at 400 MH
PAGE 65
MOBILE INTEL® CELERON® PROCESSOR at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE Table 3.6. Mobile Celeron® Processor Power Specifications1 TCASE = 0 to TCASE,max; VCC = 1.6 V ±135 mV; VCCP = 1.8 V ±90 mV Symbol dICC/dt Parameter VCC power supply current slew rate Min Typ Max Unit 20 A/µs Notes 6, 7 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.