Intel® Celeron® Processor 200 Sequence Specification Update — For the Intel® Celeron® processor 220 January 2008 Notice: The Celeron processor 200 sequence may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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Contents Revision History ...................................................................................................................4 Preface ...............................................................................................................................5 Summary Tables of Changes ..................................................................................................7 General Information.......................................................................................
Revision History Revision History Revision Number Description Date -001 • Initial Release October 2007 -002 • Added Erratum AT93 January 2008 § 4 Specification Update
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number QDF Number is a several digit code that is used to distinguish between engineering samples. These processors are used for qualification and early design validation.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed stepping. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Item Numbering Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that is used in Intel’s microprocessor specification updates: A= C= D= E= AE = AF = AG = Dual-Core Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes AJ = AK = AL = AM = AN = AO = AP = AQ = AR = AS = AT = AV = AAA = AAB = AAC = Intel® Celeron® processor 200 series Intel® Core™2 Extreme processor QX9000 series and Intel® Core™2 Quad processor Q9000 sequence Quad-Core Intel® Xeon® Processor 5400 Series Dual-Core Intel® Xeon® Processor 5200 Series Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Process Quad-Core Intel® Xeon® processor 3300 series Dual-Core Intel® Xeon® E3110 Processor Intel® Celeron® dua
Summary Tables of Changes NO AT12 AT13 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AT33 AT34 10 A1 Plan ERRATA X No Fix Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May be Incorrect X No Fix LER MSRs May be Incorrectly Updated X No Fix Performance Monitoring Events for Retired Instructions (C0H) May Not be Accurate X No Fix Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH)
Summary Tables of Changes NO AT35 AT36 AT37 AT38 AT39 AT40 AT41 AT42 AT43 AT44 AT45 AT46 AT47 AT48 AT49 AT50 AT51 AT52 AT53 AT54 AT55 AT56 AT57 AT58 A1 Plan ERRATA X Plan Fix PREFETCHh Instruction Execution under Some Conditions May Lead to Processor Livelock X Plan Fix PREFETCHh Instructions May Not be Executed when Alignment Check (AC) is Enabled X Plan Fix Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE Memory Image May Be Unexpectedly All 1's after FXSAVE X Plan Fix Perfor
Summary Tables of Changes NO AT59 AT60 AT61 AT62 AT63 AT64 AT65 AT66 AT67 AT68 AT69 AT70 AT71 AT72 AT73 AT74 AT75 AT76 AT77 AT78 AT79 AT80 AT81 AT82 12 A1 Plan ERRATA X No Fix PMI May Be Delayed to Next PEBS Event X Plan Fix PEBS Buffer Overflow Status Will Not be Indicated Unless IA32_DEBUGCTL[12] is Set X No Fix Asynchronous MCE During a Far Transfer May Corrupt ESP X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint X No Fix BTM/BTS Branch-From Instruction
Summary Tables of Changes NO AT83 AT84 AT85 AT86 A1 Plan ERRATA X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI X No Fix Store Ordering May be Incorrect between WC and WP Memory X Plan Fix Fixed Function Performance Counters MSR_PERF_FIXED_CTR1 (30AH) and MSR_PERF_FIXED_CTR2 (30BH) are Not Cleared When the Processor is Reset X No Fix Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #PF X Plan Fix X No Fi
General Information General Information Figure 1. Intel® Celeron® Processor 200 Sequence Package Top-Side Marking Information GRIP1LINE1 GRIP1LINE2 GRIP1LINE1: GRIP1LINE2: GRIP2LINE1: GRIP2LINE2: LE80557 220 {FPO} SLAF2 1.
Identification Information Identification Information Component Identification The Celeron processor 200 sequence can be identified by the following values: Family1 Model2 00000110b 00010110b NOTES: 1.
Errata Errata AT1. Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set.
Errata AT4. Problem: Implication: VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR The LER MSR may be unexpectedly updated, if the resultant value of the Zero Flag (ZF) is zero after executing the following instructions 1. VERR (ZF=0 indicates unsuccessful segment read verification) 2. VERW (ZF=0 indicates unsuccessful segment write verification) 3. LAR (ZF=0 indicates unsuccessful access rights load) 4.
Errata AT7. General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted Problem: When the processor encounters an instruction that is greater than 15 bytes in length, a #GP is signaled when the instruction is decoded. Under some circumstances, the #GP fault may be preempted by another lower priority fault (e.g. Page Fault (#PF)). However, if the preempting lower priority faults are resolved by the operating system and the instruction retried, a #GP fault will occur.
Errata AT10. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memorybased APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g.
Errata AT13.
Errata AT15. Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH) Does Not Count According To The Specification Problem: The CPU_CLK_UNHALTED performance monitor with mask 1 counts bus clock cycles instead of counting the core clock cycles at the maximum possible ratio. The maximum possible ratio is computed by dividing the maximum possible core frequency by the bus frequency.
Errata AT18. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is not exactly representable in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally set by the processor. Under certain rare conditions, this bit may not be set when this rounding occurs.
Errata AT20. Sequential Code Fetch to Non-canonical Address May have Nondeterministic Results Problem: If code sequentially executes off the end of the positive canonical address space (falling through from address 00007fffffffffff to non- canonical address 0000800000000000), under some circumstances the code fetch will be converted to a canonical fetch at address ffff800000000000. Implication: Due to this erratum, the processor may transfer control to an unintended address.
Errata AT22. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur, it is possible that the load portion of the instruction will have executed before the exception handler is entered. • If an instruction that performs a memory load causes a code segment limit violation. • If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX) instruction that performs a memory load has a floating-point exception pending.
Errata AT24. EIP May be Incorrect after Shutdown in IA-32e Mode Problem: When the processor is going into shutdown state the upper 32 bits of the instruction pointer may be incorrect. This may be observed if the processor is taken out of shutdown state by NMI#. Implication: A processor that has been taken out of the shutdown state may have an incorrect EIP. The only software which would be affected is diagnostic software that relies on a valid EIP. Workaround: None identified.
Errata AT27.
Errata AT29. Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results Problem: The act of one processor, or system bus master, writing data into a currently executing code segment of a second processor with the intent of having the second processor execute that data as code is called cross-modifying code (XMC). XMC that does not force the second processor to execute a synchronizing instruction, prior to execution of the new code, is called unsynchronized XMC.
Errata AT31. Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit while the processor is operating in 16-bit mode or if a memory address exceeds the 4GB limit while the processor is operating in 32-bit mode.
Errata AT34. FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to a Misaligned Base Address (Alignment <= 0x10h) May Cause FPU Instruction or Operand Pointer Corruption Problem: If a FXSAVE/FXRSTOR instruction stores to the end of the segment causing a wrap to a misaligned base address (alignment <= 0x10h), and one of the following conditions is satisfied: 1. 32-bit addressing, obtained by using address-size override, when in 64-bit mode. 2.
Errata AT37. Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE Memory Image May Be Unexpectedly All 1's after FXSAVE Problem: The upper 32 bits of the FPU Data (Operand) Pointer may incorrectly be set to all 1's instead of the expected value of all 0's in the FXSAVE memory image if all of the following conditions are true: Implication: • The processor is in 64-bit mode. • The last floating point operation was in compatibility mode • Bit 31 of the FPU Data (Operand) Pointer is set.
Errata AT40. SYSCALL Immediately after Changing EFLAGS.TF May Not Behave According to the New EFLAGS.TF Problem: If a SYSCALL instruction follows immediately after EFLAGS.TF was updated and IA32_FMASK.TF (bit 8) is cleared, then under certain circumstances SYSCALL may behave according to the previous EFLAGS.TF. Implication: When the problem occurs, SYSCALL may generate an unexpected debug exception, or may skip an expected debug exception. Workaround: Mask EFLAGS.TF by setting IA32_FMASK.TF (bit 8).
Errata AT43. Code Breakpoint May Be Taken after POP SS Instruction if it is followed by an Instruction that Faults Problem: A POP SS instruction should inhibit all interrupts including Code Breakpoints until after execution of the following instruction. This allows sequential execution of POP SS and MOV eSP, eBP instructions without having an invalid stack during interrupt handling.
Errata AT46. INIT Does Not Clear Global Entries in the TLB Problem: INIT may not flush a TLB entry when: Implication: • The processor is in protected mode with paging enabled and the page global enable flag is set (PGE bit of CR4 register). • G bit for the page table entry is set. • TLB entry is present in TLB when INIT occurs. Software may encounter unexpected page fault or incorrect address translation due to a TLB entry erroneously left in TLB after INIT.
Errata AT49. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early Problem: In 64-bit Mode CMPSB, LODSB, or SCASB executed with a repeat prefix and count greater than or equal to 248 may terminate early. Early termination may result in one of the following.
Errata AT51. MOV To/From Debug Registers Causes Debug Exception Problem: When in V86 mode, if a MOV instruction is executed to/from a debug register, a general-protection exception (#GP) should be generated. However, in the case when the general detect enable flag (GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead. Implication: With debug-register protection enabled (i.e.
Errata AT54. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable System Behavior Problem: Returning back from SMM mode into real mode while EFLAGS.VM is set in SMRAM may result in unpredictable system behavior. Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in unpredictable system behavior. Intel has not observed this behavior in commercially available software. Workaround: SMM software should not change the value of EFLAGS.
Errata AT57. CPL-Qualified BTS May Report Incorrect Branch-From Instruction Address Problem: CPL (Current Privilege Level)-qualified BTS (Branch Trace Store) may report incorrect branch-from instruction address under the following conditions: • Either BTS_OFF_OS [9] or BTS_OFF_USR [10] is selected in IA32_DEBUGCTLC MSR (1D9H). • Implication: Privilege-level transitions occur between CPL > 0 and CPL 0 or vice versa.
Errata AT60. PEBS Buffer Overflow Status Will Not be Indicated Unless IA32_DEBUGCTL[12] is Set Problem: IA32_PERF_GLOBAL_STATUS MSR (38EH) bit [62] when set, indicates that a PEBS (Precise Event-Based Sampling) overflow has occurred and a PMI (Performance Monitor Interrupt) has been sent. Due to this erratum, this bit will not be set unless IA32_DEBUGCTL MSR (1D9H) bit [12] (which stops all Performance Monitor Counters upon a PMI) is also set.
Errata AT63. BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts Problem: When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a software interrupt may result in the overwriting of BTM/BTS branch-from instruction address by the LBR (Last Branch Record) branch-from instruction address. Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts. Workaround: None identified.
Errata AT66. Debug Register May Contain Incorrect Information on a MOVSS or POPSS Instruction Followed by SYSRET Problem: In IA-32e mode, if a MOVSS or POPSS instruction with a debug breakpoint is followed by the SYSRET instruction, incorrect information may exist in the Debug Status Register (DR6). Implication: When debugging or when developing debuggers, this behavior should be noted. This erratum will not occur under normal usage of the MOVSS or POPSS instructions (i.e.
Errata AT69. Performance Monitoring Events for L1 and L2 Miss May Not be Accurate Problem: Performance monitoring events 0CBh with an event mask value of 02h or 08h (MEM_LOAD_RETIRED.L1_LINE_MISS or MEM_LOAD_RETIRED.L2_LINE_MISS) may under count the cache miss events.
Errata AT72.
Errata AT75. Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some Decoded Instructions Problem: MACRO_INSTS.DECODED performance monitoring counter (Event 0AAH, Umask 01H) counts the number of macro instructions decoded, but not necessarily retired.
Errata AT77. Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Problem: Software which is written so that multiple agents can modify the same shared unaligned memory location at the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boundary.
Errata AT79. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum, if execution of the ENTER instruction results in a fault, the dynamic storage area of the resultant stack frame may contain unexpected values (i.e. residual stack data as a result of processing the fault). Implication: Data in the created stack frame may be altered following a fault on the ENTER instruction.
Errata AT81. Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault Problem: If code segment limit is set close to the end of a code page, then due to this erratum the memory page Access bit (A bit) may be set for the subsequent page prior to general protection fault on code segment limit. Implication: When this erratum occurs, a non-accessed page which is present in memory and follows a page that contains the code segment limit may be tagged as accessed.
Errata AT83. Storage of PEBS Record Delayed Following Execution of MOV SS or STI Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based Sampling), overflow of the counter results in storage of a PEBS record in the PEBS buffer. The information in the PEBS record represents the state of the next instruction to be executed following the counter overflow.
Errata AT86. Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #PF Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to both code #DB (Debug Exception) and code Segment Limit Violation #GP (General Protection Fault).
Errata AT88. Performance Monitoring Event MISALIGN_MEM_REF May Over Count Problem: Performance monitoring event MISALIGN_MEM_REF (05H) is used to count the number of memory accesses that cross an 8-byte boundary and are blocked until retirement. Due to this erratum, the performance monitoring event MISALIGN_MEM_REF also counts other memory accesses. Implication: The performance monitoring event MISALIGN_MEM_REF may over count.
Errata AT91. PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR Information Problem: When Precise Event-Based Sampling (PEBS) is configured with Performance Monitoring Interrupt (PMI) on PEBS buffer overflow enabled and Last Branch Record (LBR) Freeze on PMI enabled by setting FREEZE_LBRS_ON_PMI flag (bit 11) to 1 in IA32_DEBUGCTL (MSR 1D9H), the LBR stack is frozen upon the occurrence of a hardware PMI request. Due to this erratum, the LBR freeze may occur too soon (i.e.
Errata Workaround: It is possible for the BIOS to contain a workaround for this erratum. Please contact your Intel sales representative for availability. Status: For the steppings affected, see the Summary Tables of Changes.
Specification Changes Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Celeron® Processor 200 Sequence Datasheet • Intel® 64 and IA-32 Architectures Software Developer’s Manual volumes 1,2A, 2B, 3A, and 3B All Specification Changes will be incorporated into a future version of the appropriate Intel® Celeron® processor 200 sequence documentation. Δ Intel processor numbers are not a measure of performance.
Specification Clarifications Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel® Celeron® Processor 200 Sequence Datasheet • Intel® 64 and IA-32 Architectures Software Developer’s Manual volumes 1,2A, 2B, 3A, and 3B All Specification Clarifications will be incorporated into a future version of the appropriate Intel® Celeron® processor 200 sequence documentation. AT1.
Documentation Changes Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Celeron® Processor 200 Sequence Datasheet All Documentation Changes will be incorporated into a future version of the appropriate Intel® Celeron® processor 200 sequence documentation.
