Intel® Celeron® Processor 500Δ Series Datasheet For Platforms Based on Mobile Intel® 965 Express Chipset Family January 2008 Revision 003 Document Number: 317665-003
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Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 8 1.2 References ......................................................................................................... 9 2 Low Power Features ................................................................................................ 11 2.
Figures 1 2 3 4 5 6 7 Package-Level Low-Power States ................................................................................11 Core Low-Power States .............................................................................................12 Active VCC and ICC Loadline Standard Voltage .............................................................26 1-MB Fused Micro-FCPGA Processor Package Drawing (1 of 2) ........................................
Revision History Document Number Revision Number 317666 -001 Initial Release June 2007 317666 -002 Corrected Figures 4, 5, 6, & 7 November 2007 317665 -003 Added the Intel Celeron processor 560 January 2008 Description Date § Datasheet 5
Datasheet
Introduction 1 Introduction This document covers the Intel® Celeron® processor 500 series for platforms based on Mobile Intel® 965 Express Chipset family. It is based on the new Intel® Core™ microarchitecture. In this document the Celeron processor 500 series is referred to as the processor.
Introduction 1.1 Terminology Term 8 Definition # A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted.
Introduction 1.2 References Material and concepts in the following documents may be beneficial when reading this document.
Introduction 10 Datasheet
Low Power Features 2 Low Power Features 2.1 Clock Control and Low Power States The processor supports the C1/AutoHALT, C1/MWAIT, C2, and C3 core low-power states, along with their corresponding package-level states for power management. These package states include Normal, Stop Grant, Stop Grant Snoop, Sleep, and Deep Sleep. The processor’s central power management logic enters a package low-power state by initiating a P_LVLx (P_LVL2, P_LVL3) I/O read to the Intel 965 Express Chipset family.
Low Power Features Figure 2.
Low Power Features 2.1.1.3 C1/MWAIT Powerdown State C1/MWAIT is a low-power state entered when the processor core executes the MWAIT instruction. Processor behavior in the C1/MWAIT state is identical to the C1/AutoHALT state except that there is an additional event that can cause the processor core to return to the C0 state: the Monitor event. See the Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 2A/2B: Instruction Set Reference for more information. 2.1.1.
Low Power Features Specification T45). When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP# (AC Specification T75). While in the Stop-Grant state, the processor services snoops and latch interrupts delivered on the FSB. The processor latches SMI#, INIT# and LINT[1:0] interrupts and services only upon return to the Normal state. The PBE# signal may be driven when the processor is in Stop-Grant state.
Low Power Features 2.1.2.5 Deep Sleep State Deep Sleep state is a very low-power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings.
Low Power Features 16 Datasheet
Electrical Specifications 3 Electrical Specifications 3.1 Power and Ground Pins For clean, on-chip power distribution, the processor has many VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Please refer to the platform design guides for more details.
Electrical Specifications Table 2. 18 Voltage Identification Definition (Sheet 1 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 0 0 0 0 0 0 1.5000 0 0 0 0 0 0 1 1.4875 0 0 0 0 0 1 0 1.4750 0 0 0 0 0 1 1 1.4625 0 0 0 0 1 0 0 1.4500 0 0 0 0 1 0 1 1.4375 0 0 0 0 1 1 0 1.4250 0 0 0 0 1 1 1 1.4125 0 0 0 1 0 0 0 1.4000 0 0 0 1 0 0 1 1.3875 0 0 0 1 0 1 0 1.3750 0 0 0 1 0 1 1 1.3625 0 0 0 1 1 0 0 1.
Electrical Specifications Table 2. Datasheet Voltage Identification Definition (Sheet 2 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 1 0 0 1 0 1 1.0375 0 1 0 0 1 1 0 1.0250 0 1 0 0 1 1 1 1.0125 0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.
Electrical Specifications Table 2. 20 Voltage Identification Definition (Sheet 3 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.4625 1 0 1 0 1 0 0 0.4500 1 0 1 0 1 0 1 0.4375 1 0 1 0 1 1 0 0.4250 1 0 1 0 1 1 1 0.
Electrical Specifications Table 2. 3.4 Voltage Identification Definition (Sheet 4 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 1 1 0 0 0 1 0.0875 1 1 1 0 0 1 0 0.0750 1 1 1 0 0 1 1 0.0625 1 1 1 0 1 0 0 0.0500 1 1 1 0 1 0 1 0.0375 1 1 1 0 1 1 0 0.0250 1 1 1 0 1 1 1 0.0125 1 1 1 1 0 0 0 0.0000 1 1 1 1 0 0 1 0.0000 1 1 1 1 0 1 0 0.0000 1 1 1 1 0 1 1 0.0000 1 1 1 1 1 0 0 0.
Electrical Specifications For testing purposes, route the TEST3 and TEST5 signals through a ground referenced Z0 = 55-Ω trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection. 3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the chipset system on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3.
Electrical Specifications Table 4.
Electrical Specifications Table 5. Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit -40 85 °C TSTORAGE Processor storage temperature VCC Any processor supply voltage with respect to VSS -0.3 1.55 V VinAGTL+ AGTL+ buffer DC input voltage with respect to VSS -0.1 1.55 V VinAsynch_CMOS CMOS buffer DC input voltage with respect to VSS -0.1 1.55 V Notes1 2, 3, 4 NOTES: 1.
Electrical Specifications Table 6. DC Voltage and Current Specifications Symbol Parameter Min Typ Max ICC for processors Processor Number ICC IAH, ISGNT Frequency 530 1.73 GHz 540 1.86 GHz 550 2.00 GHz 560 2.13 GHz Unit Notes A Die Variant 1-M Fused 34.5 1M 32.0 1-M Fused 34.5 1M 32.0 1-M Fused 34.5 1M 32.0 1-M Fused 34.5 1M 32.0 ICC Auto-Halt & Stop-Grant A 3, 4 21 A 3, 4 ISLP ICC Sleep 20.5 A 3, 4 IDSLP ICC Deep Sleep 18.
Electrical Specifications Figure 3. Active VCC and ICC Loadline Standard Voltage Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. V CC [V] V CC max V CC, DC max 10 mV= RIPPLE V CC nom V CC, DC min V CC min +/-V CC nom * 1.5% = VR St. Pt. Error 1/ ICC [A] 0 ICC max N ote 1/ V CC Set Point Error Tolerance is per below : Tolerance --------------+/-1.5% +/-11.5 mV Table 7.
Electrical Specifications Table 8. Symbol VCCP GTLREF RCOMP AGTL+ Signal Group DC Specifications Parameter I/O Voltage Min Typ Max Unit 1.00 1.05 1.10 V Reference Voltage Compensation Resistor 2/3 VCCP 27.23 27.5 6 Ω 10 Ω 11 Input High Voltage GTLREF+0.10 VCCP VCCP+0.10 V 2, 6 VIL Input Low Voltage -0.10 0 GTLREF-0.10 V 3, 4 VOH Output High Voltage VCCP-0.10 VCCP VCCP Termination Resistance 50 55 61 Ω 7 Buffer On Resistance 22 25 28 Ω 5 ±100 µA 8 2.
Electrical Specifications Table 9. CMOS Signal Group DC Specifications Symbol Parameter VCCP I/O Voltage Notes1 Min Typ Max Unit 1.00 1.05 1.10 V 0.7*VCCP VCCP VCCP+0.1 V 2 -0.10 0.00 0.3*VCCP V 2, 3 VIH Input High Voltage VIL Input Low Voltage CMOS VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2 VOL Output Low Voltage -0.10 0 0.1*VCCP V 2 IOH Output High Current 1.5 4.1 mA 5 IOL Output Low Current 1.5 4.
Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information 4.1 Package Mechanical Specifications The processor has two variants, both available in a 478-pin Micro-FCPGA package. Package mechanical dimensions are shown in Figure 4 for the 1-MB fused variant and Figure 6 for the 1-MB variant.
Package Mechanical Specifications and Pin Information Figure 4. 1-MB Fused Micro-FCPGA Processor Package Drawing (1 of 2) Bottom View Top View Front View Side View & ' %( ! "# $% $ ) P Detail A + , 1--1 .0.2 1/ * * , .
Package Mechanical Specifications and Pin Information Figure 5. 1-MB Fused Micro-FCPGA Processor Package Drawing (2 of 2) "# $ %& ' Side View ( ( $ %& ' Top View ø0.305±0.25 ø0.406 M C A B ø0.
Package Mechanical Specifications and Pin Information Figure 6. 1-MB Micro-FCPGA Processor Package Drawing (1 of 2) 0 1 0 1 6 Top View 6 Bottom View Front View ( )* # $ "% !" ! Side View & oP Detail A .**. +-+/ ., ' ' ' ' 0 . 0 . 1 . 1 . 6 . 6 . &.
Package Mechanical Specifications and Pin Information Figure 7. 1-MB Micro-FCPGA Processor Package Drawing (2 of 2) "# $ %& ' Top View ø0.305±0.25 ø0.406 M C A B ø0.
Package Mechanical Specifications and Pin Information 4.2 Processor Pinout and Pin List Table 11 shows the top view pinout of the processor. Table 11.
Package Mechanical Specifications and Pin Information Table 12.
Package Mechanical Specifications and Pin Information This page is intentionally left blank.
Package Mechanical Specifications and Pin Information Table 13. Pin Name Pin Listing by Pin Name (Sheet 1 of 15) Pin Number Signal Buffer Type Direction Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Name Pin Listing by Pin Name (Sheet 3 of 15) Pin Number Signal Buffer Type Direction Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Name Pin Listing by Pin Name (Sheet 5 of 15) Pin Number Signal Buffer Type Direction Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Name Pin Listing by Pin Name (Sheet 7 of 15) Pin Number Signal Buffer Type Direction Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Name Pin Listing by Pin Name (Sheet 9 of 15) Pin Number Signal Buffer Type Direction Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Name Pin Listing by Pin Name (Sheet 11 of 15) Pin Number Signal Buffer Type Direction Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Name Pin Listing by Pin Name (Sheet 13 of 15) Pin Number Signal Buffer Type Direction Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin Name Pin Listing by Pin Name (Sheet 15 of 15) Pin Number Signal Buffer Type Direction Table 14.
Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number (Sheet 3 of 17) Pin Number Signal Buffer Type Direction TDO AB3 Open Drain Output VSS AB4 Power/Other TMS AB5 CMOS Input TRST# AB6 CMOS Input VCC AB7 Pin Name Table 14.
Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number (Sheet 5 of 17) Pin Number Signal Buffer Type VCC AD14 Power/Other VCC AD15 Power/Other VSS AD16 Power/Other VCC AD17 Power/Other VCC AD18 Power/Other VSS AD19 Power/Other D[54]# AD20 Source Synch Input/ Output D[59]# AD21 Source Synch Input/ Output Pin Name VSS AD22 Direction Power/Other Table 14.
Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number (Sheet 7 of 17) Pin Number Signal Buffer Type RSVD B2 Reserved INIT# B3 CMOS LINT1 B4 CMOS DPSLP# B5 CMOS VSS B6 Pin Name Table 14.
Package Mechanical Specifications and Pin Information Table 14.
Package Mechanical Specifications and Pin Information Table 14.
Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number (Sheet 13 of 17) Pin Number Signal Buffer Type Direction D[20]# L23 Source Synch Input/ Output VSS L24 Power/Other D[29]# L25 Source Synch Input/ Output DSTBN[1]# L26 Source Synch ADSTB[0]# M1 Source Synch VSS M2 Power/Other Pin Name Table 14.
Package Mechanical Specifications and Pin Information Table 14.
Package Mechanical Specifications and Pin Information Table 14.
Package Mechanical Specifications and Pin Information 4.3 Table 15. Alphabetical Signals Reference Signal Description (Sheet 1 of 8) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel® Celeron® FSB.
Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 2 of 8) Name BPM[2:1]# BPM[3,0]# Type Output Input/ Output Description BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Celeron FSB agents.
Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 3 of 8) Name Type Description DBR# Output DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.
Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 4 of 8) Name Type Description Data strobe used to latch in D[63:0]#. DSTBN[3:0]# Input/ Output Signals Associated Strobe D[15:0]#, DINV[0]# DSTBN[0]# D[31:16]#, DINV[1]# DSTBN[1]# D[47:32]#, DINV[2]# DSTBN[2]# D[63:48]#, DINV[3]# DSTBN[3]# Data strobe used to latch in D[63:0]#.
Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 5 of 8) Name IERR# Type Output Description IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor keeps IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 6 of 8) Name PRDY# PREQ# Type Output Input Description Probe Ready signal used by debug tools to determine processor debug readiness. Please refer to the appropriate platform design guide for more implementation details. Probe Request signal used by debug tools to request debug operation of the processor. Please refer to the appropriate platform design guide for more implementation details.
Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 7 of 8) Name SLP# SMI# Type Description Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state do not recognize snoops or interrupts.
Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 8 of 8) Name Type Description TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents. TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. VCC Input Processor core power supply.
Thermal Specifications 5 Thermal Specifications A complete thermal solution includes both component and system level thermal management features. The processor requires a thermal solution to maintain temperatures within operating limits. Caution: Any attempt to operate the processor outside operating limits may result in permanent damage to the processor and potentially other components in the system.
Thermal Specifications The processor incorporates three methods of monitoring die temperature: • Thermal diode • Intel® Thermal Monitor • Digital thermal sensor Note: The Intel Thermal Monitor (detailed in Section 5.2) must be used to determine when the maximum specified processor junction temperature has been reached. 5.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal “diode”, with its collector shorted to Ground.
Thermal Specifications If the ntrim value used to calculate the Toffset differs from the ntrim value used to in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset can be adjusted by calculating nactual and then recalculating the offset using the ntrim as defined in the temperature sensor manufacturer’s datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 17. Table 17. Table 18. Table 19.
Thermal Specifications Table 20. Thermal Diode Parameters using Transistor Model Symbol Parameter IFW Forward Bias Current IE Emitter Current nQ Transistor Ideality Beta RT Min Typ 5 5 0.997 1.001 0.3 Series Resistance 2.79 4.52 Max Unit Notes 200 µA 1, 2 200 µA 1 1.005 3, 4, 5 0.760 3, 4 6.24 Ω 3, 6 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 19. 3.
Thermal Specifications Caution: An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously.
Thermal Specifications asserted until the processor exits the low-power state and the processor junction temperature drops below the thermal trip point. If Intel Thermal Monitor automatic mode is disabled, the processor operates out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor automatically shuts down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal goes active.
Thermal Specifications 5.5 PROCHOT# Signal Pin An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Intel Thermal Monitor 1 is enabled (note that the Intel Thermal Monitor 1 must be enabled for the processor to be operating within specification), the TCC is active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
