Intel® Celeron® D Processor 300 Δ Sequence on 90 nm Process Specification Update September 2008 Rev 024 ® ® Notice: The Intel Celeron D Processor on 90 nm Process and in the 478-Pin Package ® ® and the Intel Celeron D Processor on 90 nm Process and in the 775 Land Package may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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Contents Preface............................................................................................................................. 6 Summary Tables of Changes................................................................................................ 8 Identification Information .................................................................................................. 17 Errata ............................................................................................................
Revision History Version 4 Description Date -001 • Initial Release -002 • Added Errata L31-L35 August 2004 -003 • Added Errata L36-50 September 2004 -004 • Added E step information. Added Erratum L49-L52. Minor updates to Summary of Errata Tables. Updated Processor Identification Table. September 2004 -005 • Added Erratum L53-L57. -006 • Added Erratum L58. Updated Processor Identification Table. November 2004 -007 • Added Specification Clarification L1. Updated Errata L29 & L33.
Version Description Date -022 • Updated summary table of changes.
Preface Preface This document is an update to the specifications contained in the documents listed the following Affected Documents/Related Documents table. It is a compilation device and document errata and specification clarifications and changes, and intended for hardware system manufacturers and for software developers applications, operating system, and tools.
Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number Errata are design defects or errors.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Note: Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates: A= Dual-Core Intel® Xeon® processor 7000 sequence C= Intel® Celeron® processor D= Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes AD = Intel(R) Celeron(R) D processor on 65nm process AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process AF = Dual-Core Intel® Xeon® processor LV AG = Dual-Core Intel® Xeon® processor 5100 series AH = Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor technology AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 sequence AJ = Quad-Core Intel® Xeon® processor 5300 series AK =
Summary Tables of Changes NO.
Summary Tables of Changes 12 NO. B1 C0 D0 E0 LE01 G1 LG11 Plans Errata L18 X X X X X X X No Fix The Processor May Issue Multiple Code Fetches to the Same Cacheline for Systems with Slow Memory L19 X X X X X X X No Fix Parity Error in the L1 Cache may cause the processor to hang L20 X X Fixed BPM4# Signal Not Being Asserted According to Specification L21 X X No Fix Front Side Bus Machine Checks May be Reported as a Result of On-Going Transactions during Warm Reset.
Summary Tables of Changes NO.
Summary Tables of Changes NO.
Summary Tables of Changes NO.
Summary Tables of Changes NO.
Identification Information Identification Information The Intel® Celeron® D Processor on 90 nm Process and in the 478-Pin Package and the Intel® Celeron® D Processor on 90 nm Process and in the 775 Land Package may be identified by the following values. Family1 Model2 1111b 0011b 1111b 0100b NOTES: 1.
Identification Information Table 1. Intel® Celeron® D Processor on 90 nm Process and in the 478-Pin Package and the Intel® Celeron® D Processor on 90 nm Process and in the 775 Land Package Identification Information Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Package And Revision Notes 325 2.53 533 256KB 02 478-pin micro-PGA with 35.0 x 35.0 mm FC-mPGA4 package 1 0F41h 320 2.40 533 256KB 01 775-land FC-LGA4 37.5 x 37.5 mm 1 E0 0F41h 325J 2.
Identification Information Table 1. Intel® Celeron® D Processor on 90 nm Process and in the 478-Pin Package and the Intel® Celeron® D Processor on 90 nm Process and in the 775 Land Package Identification Information Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Package And Revision Notes 345J 3.06 533 256KB 01 775-land FC-LGA4 37.5 x 37.5 mm 2 0F41h 345J 3.06 533 256KB 01 775-land FC-LGA4 37.5 x 37.5 mm 1 E0 0F41h 315 2.
Identification Information Table 1. Intel® Celeron® D Processor on 90 nm Process and in the 478-Pin Package and the Intel® Celeron® D Processor on 90 nm Process and in the 775 Land Package Identification Information Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Package And Revision Notes 335 2.80 533 256KB 02 775-land FC-LGA4 37.5 x 37.5 mm 1 0F41h 335 2.80 533 256KB 02 478-pin micro-PGA with 35.0 x 35.0 mm FC-mPGA4 package 1 D0 0F34h 340 2.
Identification Information Table 1. Intel® Celeron® D Processor on 90 nm Process and in the 478-Pin Package and the Intel® Celeron® D Processor on 90 nm Process and in the 775 Land Package Identification Information Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Package And Revision Notes 326 2.53 533 256KB 01 775-land FC-LGA4 37.5 x 37.5 mm 1, 3 0F49h 331 2.66 533 256KB 01 775-land FC-LGA4 37.5 x 37.5 mm 1, 3 G1 0F49h 336 2.
Identification Information Table 1. Intel® Celeron® D Processor on 90 nm Process and in the 478-Pin Package and the Intel® Celeron® D Processor on 90 nm Process and in the 775 Land Package Identification Information Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Package And Revision Notes 350 3.2 533 256KB 01 478-pin micro-PGA with 35.0 x 35.0 mm FC-mPGA4 package 1 0F49h 326 2.53 533 256KB 01 775-land FC-LGA4 37.5 x 37.5 mm 1, 3 G1 0F49h 331 2.
Identification Information Component Marking Information This section contains top marking information for the Intel® Celeron® D Processor on 90 nm Process and in the 478-Pin Package and the Intel® Celeron® D Processor on 90 nm Process and in the 775 Land Package Figure 1. Example of Sample Package Markings QDF / Countryof Assy FPO – Serial # Intel Confidential QYYY ES XXXXX i m c `03 ZZZZZZZZ FFFFFFFF-NNNN AAAAAAAA-NNNN 2-D MatrixMark ProductCode ATPO – Serial # Figure 2.
Identification Information Figure 3. Package Markings with Processor Number Processor i m © ‘04 Celeron® D 2A GHZ/512/400/1.50V 346 SL7NX XXXXX SYYYY XXXXXX 3.
Errata Errata L1. Transaction Is Not Retired after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, the transaction will not be retried. Implication: When this erratum occurs, locked transactions will not be retried. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. L2.
Errata L3. Processor May Hang Due to Speculative Page Walks to NonExistent System Memory Problem: A load operation issued speculatively by the processor that misses the Data Translation Lookaside Buffer (DTLB) results in a page walk. A branch instruction older than the load retires so that this load operation is now in the mispredicted branch path. Due to an internal boundary condition, in some instances the load is not canceled before the page walk is issued.
Errata L5. Machine Check Architecture Error Reporting and Recovery May Not Work As Expected Problem: When the processor detects errors it should attempt to report and/or recover from the error. In the situations described below, the processor does not report and/or recover from the error(s) as intended. When a transaction is deferred during the snoop phase and subsequently receives a Hard Failure response, the transaction should be removed from the bus queue so that the processor may proceed.
Errata The overflow bit should be set to indicate when more than one error has occurred. The overflow bit being set indicates that more than one error has occurred. Because of this erratum, if any further errors occur, the MCA overflow bit will not be updated, thereby incorrectly indicating only one error has been received.
Errata return data to the core, leaving the processor empty. IA32_MC0_STATUS MSR does indicate that a hard fail response occurred. The processor may hang when the following events occur and the machine check exception is enabled, CR4.MCE=1. A processor that has it’s STPCLK# pin asserted will internally enter the Stop Grant State and finally issue a Stop Grant Acknowledge special cycle to the bus.
Errata Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes L7. Cascading of Performance Counters Does Not Work Correctly When Forced Overflow Is Enabled Problem: The performance counters are organized into pairs. When the CASCADE bit of the Counter Configuration Control Register (CCCR) is set, a counter that overflows will continue to count in the other counter of the pair. The FORCE_OVF bit forces the counters to overflow on every non-zero increment.
Errata L10. Processor Flags #PF Instead of #AC on an Unlocked CMPXC8B Instruction Problem: If a data page fault (#PF) and alignment check fault (#AC) both occur for an unlocked CMPXC8B instruction, then #PF will be flagged Implication: Software that depends #AC before #PF will be affected since #PF is flagged in this case Workaround: Remove the software’s dependency on the fact that #AC has precedence over #PF.
Errata L13. When the Processor Is in the System Management Mode (SMM), Debug Registers May Be Fully Writeable Problem: When in System Management Mode (SMM), the processor executes code and stores data in the SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the processor should block writes to the reserved bit locations. Due to this erratum, the processor may not block these writes.
Errata L16. System May Hang if a Fatal Cache Error Causes Bus Write Line (BWL) Transaction to Occur to the Same Cache Line Address As an Outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL) Problem: A processor internal cache fatal data ECC error may cause the processor to issue a BWL transaction to the same cache line address as an outstanding BRL or BRIL.
Errata Problem: Systems with long latencies on returning code fetch data from memory e.g. BIOS ROM, may cause the processor to issue multiple fetches to the same cache line, once per each instruction executed Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a result of this erratum, in a commercially available system Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes L19.
Errata L22. A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May Cause an Incorrect Address to Be Reported to the #GP Exception Handler Problem: If a 16-bit application executes a branch instruction that causes an address wrap to a target address outside of the code segment, the address of the branch instruction should be provided to the general protection exception handler.
Errata L24.
Errata L26. Some Front Side Bus I/O Specifications Are Not Met. Problem: Problem: The following front side bus I/O specifications are not met: • The VIH(min) for the GTL+ signals is specified as GTLREF + (0.10 * VCC) [V]. • The VIH(min) for the Asynchronous GTL+ signals is specified as Vcc/2 + (0.10 * VCC) [V]. • Common Clock Output Valid Delay (min) is specified as -0.250 ns. • Common Clock Input Setup Time is specified as 0.700 ns.
Errata Function returns an incorrect physical address size value of 40 bits. The correct physical address size is 36 bits Implication: Function 80000008H returns an incorrect physical address size value of 40 bits Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes L28.
Errata continual sequence of UC fetch, implicit writeback, and Request for Ownership (RFO) retries Implication: This erratum has not been observed in any commercially available operating system or application. The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as being unsupported in the IA-32 Intel® Architecture Software Developer's Manual, Volume 3, section 10.12.4, Programming the PAT.
Errata Problem: The RF flag is normally used for code breakpoint management during debug of an application. It is not typically used during normal program execution. Code breakpoints or single step debug behavior in the presence of hardware task switches, therefore, may be unpredictable as a result of this erratum. This erratum has not been observed in commercially available software Implication: The RF flag is normally used for code breakpoint management during debug of an application.
Errata Status: For the steppings affected, see the Summary Tables of Changes L36. CPUID Instruction May Report Incorrect L2 Associativity in Leaf 0x80000006 Problem: L2 associativity reported by CPUID with EAX=80000006H instruction may be incorrect. Implication: Software may see an incorrect L2 associativity when viewed via CPUID with EAX=80000006H, however, when viewed via CPUID with EAX=4H the associativity value is correct. Workaround: None identified.
Errata L39. Machine Check Exceptions May Not Update Last-Exception Record MSRs (LERs) Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine Check Exceptions occur. Implication: When this erratum occurs, the LER may not contain information relating to the machine check exception. They will contain information relating to the exception prior to the machine check exception. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.
Errata Implication: If the guidelines in the Software Developer's Manual are not followed, stale data may be loaded into the processor's Translation Lookaside Buffer (TLB) and used for memory operations. This erratum has not been observed with any commercially available software. Workaround: The guidelines in the IA-32 Intel® Architecture Software Developer's Manual should be followed. Status: For the steppings affected, see the Summary Tables of Changes. L42.
Errata L45. Read for Ownership Processor to Hang and Simultaneous Fetch May Cause the Problem: The processor may hang when it attempts to fetch from cache line X and line X+1 simultaneously with a Read for Ownership to cache line X. If the fetch to cache line X+1 occurs within a small window of time, the processor will detect this as selfmodifying code and the Read for Ownership will be infinitely recycled. Implication: If this erratum occurs, the processor may hang.
Errata Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. L49. Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR Registers Problem: When an access is made to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an expected #GP fault may not happen. Implication: A read of the MSR_LASTBRANCH_0_FROM_LIP MSR register may not cause a #GP fault.
Errata Status: For the steppings affected, see the Summary Tables of Changes. L53. The Execute Disable Bit Fault May Be Reported before Other Types of Page Fault When Both Occur Problem: If the Execute Disable Bit is enabled and both the Execute Disable Bit fault and page faults occur, the Execute Disable Bit fault will be reported prior to other types of page fault being reported. Implication: No impact to properly written code since both types of faults will be generated but in the opposite order.
Errata Problem: When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of the IA32_MCi_STATUS register may be asserted even though the contents of the IA32_MCi_ADDR and IA32_MCi_MISC MSRs were not properly captured. Implication: If this erratum occurs, the MCA information captured in the IA32_MCi_ADDR and IA32_MCi_MISC may not correspond to the reported machine-check error, even though the ADDRV and MISCV are asserted. Workaround: None identified.
Errata • BTS/PEBS absolute maximum is less than a record size from the end of the virtual address space • The record that would cross BTS/PEBS absolute maximum will also continue past the end of the virtual address space A BTS/PEBS record can be written that will wrap at the 4G boundary (IA32) or 2^64 boundary (EM64T mode), and write memory outside of the BTS/PEBS buffer Implication: Software that uses BTS/PEBS near the 4G boundary (IA32) or 2^64 boundary (EM64T mode), and defines the buffer such that
Errata Or 2. Snoop filtering central agents can: a. Not use processor-originated BWIL or BLW transactions to update their snoop filter information, or b. Update the associated cache line state information to shared state on the originating bus (rather than invalid state) in reaction to a BWIL or BLW Status: For the steppings affected, see the Summary Tables of Changes. L61.
Errata Problem: A processor is expected to respond with an undefined opcode (#UD) fault when executing either opcode 0F 78 or a Grp 6 Opcode with bits 5:3 of the Mod/RM field set to 6, however the processor may respond instead, with a load to an incorrect address. Implication: This erratum may cause unpredictable system behavior or system hang. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. L64.
Errata Problem: For processors with Intel EM64T enabled, the upper 32 bits of the FS and GS data segment registers corresponding to a null base may not get cleared when segments are loaded in Virtual-8086 mode. Implication: This erratum may cause incorrect data to be loaded or stored to memory if FS/GS is not initialized before use in 64-bit mode. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
Errata L69. FXRSTOR May Not Restore Non-canonical Effective Addresses on Processors with Intel® Extended Memory 64 Technology (Intel® EM64T) Enabled Problem: If an x87 data instruction has been executed with a non-canonical effective address, FXSAVE may store that non-canonical FP Data Pointer (FDP) value into the save image. An FXRSTOR instruction executed with 64-bit operand size may signal a General Protection Fault (#GP) if the FDP or FP Instruction Pointer (FIP) is in noncanonical form.
Errata L72. An REP MOVS or an REP STOS Instruction with RCX >= 2^32 May Fail to Execute to Completion or May Write to Incorrect Memory Locations on Processors Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP MOVS or an REP STOS instruction executed with the register RCX >= 2^32, may fail to execute to completion or may write data to incorrect memory locations.
Errata L75. A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported Incorrectly in the Branch Trace Store (BTS) Memory Record or in the Precise Event Based Sampling (PEBS) Memory Record Problem: On a processor supporting Intel® EM64T, • If an instruction fetch wraps around the 4G boundary in Compatibility Mode, the 64-bit value of LIP in the BTS memory record will be incorrect (upper 32 bits will be set to FFFFFFFFh when they should be 0).
Errata Implication: In IA-32e mode, under the conditions given above, an IRET can get an AC# even if alignment checks are disabled at the start of the IRET. This erratum can only be observed with a software generated stack frame. Workaround: Software should not generate misaligned stack frames for use with IRET. Status: For the steppings affected, see the Summary Tables of Changes. L78.
Errata Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system. Workaround: Software should ensure at least one of the following is true when modifying shared data by multiple agents: • The shared data is aligned • Proper semaphores or barriers are used in order to prevent concurrent data accesses Status: For the steppings affected, see the Summary Tables of Changes. L80.
Errata conditions required to observe this erratum are a VM entry that returns from SMM with the “IA-32e guest” VM-entry control set to 1 in the SMM VMCS and the “host address-space size” VM-exit control cleared to 0 in the executive VMCS. Implication: A VM Exit will occur when a VMX Abort was expected. Workaround: An SMM VMM should always set the “IA-32e guest” VM-entry control in the SMM VMCS to be the value that was in the LMA bit (IA32_EFER.LMA.
Specification Changes Specification Changes There are no specification changes in this Specification Update revision.
Specification Clarifications Specification Clarifications The Specification clarifications listed in this section (If any) apply to the following documents: • Intel® Celeron® D Processors 340, 335, 330, 325, and 320 Datasheet - On 90 nm Process in the 478-pin Package Datasheet • Intel® Celeron® D Processor 3xx Sequence – On 90 nm Process in the 775-Land Package Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate Celeron D processor on 90 nm process and
Specification Clarifications VTTPWRGD, VTT or Vcc signal will de-assert THERMTRIP#, if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 us of the assertion of PWRGOOD (provided VTTPWRGD, VTT, and Vcc are asserted).
Documentation Changes Documentation Changes There are no documentation changes in this Specification Update revision.
