Intel® Celeron® D Processor 300Δ Sequence Datasheet – On 90 nm Process in the 775-Land Package December 2005 Document Number: 304092-006
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Contents 1 Introduction....................................................................................................................... 11 1.1 1.2 2 Electrical Specifications.................................................................................................... 15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3 Processor Land Assignments.............................................................................. 41 Alphabetical Signals Reference .........................
5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 6 Features ........................................................................................................................... 79 6.1 6.2 7 7.2 7.3 Mechanical Specifications ................................................................................... 84 7.1.1 Boxed Processor Cooling Solution Dimensions ..................................... 84 7.1.2 Boxed Processor Fan Heatsink Weight.................................................. 86 7.1.
Figures 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 4-2 5-1 5-2 5-3 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 Datasheet Phase Lock Loop (PLL) Filter Requirements ...................................................... 19 VCC Static and Transient Tolerance for 775_VR_CONFIG_04A .......................27 VCC Overshoot Example Waveform................................................................... 30 Processor Package Assembly Sketch.................................................................
Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 3-1 3-2 3-3 4-1 4-2 4-3 5-1 5-2 5-3 5-4 6-1 7-1 7-2 6 References.......................................................................................................... 13 Core Frequency to FSB Multiplier Configuration................................................. 16 Voltage Identification Definition........................................................................... 18 FSB Signal Groups ....................
Revision History Revision Number Description Date -001 • Initial release September 2004 -002 • Added 3.
Datasheet
Intel® Celeron® D Processor 300 Sequence Features Available at 3.33 GHz, 3.20 GHz, 3.06 GHz, 2.93 GHz, 2.80 GHz, 2.66 GHz, and 2.
Datasheet
Introduction 1 Introduction The Intel® Celeron® D processor 300 sequence on 90 nm process and in the 775-land package is a follow-on to the Intel® Celeron® D processor in the 478-pin package. This processor uses FlipChip Land Grid Array (FC-LGA4) package technology, and plugs into a 775-land LGA socket, referred to as the LGA775 socket. LGA775 is required to support higher frequency processors. This next generation of socket provides longevity for processor support beyond 2004.
Introduction 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1-1. References Document Document Numbers/ Location Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land LGA Package Thermal Design Guide http://developer.intel.com/ design/Pentium4/guides/ 302553.htm Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket http://developer.intel.com/ design/Pentium4/guides/ 302356.
Introduction 14 Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 FSB and GTLREF Most processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology. Platforms implement a termination voltage level for GTL+ signals defined as VTT. VTT must be provided via a separate voltage source and not be connected to VCC.
Electrical Specifications 2.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low power states, must be provided by the voltage regulator solution (VR). For more details, refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. 2.3.
Electrical Specifications 2.4 Voltage Identification The VID specification for the Celeron D processor in the 775-land package is supported by the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. The voltage set by the VID signals is the maximum voltage allowed by the processor. A minimum voltage is provided in Table 2-8 and changes with frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification.
Electrical Specifications Table 2-2. Voltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.
Electrical Specifications 2.4.1 Phase Lock Loop (PLL) Power and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators for the Celeron D processor in the 775-land package. Since these PLLs are analog, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VTT.
Electrical Specifications 2.5 Reserved, Unused, and TESTHI Signals All RESERVED signals must remain unconnected. Connection of these signals to VCC,VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED signals. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level.
Electrical Specifications With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.
Electrical Specifications Table 2-4.
Electrical Specifications 2.8 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Celeron D processor in the 775-land package be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage level.
Electrical Specifications At conditions exceeding absolute maximum and minimum ratings, neither functionality nor longterm reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.
Electrical Specifications Table 2-8. Voltage and Current Specifications Symbol VID range Parameter VID Processor Number Min Typ Max Unit Notes 1.250 — 1.400 V 1 V 2, 3, 4, 5, 6 A 7 A 8, 9, 13 Core Frequency VCC for 775_VR_CONFIG_04A processors VCC 325J/326 2.53 GHz 330J/331 2.66 GHz 335J/336 2.80 GHz 340J/341 2.93 GHz 345J/346 3.06 GHz 351 3.20 GHz 355 Processor Number Refer to Table 2-9 and Figure 2-2 3.
Electrical Specifications 2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.4 and Table 2-2 for more information. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm.
Electrical Specifications Figure 2-2. VCC Static and Transient Tolerance for 775_VR_CONFIG_04A Icc [A] 0 10 20 30 40 50 60 70 VID - 0.000 VID - 0.025 Vcc Maximum VID - 0.050 Vcc [V] VID - 0.075 VID - 0.100 Vcc Typical VID - 0.125 Vcc Minimum VID - 0.150 VID - 0.175 VID - 0.200 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.12. 2. This loadline specification shows the deviation from the VID set point. 3.
Electrical Specifications Table 2-10. GTL+ Asynchronous Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage 0.0 VTT/2 – (0.10 * VTT) — 2, 3 VIH Input High Voltage VTT/2 + (0.10 * VTT) VTT — 3, 4, 5, 6 VOH Output High Voltage 0.90*VTT VTT V 5, 6, 7 IOL Output Low Current — VTT/[(0.
Electrical Specifications . Table 2-12. PWRGOOD and TAP Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1, VHYS Input Hysteresis 200 350 mV 3 V T+ Input low to high threshold voltage 0.5 * (VTT + VHYS_MIN) 0.5 * (VTT + VHYS_MAX) V 4 V T- Input high to low threshold voltage 0.5 * (VTT – VHYS_MAX) 0.
Electrical Specifications 2.12 VCC Overshoot Specification The Celeron D processor in the 775-land package can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the maximum allowable time duration above VID).
Electrical Specifications 2.13 GTL+ FSB Specifications Termination resistors are not required for most GTL+ signals, as these are integrated into the processor silicon. Valid high and low levels are determined by the input buffers which compare a signal’s voltage with a reference voltage called GTLREF. Table 2-17 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. Table 2-17.
Electrical Specifications 32 Datasheet
Package Mechanical Specifications 3 Package Mechanical Specifications The Celeron D processor in the 775-land package is packaged in a Flip-Chip Land Grid Array (FC-LGA4) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications Figure 3-4.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.
Package Mechanical Specifications 3.5 Package Insertion Specifications The Celeron D processor in the 775-land package can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the Celeron D processor in the 775-land package is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications Figure 3-6. Processor Top-Side Marking Example Grp1line1: Grp1line2: Grp1line3: Grp1line4: Grp1line5: INTEL m © ‘03 CELERON® D 2.
Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 3-7 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 3-7.
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter contains the processor land assignments and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the Celeron D processor in the 775-land package. The landout footprint is shown in Figure 4-1 and Figure 4-2. These figures show the physical location of each signal on the package landout footprint (top view).
Land Listing and Signal Descriptions Figure 4-1.
Land Listing and Signal Descriptions Figure 4-2.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments 46 Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments 48 Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments 50 Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Datasheet Land # Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignments Datasheet Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignments 54 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignments Datasheet Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignments 56 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignments Datasheet Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignments 58 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignments Datasheet Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignments 60 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignments Datasheet Table 4-2.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 9) Name Type Description 36 A[35:3]# Input/ Output A[35:3]# (Address) define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 9) Name BCLK[1:0] Type Description Input The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 9) Name Type Description COMP[1:0] Analog COMP[1:0] must be terminated to VSS on the system board using precision resistors. COMP[3:2] Analog For future processor compatibility COMP[3:2] must be terminated to VTT on the system board using precision resistors. COMP[5:4] Analog For future processor compatibility, COMP[5:4] must be terminated to VTT on the system board using precision resistors.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 4 of 9) Name Type Description DEFER# Input DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins/lands of all processor FSB agents. DP[3:0]# Input/ Output DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 5 of 9) Name Type Description GTLREF_SEL Output GTLREF_SEL is used to select the appropriate chipset GTLREF voltage. HIT# Input/ Output HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 6 of 9) Name LOCK# Type Input/ Output Description LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 7 of 9) Name RESET# Type Description Input Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all FSB agents will de-assert their outputs within two clocks.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 8 of 9) Name THERMTRIP# Type Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 9 of 9) Name Type Description VSS Input VSS are the ground pins for the processor and should be connected to the system ground plane. VSSA Input VSSA is the isolated ground for internal PLLs. VSS_SENSE Output VSS_SENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The Celeron D processor in the 775-land package requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations Refer to the Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land LGA Package Thermal Design Guide and the Processor Power Characterization Methodology for the details of this methodology. The case temperature is defined at the geometric top center of the processor IHS. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained periods of time.
Thermal Specifications and Design Considerations Table 5-2. Thermal Profile for Processors Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) 0 44.2 30 52.6 60 61.0 2 44.8 32 53.2 62 61.6 4 45.3 34 53.7 64 62.1 6 45.9 36 54.3 66 62.7 8 46.4 38 54.8 68 63.2 10 47.0 40 55.4 70 63.8 12 47.6 42 56.0 72 64.4 14 48.1 44 56.5 74 64.9 16 48.7 46 57.1 76 65.5 18 49.2 48 57.6 78 66.0 20 49.8 50 58.2 80 66.6 22 50.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) are specified in Table 5-1. These temperature specifications are meant to help ensure proper operation of the processor. Figure 5-2 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land LGA Package Thermal Design Guide.
Thermal Specifications and Design Considerations expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.
Thermal Specifications and Design Considerations Figure 5-3. Thermal Monitor 2 Frequency and Voltage Ordering TT M2 Temperature fMAX fT M2 Frequency VID VIDT M2 VID PROCHOT# Time The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC can not be activated via the on demand mode.
Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#.
Thermal Specifications and Design Considerations 5.2.7 Thermal Diode The processor incorporates an on-die thermal diode. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. Table 5-3 and Table 5-4 provide the diode parameter and interface specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor.
Features 6 Features This chapter contains power-on configuration options and clock control/low power state descriptions. 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Celeron D processor in the 775-land package samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation.
Features Figure 6-1.
Features 6.2.3 Stop-Grant States When the STPCLK# signal is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state.
Features 82 Datasheet
Boxed Processor Specifications 7 Boxed Processor Specifications The Celeron D processor in the 775-land package will also be offered as an boxed Intel processor. Boxed Intel processors are intended for system integrators who build systems from baseboards and standard components. The boxed Celeron D processor in the 775-land package will be supplied with a cooling solution.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Celeron D processor in the 775- land package fan heatsink. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed Pentium 4 processor in the 775-land package. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 7-3. Space Requirements for the Boxed Processor (Top View) 95.0 [3.74] 95.0 [3.74] B d P T Vi NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 7-4.
Boxed Processor Specifications 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. Refer to Chapter 5 and the Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land LGA Package Thermal Design Guide for details on the processor weight and heatsink requirements. 7.1.
Boxed Processor Specifications Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description Pin 1 2 3 4 Signal GND +12 V SENSE CONTROL Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width. Match with straight pin, friction lock header on mainboard. 1 2 3 4 Table 7-1. Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit +12V: 12 volt fan power supply 10.2 12 13.
Boxed Processor Specifications 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator.
Boxed Processor Specifications Figure 7-7. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Top View) Figure 7-8.
Boxed Processor Specifications 7.3.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header, it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
Boxed Processor Specifications Table 7-2. Boxed Processor Fan Heatsink Set Points Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed X ≤ 30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. Y = 34 When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
Boxed Processor Specifications 92 Datasheet
Debug Tools Specifications 8 Debug Tools Specifications Refer to the ITP700 Debug Port Design Guide for information regarding debug tools specifications. The ITP700 Debug Port Design Guide is located on http://developer.intel.com. 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Celeron D processor in the 775-land package systems.
Debug Tools Specifications 94 Datasheet
