Intel® Celeron® D Processor 3xx∆ Sequence Datasheet – On 90 nm Process in the 478-pin Package June 2005 Document Number: 302353-005
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Contents 1 Introduction ................................................................................................................11 1.1 1.2 2 Electrical Specifications ........................................................................................15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3 Processor Pin Assignments ................................................................................39 Alphabetical Signals Reference ..........................................
5.2.3 5.2.4 5.2.5 5.2.6 6 Features ....................................................................................................................... 69 6.1 6.2 7 7.2 7.3 Mechanical Specifications................................................................................... 74 7.1.1 Boxed Processor Cooling Solution Dimensions ..................................... 74 7.1.2 Boxed Processor Fan Heatsink Weight.................................................. 75 7.1.
Figures 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 5-1 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 Datasheet Phase Lock Loop (PLL) Filter Requirements ......................................................18 VCC Static and Transient Tolerance....................................................................25 VCC Overshoot Example Waveform....................................................................29 Processor Package Assembly Sketch.................................................................
Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 3-1 3-2 3-3 4-1 4-2 4-3 5-1 5-2 5-3 6-1 7-1 7-2 6 References.......................................................................................................... 13 Core Frequency to FSB Multiplier Configuration................................................. 16 Voltage Identification Definition........................................................................... 17 FSB Pin Groups ......................
Revision History Revision Number Datasheet Description Date -001 • Initial release June 2004 -002 • Minor updates for clarity July 2004 -003 • Added 2.93 GHz processor September 2004 -004 • Added 3.06 GHz processor November 2004 -005 • Added 3.
Datasheet
Intel® Celeron® D Processor 3xx Sequence Features T T T T T T T Available at 3.20 GHz, 3.06 GHz, 2.93 GHz, 2.80 GHz, 2.66 GHz, 2.53 GHz, and 2.
Datasheet
Introduction 1 Introduction The Intel® Celeron® D processor on 90 nm process and in the 478-pin package uses Flip-Chip Pin Grid Array 4 (FC-mPGA4) package technology, and plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Celeron D processor on 90 nm process and in the 478-pin package is based on the same Intel 32-bit microarchitecture and maintains the tradition of compatibility with IA-32 software.
Introduction 1.1.1 Processor Packaging Terminology Commonly used terms are explained here for clarification: • Intel® Celeron® D processor on 90 nm process and in the 478-pin package — Celeron D processor in the FC-mPGA4 package with a 256-KB L2 cache. • Processor — For this document, the term processor is the generic form of the Celeron D processor. • Keep-out zone — The area on or near the processor that system design can not use.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document: Table 1-1. References Document Document Number/ Location Intel® 865G/865GV/865PE/865P Chipset Platform Design Guide http://developer.intel.com/ design/chipsets/designex/ 252518.htm Intel® Pentium® 4 Processor in 478-pin Package and Intel® 845G/845GL Chipset Platform Design Guide http://developer.intel.com/ design/chipsets/designex/ 298654.
Introduction 14 Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 FSB and GTLREF Most Celeron D processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology. The termination voltage level for the Celeron D processor GTL+ signals is VCC, which is the operating voltage of the processor core.
Electrical Specifications 2.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low power states, must be provided by the voltage regulator solution (VR). For more details on this topic, refer to the applicable VRD design guide. 2.3.
Electrical Specifications 2.4 Voltage Identification The VID specification for the Celeron D processor is supported by the applicable VRD design guide. The voltage set by the VID pins is the maximum voltage allowed by the processor. A minimum voltage is provided in Table 2-8 and changes with frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification.
Electrical Specifications 2.4.1 Phase Lock Loop (PLL) Power and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Celeron D processor silicon. Since these PLLs are analog, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC.
Electrical Specifications 2.5 Reserved, Unused, and TESTHI Pins All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a pin listing of the processor and the location of all RESERVED pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level.
Electrical Specifications 2.6 FSB Signal Groups The FSB signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers that use GTLREF as a reference level. In this document, the term "GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when driving.
Electrical Specifications Table 2-4.
Electrical Specifications 2.9 FSB Frequency Select Signals (BSEL[1:0]) The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 2-6 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.
Electrical Specifications 2.11 Processor DC Specifications The processor DC specifications in this section are defined at the processor core silicon and not at the package pins unless noted otherwise. See Chapter 4 for the pin signal definitions and signal pin assignments. Most of the signals on the processor FSB are in the GTL+ signal group. The DC specifications for these signals are listed in Table 2-10.
Electrical Specifications 3. 4. 5. 6. 7. 8. 9. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
Electrical Specifications Figure 2-2. VCC Static and Transient Tolerance Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 VID - 0.000 Vcc Maximum VID - 0.050 Vcc [V] VID - 0.100 VID - 0.150 VID - 0.200 Vcc Typical Vcc Minimum VID - 0.250 VID - 0.300 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.12. 2. This loadline specification shows the deviation from the VID set point. 3.
Electrical Specifications Table 2-10. GTL+ Signal Group DC Specifications Parameter Min Max Unit Notes1 VIL Input Low Voltage 0.0 GTLREF – (0.10 * VCC) V 2,3 VIH Input High Voltage GTLREF + (0.10 * VCC) VCC V 3,4,5 VOH Output High Voltage 0.90*VCC VCC V 3,5 IOL Output Low Current N/A VCC/ [0.50*RRTT_MIN+RON_MIN] A ILI Input Leakage Current N/A ± 200 µA 6 ILO Output Leakage Current N/A ± 200 µA 7 Ron_compatible Buffer On Resistance 6.33 10.
Electrical Specifications 11. These specifications are different depending on whether the platform is forward compatible to the Celeron D processor or if it is optimized for the Celeron D processor. A compatible platform is one that is designed for a previous generation processor but has some level of compatibility with the Celeron D processor.
Electrical Specifications Table 2-15. BSEL [1:0] and VID[5:0] DC Specifications Symbol Parameter Max Unit Notes1 Ron (BSEL) Buffer On Resistance 60 Ω 2 Ron (VID) Buffer On Resistance 60 Ω 2 IOL Max Pin Current 8 mA ILO Output Leakage Current 200 µA 3.3 + 5% V VTOL Voltage Tolerance 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3.
Electrical Specifications Figure 2-3. VCC Overshoot Example Waveform Example Overshoot Waveform Voltage (V) VID + 0.050 VOS VID TOS Time TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.12.1 Die Voltage Validation Overshoot events from application testing on real processors must meet the specifications in Table 2-17 when measured across the VCC_SENSE and VSS_SENSE pins.
Electrical Specifications 2.13 GTL+ FSB Specifications Termination resistors are not required for most GTL+ signals; they are integrated into the processor silicon. Valid high and low levels are determined by the input buffers that compare a signal’s voltage with a reference voltage called GTLREF. Table 2-18 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. Table 2-18.
Package Mechanical Specifications 3 Package Mechanical Specifications The Celeron D processor is packaged in a Flip-Chip Pin Grid Array (FC-mPGA4) package that interfaces with the motherboard via a mPGA478B socket. The package consists of a processor core mounted on a substrate pin-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions (such as a heatsink).
Package Mechanical Specifications Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.
Package Mechanical Specifications 3.4 Package Handling Guidelines Table 3-2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 3-2. Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N [80 lbf] 1,2 Tensile 156 N [35 lbf] 2,3 Torque 8 N-m [70 lbf-in] 2,4 NOTES: 1.
Package Mechanical Specifications 3.8 Processor Markings Figure 3-5 and Figure 3-5 show the topside markings on the processor. These diagrams are to aid in the identification of the Celeron D processor. Figure 3-4. Processor Top-Side Marking Example (with Processor Number) I m © ‘04 Celeron® D 345 SL7NX XXXXX 3.06GHz/256/533 FFFFFFFF-NNNN Processor Number 2D Matrix Figure 3-5. Processor Top-Side Marking Example Grp1line1: Grp1line2: Grp1line3: Grp1line4: Grp1line5: INTEL m © ‘03 CELERON® D 2.
Package Mechanical Specifications 3.9 Processor Pinout Coordinates Figure 3-6 shows the top view of the processor pin coordinates. The coordinates are referred to throughout the document to identify processor pins . Figure 3-6.
Package Mechanical Specifications 38 Datasheet
Pin Listing and Signal Descriptions 4 Pin Listing and Signal Descriptions This chapter provides the Celeron D processor pinout and signal description. 4.1 Processor Pin Assignments The pinout footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the pinout arranged by pin number. Table 4-1 provides the pinout arranged alphabetically by signal name and Table 4-2 provides the pinout arranged numerically by pin number.
Pin Listing and Signal Descriptions Figure 4-1.
Pin Listing and Signal Descriptions Figure 4-2.
Pin Listing and Signal Descriptions Table 4-1. Alphabetical Pin Assignment Pin Name 42 Pin # Signal Buffer Type Direction Table 4-1.
Pin Listing and Signal Descriptions Table 4-1.
Pin Listing and Signal Descriptions Table 4-1. Alphabetical Pin Assignment Pin Name 44 Pin # Signal Buffer Type Direction Table 4-1.
Pin Listing and Signal Descriptions Table 4-1. Alphabetical Pin Assignment Pin Name Datasheet Pin # Signal Buffer Type Direction Table 4-1.
Pin Listing and Signal Descriptions Table 4-1. Alphabetical Pin Assignment Pin Name 46 Pin # Signal Buffer Type Direction Table 4-1.
Pin Listing and Signal Descriptions Table 4-1. Alphabetical Pin Assignment Pin Name Datasheet Pin # Signal Buffer Type Direction Table 4-1.
Pin Listing and Signal Descriptions Table 4-2. Numerical Pin Assignment Pin # 48 Pin Name Signal Buffer Type A2 THERMTRIP# Asynch GTL+ A3 VSS Power/Other A4 VSS_SENSE Power/Other A5 VCC_SENSE Power/Other A6 TESTHI11 Power/Other A7 RESERVED A8 VCC A9 VSS A10 A11 Direction Output Table 4-2.
Pin Listing and Signal Descriptions Table 4-2. Numerical Pin Assignment Pin # Datasheet Pin Name Signal Buffer Type Direction Table 4-2.
Pin Listing and Signal Descriptions Table 4-2. Numerical Pin Assignment Pin # 50 Pin Name Signal Buffer Type Direction Table 4-2.
Pin Listing and Signal Descriptions Table 4-2. Numerical Pin Assignment Pin # Datasheet Pin Name Signal Buffer Type Direction Table 4-2.
Pin Listing and Signal Descriptions Table 4-2. Numerical Pin Assignment Pin # 52 Pin Name Signal Buffer Type Direction Table 4-2.
Pin Listing and Signal Descriptions Table 4-2.
Pin Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 8) Name A[35:3]# Type Description Input/ Output A[35:3]# (Address) define a 236-byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Celeron® D processor FSB.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 8) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 8) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 4 of 8) Name DRDY# Type Input/ Output Description DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins of all processor FSB agents. Data strobe used to latch in D[63:0]#.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 5 of 8) Name IGNNE# Type Input Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 6 of 8) Name Type Description This is an input to the processor to determine if the processor is in an optimized platform or a compatible platform. This input has a weak internal pull-up. OPTIMIZED/ COMPAT# PROCHOT# PWRGOOD Input Input/ Output Input A compatible platform is one that is designed for a previous generation processor but has some level of compatibility with the Celeron D processor.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 7 of 8) Name SLP# SMI# Type Description Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts.
Pin Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 8 of 8) Name Type Description VCC Input VCC are the power pins for the processor. The voltage supplied to these pins is determined by the VID[5:0] pins. VCCA Input VCCA provides isolated power for the internal processor core PLLs. Refer to the applicable chipset platform design guide for complete implementation details. VCCIOPLL Input VCCIOPLL provides isolated power for internal processor FSB PLLs.
Pin Listing and Signal Descriptions 62 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The Celeron D processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations power consumption. The Thermal Monitor feature is intended to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.2. In all cases, the Thermal Monitor feature must be enabled for the processor to remain within specification. Table 5-1.
Thermal Specifications and Design Considerations 5.2 Processor Thermal Features 5.2.1 Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the TCC when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption as needed by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications.
Thermal Specifications and Design Considerations increments. On-Demand mode may be used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. 5.2.3 PROCHOT# Signal Pin An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature.
Thermal Specifications and Design Considerations 5.2.5 TCONTROL and Fan Speed Reduction (Optional) TCONTROL and Fan Speed Reduction are not requirements for the Celeron D processor on 90 nm process and in the 478-pin package, but are provided as options for platforms that can use these features. TCONTROL is part of the temperature specification that defines temperature for system fan speed management. The BIOS reads the TCONTROL value once and configures the fan control chip appropriately.
Thermal Specifications and Design Considerations Table 5-3.
Features 6 Features This chapter contains power-on configuration options and clock control/low power state descriptions. 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Celeron D processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation.
Features 6.2.2 AutoHALT Powerdown State—State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Power Down state.
Features 6.2.3 Stop-Grant State—State 3 When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state.
Features 6.2.5 Sleep State—State 5 The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state.
Boxed Processor Specifications 7 Boxed Processor Specifications The Celeron D processor is also offered as a boxed Intel processor. Boxed Intel processors are intended for system integrators who build systems from baseboards and standard components. The boxed Celeron D processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed Celeron D processor.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Celeron D processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed Celeron D processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the Intel® Pentium 4 Processor on 90 nm Process Thermal Design Guidelines for details on the processor weight and heatsink requirements. Note: The processor retention mechanism based on the Intel reference design should be used, to ensure compatibility with the heatsink attach clip assembly and the boxed processor thermal solution.
Boxed Processor Specifications 7.2 Electrical Requirements 7.2.1 Fan Heatsink Power Supply The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 7-4. Baseboards must provide a matched power header to support the boxed processor. Table 7-1 contains specifications for the input and output signals at the fan heatsink connector.
Boxed Processor Specifications Figure 7-5. Baseboard Power Header Placement Relative to Processor Socket 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 7-6. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View) Figure 7-7.
Boxed Processor Specifications 7.3.2 Variable Speed Fan The boxed processor fan operates at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum.
Boxed Processor Specifications 80 Datasheet
Debug Tools Specifications 8 Debug Tools Specifications Refer to the ITP700 Debug Port Design Guide for information regarding debug tools specifications. The ITP700 Debug Port Design Guide is located on http://developer.intel.com. 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Celeron D processor systems.
Debug Tools Specifications 82 Datasheet
