Intel Celeron Processor for the PGA370 Socket up to 1.40 GHz on 0.13 Micron Process Datasheet

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Intel

Celeron

Processor for the PGA370

Socket up to 1.40 GHz on 0.13 Micron

Process

Datasheet

Product Features

The Intel

Celeron

processor is designed for uni-processor based Value PC desktops and is binary

compatible with previous generation Intel architecture processors. The Intel Celeron

processor provides

good performance for applications running on advanced operating systems such as Windows* 95/98,

WindowsNT*, Windows* 2000, WindowsXP* and UNIX*. This is achieved by integrating the best

attributes of Intel processors—the dynamic execution performance of the P6 microarchitecture plus the

capabilities of MMX™ technology—bringing a balanced level of performance to the Value PC market

segment. The Intel Celeron processor offers the dependability you would expect from Intel at an

exceptional value. Systems based on Intel Celeron processors also include the latest features to simplify

system management and lower the cost of ownership for small business and home environments.

■ Available at 1.4 GHz, 1.30 GHz, 1.20 GHz,

1.10A GHz, 1A GHz and 900 MHz with

100 MHz system bus

■ 256 KB on-die Level 2 (L2) cache with Error

Correcting Code (ECC))

■ Dual Independent Bus (DIB) architecture:

Separate dedicated external System Bus and

dedicated internal high-speed cache bus

■ Internet Streaming SIMD Extensions for

enhanced video, sound and 3D performance

■ Binary compatible with applications running

on previous members of the Intel

microprocessor line

■ Dynamic execution micro architecture

■ Power Management capabilities

—System Management mode

—Multiple low-power states

■ Optimized for 32-bit applications running on

advanced 32-bit operating systems

■ Flip Chip Pin Grid Array (FC-PGA2) packaging

technology

■ Integrated high performance 16 KB instruction

and 16 KB data, nonblocking, level one cache

■ Integrated Full Speed level two cache allows for

low latency on read/store operations

■ Error-correcting code for System Bus data

May 2002

Order Number: 298596-004

Summary of content (82 pages)

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Intel® Celeron® Processor for the PGA370 Socket up to 1.40 GHz on 0.13 Micron Process Datasheet Product Features ■ ■ ■ ■ ■ ■ Available at 1.4 GHz, 1.30 GHz, 1.20 GHz, 1.
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Contents 1.0 Introduction......................................................................................................................... 9 1.1 1.2 2.0 Electrical Specifications....................................................................................................13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3.0 Processor System Bus and VREF ........................................................
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 3.4 4.0 Thermal Specifications and Design Considerations......................................................... 51 4.1 4.2 5.0 6.2 6.3 Mechanical Specifications................................................................................... 68 6.1.1 Mechanical Specifications for the FC-PGA2 Package ........................... 68 6.1.2 Boxed Processor Heatsink Weight.........................................................
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Datasheet Integrated Heat Spreader (IHS) ............................................................................ 9 AGTL Bus Topology in a Uniprocessor Configuration.........................................14 Stop Clock State Machine ...................................................................................
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 6 Processor Identification....................................................................................... 11 System Bus Clock in Deep Sleep Mode (Differential Mode only) ....................... 16 Voltage Identification Definition ..............................................................
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Revision History Datasheet Revision Date -004 May 2002 Description • Added 1.4 GHz processor information; Added Section 3.4, “VTT_PWRGD Signal Quality Specification”; Updated Table 40, “Signal Description” for VCMOS_REF.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process This page is intentionally left blank.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 1.0 Introduction The Intel® Celeron® processor based on 0.13 micron process core for the PGA370 socket is the next member of the P6 family, in the Intel IA-32 processor line and hereafter will be referred to as simply “the processor”. The processor will continue in the package technology called flip-chip pin grid array but will contain a Integrated Heat Spreader (IHS) (see Figure 1).
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 1.1 Terminology In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a signal is in the active state (based on the name of the signal) when driven to a low level. For example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable interrupt has occurred.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 1.1.2 Table 1. Processor Naming Convention Processor Identification Processor Core Frequency System Bus Frequency (MHz) L2 Cache Size (Kbytes) L2 Cache Type2 CPUID1 1.4 1.40 100 256 ATC 06Bxh 1.30 1.30 GHz 100 256 ATC 06Bxh 1.203 1.20 GHz 100 256 ATC 06Bxh 1.20 1.20 GHz 100 256 ATC 06Bxh 1.10A 1.10A GHz 100 256 ATC 06Bxh 1A 1A GHz 100 256 ATC 06Bxh 900 900 MHz 100 256 ATC 06Bxh NOTES: 1.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 1.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 2.0 Electrical Specifications 2.1 Processor System Bus and VREF The processor uses the original low voltage signaling of the Gunning Transceiver Logic (GTL) technology for the system bus. The GTL system bus operates at 1.25V signal levels versus GTL+ which operates at 1.5 V signal levels. The GTL+ signal technology is used by the Intel® Pentium® Pro, Intel® Pentium® II and Intel® Pentium® III processors.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Figure 2. AGTL Bus Topology in a Uniprocessor Configuration Processor Chipset I/O I/O Note: RESET# requires external termination. 2.2 Clock Control and Low Power States Processors allow the use of Sleep, and Deep Sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 3 for a visual representation of the processor low power states.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 2.2.1 Normal State—State 1 This is the normal operating state for the processor. 2.2.2 AutoHALT Powerdown State—State 2 AutoHALT is a power state entered when the processor executes the HALT instruction. The processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# causes the processor to immediately initialize itself.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 2.2.5 Sleep State—State 5 The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from the Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT states.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 2.2.7 Clock Control BCLK provides the clock signal for the processor and on-die L2 cache. During AutoHALT Power Down and Stop-Grant states, the processor will process a system bus snoop. The processor does not stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Figure 4. PLL Filter Specification 0.2 dB 0 dB -0.5 dB Forbidden Zone Forbidden Zone -28 dB -40 dB DC 2.4 fpeak 1 MHz 66 MHz force Decoupling Guidelines Due to the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 2.5 Processor System Bus Clock and Processor Clocking The processor will implement an auto-detect mechanism that will allow the processor to use either single-ended or differential signaling for the system bus and processor clocking. The processor checks to see if the signal on pin Y33 is toggling. If this signal is toggling then the processor operates in differential mode. Refer to Figure 5 for an example on differential clocking.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process on the model 68xh based on 0.18 micron process core processor. By connecting the VID25mV signal to the Vss pin, it will disable the 25 mV stepping granularity output and the regulator will resort to 50 mV stepping increment. The voltage regulator or VRM must supply the voltage that is requested or disable itself. In addition to the new signal “VID25mV”, the processor will introduce a second new signal labeled as “VTT_PWRGD”.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process The VID pins should be pulled up to a 3.3 V level. This may be accomplished with pull-ups internal to the voltage regulator, which ensures valid VID pull-up voltage during Power-up and Power-down sequences. If external resistors are used for the VID[3:0, 25mV] signal, then the power source must be guaranteed to be stable whenever the supply to the voltage regulator is stable.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process For unused AGTL inputs, the on-die termination will be sufficient. No external RTT is necessary on the motherboard For unused CMOS inputs, active low signals should be connected through a pull-up resistor to VCCCMOS1.5 and meet VIH requirements. Unused active high CMOS inputs should be connected through a pull-down resistor to ground (VSS) and meet VIL requirements. Unused CMOS outputs can be left unconnected.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 4. System Bus Signal Groups 1 Group Name Signals AGTL Input BPRI#, DEFER#, RESET#, RSP# AGTL Output PRDY# AGTL I/O A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#2, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#, RS[2:0]#, TRDY# CMOS Input (1.25 V)3 VTT_PWRGD CMOS Input (1.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 2.8.2 System Bus Frequency Select Signals The System Bus Frequency Select Signals (BSEL [1:0]) are used to select the system bus frequency for the processor. The BSEL signals are also used by the chipset and system bus clock generator. The BSEL pins for the processor are open drain signals versus opens or shorts found on the previous Intel Celeron FC-PGA processor. Refer to Table 11 for level specifications for the BSEL signals.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 2.9 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the processor be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 7 through Table 13 list the voltage level specifications for the processor. Specifications are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter. Table 7. Voltage and Current Specifications (Sheet 1 of 2) Symbol VCCCORE VCC for processor core Core Freq Min Typ 1.4 GHz 1.5 1.30 GHz 1.5 1.20 GHz 1.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 7. Voltage and Current Specifications (Sheet 2 of 2) Symbol dIvTT/dt Parameter Core Freq Min Typ Termination current slew rate Max Unit Notes1, 2 Table 13 A/µs 8, 9, 10 See Table 13 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All specifications in this table apply only to the Celeron processor based on 0.13 micron process core. 3.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 9.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 10. AGTL Signal Group Levels Specifications Symbol Parameter Min Notes1 Max Unit VREF - 0.200 V 6 V 2, 3, 6 VIL Input Low Voltage VIH Input High Voltage Ron Buffer On Resistance 16.67 Ω 5 IL Leakage Current for inputs, outputs, and I/O ±100 µA 4, 7 VREF + 0.200 NOTES: 1. Unless otherwise noted, all specifications in this table apply to the processor at a frequency up to 1.40 GHz on 0.13 micron. 2.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 12. 3.3 Volt CMOS Output Signal Group DC Specifications Symbol 2.12 Parameter Min Max Unit V Nominal Voltage 3.45 V VOH Output High Voltage 0.9 V ILO Output Leakage Current 100 µA Notes 3.3 + 5% AGTL System Bus Specifications It is recommended that the AGTL bus be routed in a daisy-chain fashion with termination resistors to VTT.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 2.13 System Bus Timing Specifications The processor system bus timings specified in this section are defined at the socket pins on the bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins during manufacturing. Timings at the processor pins are specified by design characterization. See Section 7.0 for the processor signal definitions.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 15. System Bus Timing Specifications (Differential Clock) 100 MHz T# Parameter Unit Figure 9 Notes 1,2,6 Min Max T1: BCLK Period - average 10.0 10.2 nS T1abs: BCLK Period - Instantaneous minimum 9.8 nS 3, 4 200 pS 5 T2: BCLK Period Stability 3, 4 Vcross: Crossing point at 1V Swing 0.51 0.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 16. Valid System Bus to Core Frequency Ratios 1, 2, 3 Processor Core Frequency BCLK Frequency (MHz) Frequency Multiplier 1.4 GHz 1.40 100 14 1.30 1.30 GHz 100 13 1.20 1.20 GHz 100 12 1.204 1.204 GHz 100 12 1.1A 1.1A GHz 100 11 1A 1A GHz 100 10 900 900 MHz 100 9 NOTES: 1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency multipliers. 2.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 4. All CMOS outputs shall be asserted for at least 2 system bus clocks. 5. When driven inactive or after VCCCORE, VTT, VCCCMOS, and BCLK and BCLK# are stable. Table 19.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 21. System Bus Timing Specifications (TAP Connection) T# Parameter Min T30: TCK Frequency Max Unit 16.667 MHz Notes 1,2,3 Figure T31: TCK Period 60.0 ns 10 T32: TCK High Time 25.0 ns 10 Vcmos_ref + 0.200 V, 10 T33: TCK Low Time 25.0 ns 10 Vcmos_ref – 0.200 V, 10 ns 10 (Vcmos_ref – 0.200 V) – (Vcmos_ref + 0.200 V), T34: TCK Rise Time 5.0 4, 10 T35: TCK Fall Time 5.0 ns 10 (Vcmos_ref + 0.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 22. Platform Power-On Timings T# Parameter Min Max Unit Figure Notes 2 T45: Valid Time Before VTT_PWRGD 1.0 mS 14 1 T46: Valid Time Before PWRGOOD 2.0 mS 14 1 T47: RESET# Inactive to Valid Outputs 1 BCLK 14 1 T48: RESET# Inactive to Drive Signals 4 BCLK 14 1 NOTES: 1.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Figure 10. BCLK/BCLK#, PICCLK, and TCK Generic Clock Waveform Tp Th Vih diff Vringback (rise) V2 0V V3 V1 Vringback (fall) Vil diff Tr Tf Th Tl Tp V1 = = = = = = T5, T25, T34, (Rise Tim e) Tf Tl Tr T6, T26, T35, (Fall Tim e) T3, T23, T32, (High Tim e) T4, T24, T33, (Low Tim e) T1, T22, T31 (BC LK, TCK, PIC CLK Period) B CLK is referenced to 0.30V (D ifferential M ode), 0.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Figure 12. System Bus Setup and Hold Timings BCLK# VCross BCLK Ts V Th Valid VCross = Crossing point of BLCK and BCLK# Ts = T8, T27 (Setup Time) NOTE: Single-Ended clock uses BCLK only, Differential clock uses BCLK and BCLK# Th = T9, T28 (Hold Time) V = Vref for AGTL signal group; 0.75V for APIC and TAP signal groups Figure 13.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Figure 14. Platform Power-On Sequence and Timings Vtt, Vref Vcmosref VID Valid BSEL[1:0] Valid T45 VTT_PWRGD VCC_Core BCLK# BCLK PICCLK T46 VCC_PWRGD Configuration Inputs Inactive Valid Config RESET# Active T47 THERMTRIP# Valid PICD[1:0] Valid AGTL Outputs Valid All other CMOS Outputs Valid All other Inputs Inactive Active T48 Figure 15.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Figure 16. Test Timings (TAP Connection) TCK Tv Tw Tr Ts TDI, TMS Input Signal Tx Tu Ty Tz TDO Output Signal Tr = T43 (All Non-Test Inputs Setup Time) Ts = T44 (All Non-Test Inputs Hold Time) Tu = T40 (TDO Float Delay) Tv = T37 (TDI, TMS Setup Time) Tw = T38 (TDI, TMS Hold TIme) Tx = T39 (TDO Valid Delay) Ty = T41 (All Non-Test Outputs Valid Delay) Tz = T42 (All Non-Test Outputs Float Time) Figure 17.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 3.0 Signal Quality Specifications Signals driven on the processor system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component. Specifications are provided for simulation at the processor pins.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Figure 18. BCLK/BCLK#, PICCLK Generic Clock Waveform at the Processor Pins V3 V4 V2 V1 V5 V3 3.2 AGTL Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of AGTL layout guidelines which are available in the appropriate platform design guide. Refer to the Intel® Pentium® II Processor Developer's Manual (Order Number 243502) for the AGTL buffer specification.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Figure 19. Low to High AGTL Receiver Ringback Tolerance τ α VREF + 0.2 φ VREF ρ VREF - 0.2 δ 0.7V Clk Ref Vstart Clock Time Note: High to low case is analogous i 3.2.1 b k t l Overshoot/Undershoot Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast signal edge rates.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 3.2.2 Overshoot/Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level, VSS (overshoot) and VTT (undershoot). While overshoot can be measured relative to VSS using one probe (probe to signal and GND lead to VSS), undershoot must be measured relative to VTT. This could be accomplished by simultaneously measuring the VTT plane while measuring the signal undershoot.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can be NO other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event occurs at all times and no other events can occur). Note: Activity factor for AGTL signals is referenced to system bus clock frequency. Note: Activity factor for CMOS signals is referenced to PICCLK frequency. 3.2.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 3.2.6 Determining if a System Meets the Overshoot/Undershoot Specifications The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, AF and magnitude).
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Figure 20. Maximum Acceptable AGTL Overshoot/Undershoot Waveform Time dependent Overshoot 0.1 ns 0.3 ns 1.78 V Max 1.62 V 1.47 V 1.32 V 1 ns Vos_ref a b c a Vss -0.15 V -0.30 V -0.46 V Min 0.1 ns c b 0.3 ns 1 ns Time dependent Undershoot 3.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 3.3.1 Overshoot/Undershoot Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast signal edge rates (see Figure 21 for non-AGTL signals). The processor can be damaged by repeated overshoot events on 1.25 V or 1.8 V tolerant buffers if the charge is large enough (i.e.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 29. Signal Ringback Specifications for Non-AGTL Signal Simulation at the Processor Pins Transition Maximum Ringback (with Input Diodes Present) Unit Figure Non-AGTL Signals 2 0→1 Vcmos_ref + 0.200 V 21 Non-AGTL Signals 2 1→0 Vcmos_ref - 0.300 V 21 0→1 1.44 V 21 Input Signal Group PWRGOOD NOTES: 1. Unless otherwise noted, all specifications in this table apply to the processor up to 1.40 GHz frequency. 2.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 3.4.2 Transition time The transition time is defined as the time the signal takes to move through the transition region. A 100 microsecond transition time will ensure that the processor receives a good transition edge. 3.4.3 Noise The signal quality of the VTT_PWRGD signal is critical to the correct operation of the processor. Every effort should be made to ensure this signal is monotonic in the transition region.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 4.0 Thermal Specifications and Design Considerations This chapter provides needed data for designing a thermal solution. However, for the correct thermal measuring processes, refer to Intel® Pentium® III Processor in the FC-PGA2, 370-pin Package Thermal Design Guidelines (Order Number 249660). The processor uses flip chip pin grid array packaging technology with a Integrated Heat Spreader and has a case temperature (Tcase) specified.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 4.1.2 Thermal Diode The processor incorporates an on-die diode that may be used to monitor the die temperature (junction temperature). A thermal sensor located on the motherboard, or a stand-alone measurement kit, may monitor the die temperature of the processor for thermal management or instrumentation purposes. Table 32 and Table 33 provide the diode parameter and interface specifications.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 5.0 Mechanical Specifications The processor uses a FC-PGA2 package technology. Mechanical specifications for the processor are given in this section. See Section 1.1.1 for a complete terminology listing. The processor utilizes a PGA370 socket for installation into the motherboard. Details on the socket are available in the 370-Pin Socket (PGA370) Design Guidelines. Note: For Figure 23, the following apply: 1.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 34. The Processor Package Dimensions Millimeters Inches Symbol A1 Minimum Maximum 2.266 2.690 Notes Minimum Maximum 0.089 0.106 A2 0.980 1.180 0.038 0.047 B1 30.800 31.200 1.212 1.229 B2 30.800 31.200 1.212 1.229 C1 33.000 max C2 1.299 max 33.000 max 1.299 max D 49.428 49.632 1.946 1.954 D1 45.466 45.974 1.790 1.810 G1 0.000 17.780 0.000 0.700 G2 0.000 17.780 0.000 0.700 G3 0.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 5.2 Recommended Mechanical Keep-Out Zones Figure 24. Volumetric Keep-Out Figure 25.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 5.3 Processor Markings Figure 26 shows the processor top-side markings and it is provided to aid in the identification of the Celeron processor. Table 34 lists the measurements for the package dimensions. Figure 26.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 5.4 Processor Signal Listing Table 36 and Table 37 provide the processor pin definitions. The signal locations on the PGA370 socket are to be used for signal routing, simulation, and component placement on the baseboard. Figure 27 provides a pin-side view of the processor pinout. Figure 27.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 36. Signal Listing in Order by Signal Name Pin No. AH6 58 Pin Name A10# Signal Group Table 36. Signal Listing in Order by Signal Name (Continued) Pin No.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 36. Signal Listing in Order by Signal Name (Continued) Pin No. Datasheet Pin Name Signal Group Table 36. Signal Listing in Order by Signal Name (Continued) Pin No.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 36. Signal Listing in Order by Signal Name (Continued) Pin No. N33 60 Pin Name Reserved Signal Group Table 36. Signal Listing in Order by Signal Name (Continued) Pin No.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 36. Signal Listing in Order by Signal Name (Continued) Pin No. Datasheet Pin Name Signal Group Table 36. Signal Listing in Order by Signal Name (Continued) Pin No.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 36. Signal Listing in Order by Signal Name (Continued) Pin No. 62 Pin Name Signal Group Table 36. Signal Listing in Order by Signal Name (Continued) Pin No.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 37. Signal Listing in Order by Pin Number Pin No. Datasheet Pin Name Signal Group A3 D29# AGTL I/O A5 D28# A7 D43# Table 37. Signal Listing in Order by Pin Number (Continued) Pin No.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 37. Signal Listing in Order by Pin Number (Continued) Pin No. 64 Pin Name Signal Group Power/Other Table 37. Signal Listing in Order by Pin Number (Continued) Pin No.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 37. Signal Listing in Order by Pin Number (Continued) Pin No. AN19 Datasheet Pin Name DEFER# Signal Group Table 37. Signal Listing in Order by Pin Number (Continued) Pin No.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 37. Signal Listing in Order by Pin Number (Continued) Pin No. E31 66 Pin Name DEP4# Signal Group Table 37. Signal Listing in Order by Pin Number (Continued) Pin No.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 37. Signal Listing in Order by Pin Number (Continued) Pin No. R34 Datasheet Pin Name Vss Signal Group Table 37. Signal Listing in Order by Pin Number (Continued) Pin No.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 6.0 Boxed Processor Specifications The processor for the PGA370 socket is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from motherboards and standard components. The boxed processor will be supplied with an unattached fan heatsink. This section documents motherboard and system requirements for the fan heatsink that will be supplied with the boxed processor.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process The dimensions for the boxed processor with the integrated fan heatsink are shown in Figure 30. All dimensions are in inches. The processor uses a new technology termed FC-PGA2. The FC-PGA2 package leverages the previous FC-PGA package technology used on processors based on the 0.18 micron process. The FC-PGA2 package adds an Integrated Heat Spreader (IHS) to improve heat conduction from the processor die.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 38. Boxed Processor Fan Heatsink Spatial Dimensions Dimensions (Inches) Min Typ Max Units Fan Heatsink Length 3.14 Inches Fan Heatsink Height 1.81 Inches Fan Heatsink Width 2.6 Inches 0.33 Inches Fan Heatsink height above motherboard 0.29 Air Keepout Zones from end of Fan Heatsink 0.20 0.30 Inches Figure 31. Dimensions of Mechanical Step Feature in Heatsink Base 0.043 0.472 Units = inches 6.1.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process also recommended that the air temperature entering the fan be kept below 45 degrees C. Again, meeting the processor’s temperature specification is the responsibility of the system integrator. The processor temperature specification is found in Section 4.1 of this document. Figure 32. Thermal Airspace Requirement for all Boxed Processor Fan Heatsinks in the PGA370 Socket Measure ambient temperature 0.3 inches above center of fan inlet 0.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Figure 33. Boxed Processor Fan Heatsink Power Cable Connector Description Pin Signal 1 GND Straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. 2 +12V 0.100" pin pitch, 0.025" square pin width. 3 SENSE Waldom/Molex P/N 22-01-3037 or equivalent. Match with straight pin, friction lock header on motherboard Waldom/Molex P/N 22-23-2031, AMP P/N 640456-3, or equivalent. 1 2 3 Table 39.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process 7.0 Processor Signal Description This section provides an alphabetical listing of all the processor signals. The tables at the end of this section summarize the signals by direction: output, input, and I/O. 7.1 Alphabetical Signals Reference Table 40.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 40. Signal Description (Sheet 2 of 8) Name Type Description The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents, and must connect the appropriate pins of all such agents, if used. However, the processor does not observe assertions of the BERR# signal.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 40. Signal Description (Sheet 3 of 8) Name BSEL[1:0] Type O Description The BSEL signals are CMOS signals which are used to select the system bus frequency. A BSEL[1:0] = ‘01’ selects a 100 MHz system bus frequency. The frequency is determined by the processor(s), chipset, and frequency synthesizer capabilities. All system bus agents must operate at the same frequency. The processor operates at 100 MHz system bus frequency.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 40. Signal Description (Sheet 4 of 8) Name Type Description DYN_OE I The DYN_OE allows the BSEL and VID signals to be driven out from the processor. When this signal is low (a condition that will occur if the processor is installed in a non-supported platform), the VID and BSEL signals will be tri-stated and the platform pull-up resistors will set the VID and BSEL to all 1s which is a safe setting.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 40. Signal Description (Sheet 5 of 8) Name LINT[1:0] Type Description I The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all APIC Bus agents, including all processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 40. Signal Description (Sheet 6 of 8) Name Type Description Asserting the RESET# signal resets all processors to known states and invalidates their L1 and L2 caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCCCORE and CLK have reached their proper specifications.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 40. Signal Description (Sheet 7 of 8) Name Type Description I The SMI# (System Management Interrupt) signal is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 40. Signal Description (Sheet 8 of 8) Name Type Description VID [3:0,25mV] O The VID[3:0, 25 mV] (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are CMOS signals that must be pulled up to 3.3 V power rail with 1 KΩ resistors. The VID pins are needed to cleanly support voltage specification variations on processors. See Table 3 for definitions of these pins.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 42.
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process Table 44.