Intel® Celeron® Processor in the 478-Pin Package up to 1.80 GHz Datasheet ■ ■ ■ ■ ■ ■ ■ Available at 1.70 and 1.80 GHz Binary compatible with applications running on previous members of the Intel microprocessor line System bus frequency at 400 MHz. Rapid Execution Engine: Arithmetic Logic Units (ALUs) run at twice the processor core frequency. Hyper Pipelined Technology.
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Intel® Celeron® Processor in the 478-Pin Package Contents 1.0 Introduction......................................................................................................................... 9 1.1 1.2 2.0 Electrical Specifications....................................................................................................13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3.0 Package Load Specifications ..............................................................................
Intel® Celeron® Processor in the 478-Pin Package 6.0 Thermal Specifications and Design Considerations......................................................... 79 6.1 6.2 7.0 Features ........................................................................................................................... 83 7.1 7.2 7.3 8.0 8.2 8.3 Mechanical Specifications................................................................................... 90 8.1.1 Boxed Processor Cooling Solution Dimensions .........
Intel® Celeron® Processor in the 478-Pin Package Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Datasheet Typical Vcciopll, Vcca and Vssa Power Distribution ...........................................16 Phase Lock Loop (PLL) Filter Requirements ......................................................17 Vcc Static and Transient Tolerance ....................................................................24 AC Test Circuit .............
Intel® Celeron® Processor in the 478-Pin Package Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 6 Reference Documents ........................................................................................ 11 Voltage Identification Definition........................................................................... 15 System Bus Pin Groups ......................................................................................
Intel® Celeron® Processor in the 478-Pin Package Revision History Revision Datasheet Description Date -001 Initial Release. May 2002 -002 Added 1.80 GHz specifications.
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Intel® Celeron® Processor in the 478-Pin Package 1.0 Introduction The Intel® Celeron® processor in the 478-pin package utilizes Flip-Chip Pin Grid Array (FC-PGA2) package technology, and plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Celeron processor in the 478-pin package maintains the tradition of compatibility with IA-32 software. The Celeron processor in the 478-pin package is designed for uni-processor based Value PC desktop systems.
Intel® Celeron® Processor in the 478-Pin Package 1.1.1 Processor Packaging Terminology Commonly used terms are explained here for clarification: • Celeron® processor in the 478-pin package (also referred as the Processor) — 0.18 micron processor core in the FC-PGA2 package with a 128 KB L2 cache. • Pentium® 4 processor in the 478-pin package — 0.18 micron Pentium® 4 processor core in the FC-PGA2 package with a 256 KB L2 cache.
Intel® Celeron® Processor in the 478-Pin Package 1.2 References Material and concepts available in the following documents may be beneficial when reading this document: Table 1. Reference Documents Document Datasheet Order Number Intel® Pentium® 4 Processor in the 478-Pin Package and Intel® 850 Chipset Platform Design Guide http://developer.intel.com/design/ pentium4/guides/249888.
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Intel® Celeron® Processor in the 478-Pin Package 2.0 Electrical Specifications 2.1 System Bus and GTLREF Celeron processors in the 478-pin package system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signalling technology. As with the Intel P6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates.
Intel® Celeron® Processor in the 478-Pin Package 2.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low power states, must be provided by the voltage regulator solution (VR).
Intel® Celeron® Processor in the 478-Pin Package Table 2. Datasheet Voltage Identification Definition VID4 VID3 VID2 VID1 VID0 VCC_MAX 1 1 1 1 1 VRM output off 1 1 1 1 0 1.100 1 1 1 0 1 1.125 1 1 1 0 0 1.150 1 1 0 1 1 1.175 1 1 0 1 0 1.200 1 1 0 0 1 1.225 1 1 0 0 0 1.250 1 0 1 1 1 1.275 1 0 1 1 0 1.300 1 0 1 0 1 1.325 1 0 1 0 0 1.350 1 0 0 1 1 1.375 1 0 0 1 0 1.400 1 0 0 0 1 1.425 1 0 0 0 0 1.
Intel® Celeron® Processor in the 478-Pin Package 2.3.4 Phase Lock Loop (PLL) Power and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Celeron processor in the 478-pin package . Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e. maximum frequency).
Intel® Celeron® Processor in the 478-Pin Package . Figure 2. Phase Lock Loop (PLL) Filter Requirements 0.2dB 0dB 0.5 dB Forbidden Zone Forbidden Zone -28dB -34dB DC 1Hz fpeak 1 MHz passband 66 MHz fcore high frequency band NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz.
Intel® Celeron® Processor in the 478-Pin Package 2.4 Reserved, Unused, and TESTHI Pins All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with a future Celeron processors in the 478-pin package. See Chapter 5.0 for a pin listing of the processor and the location of all RESERVED pins.
Intel® Celeron® Processor in the 478-Pin Package 2.5 System Bus Signal Groups To simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term AGTL+ Input refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, AGTL+ Output refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
Intel® Celeron® Processor in the 478-Pin Package 2.6 Asynchronous GTL+ Signals The Celeron processor in the 478-pin package does not utilize CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output FERR# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) utilize GTL+ output buffers.
Intel® Celeron® Processor in the 478-Pin Package 2.9 Maximum Ratings Table 5 lists the processor’s maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Intel® Celeron® Processor in the 478-Pin Package 2.10.1 Flexible Motherboard Guidelines (FMB) The FMB guidelines are estimates of the maximum values the Celeron processor in the 478-pin package will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. The Celeron processor in the 478-pin package may or may not have specifications equal to the FMB value in the foreseeable future.
Intel® Celeron® Processor in the 478-Pin Package Table 7. VCC Static and Transient Tolerance Voltage Deviation from VID Setting (V)1, 2, 3 Icc (A) Maximum Typical Minimum 0 0.000 –0.025 –0.050 5 –0.010 –0.037 –0.064 10 –0.019 –0.048 –0.078 15 –0.029 –0.060 –0.092 20 –0.038 –0.072 –0.106 25 –0.048 –0.083 –0.120 30 –0.057 –0.095 –0.133 35 –0.067 –0.107 –0.147 40 –0.076 –0.119 –0.161 45 –0.085 –0.130 –0.175 50 –0.095 –0.142 –0.189 55 –0.105 –0.154 –0.
Intel® Celeron® Processor in the 478-Pin Package Figure 3. VCC Static and Transient Tolerance 1.800 1.750 1.700 Vcc [V] Vcc Maximum 1.650 Vcc Typical 1.600 Vcc Minimum 1.550 1.500 1.450 0 10 20 30 40 50 60 70 80 Icc Load [A] NOTES: 1. The loadline specification includes both static and transient limits. 2. This loadline specification applies to processors with a VID setting of 1.75 V. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins.
Intel® Celeron® Processor in the 478-Pin Package Table 8. System Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VL Input Low Voltage –.150 0.000 N/A V 6 VH Input High Voltage 0.660 0.710 0.850 V 6 VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 6, 7 2, 3, 8 VCROSS(rel) Relative Crossing Point V 6, 7 2, 3, 8, 9 ∆VCROSS Range of Crossing Points N/A N/A 0.140 V 6, 7 2, 10 VOV Overshoot N/A N/A VH + 0.
Intel® Celeron® Processor in the 478-Pin Package Table 10. Asynchronous GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit VIL Input Low Voltage 0.0 GTLREF-0.100 VIH Input High Voltage GTLREF+0.100 VCC VOH Output High Voltage VCC V IOL Output Low Current 64 mA Notes1 3 4, 5, 7 ILI Input Leakage Current N/A ± 100 µA ILO Output Leakage Current N/A ± 100 µA RON Buffer On Resistance 5 11 W 2, 5, 7 8, 9 6 NOTES: 1.
Intel® Celeron® Processor in the 478-Pin Package 2.11 AGTL+ System Bus Specifications Routing topology recommendations may be found in the appropriate Platform Design Guide as referenced in Table 1. Termination resistors are not required for most AGTL+ signals, as these are integrated into the processor silicon. Valid high and low levels are determined by the input buffers which compare a signal’s voltage with a reference voltage called GTLREF (known as VREF in previous documentation).
Intel® Celeron® Processor in the 478-Pin Package 2.12 System Bus AC Specifications The processor system bus timings specified in this section are defined at the processor core silicon and are thus not measurable at the processor pins. See Chapter 5.0 for the Celeron processor in the 478-pin package pin signal definitions. Table 14 through Table 18 list the AC specifications associated with the processor system bus.
Intel® Celeron® Processor in the 478-Pin Package . Table 14. System Bus Common Clock AC Specifications T# Parameter Min Max Unit Figure Notes1,2,3 T10: Common Clock Output Valid Delay 0.200 1.45 ns 8 4 T11: Common Clock Input Setup Time 0.65 N/A ns 8 5 T12: Common Clock Input Hold Time 0.40 N/A ns 8 5 T13: RESET# Pulse Width 1.00 10.00 ms 9 6, 7, 8 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Not 100% tested.
Intel® Celeron® Processor in the 478-Pin Package Table 15. System Bus Source Synch AC Specifications AGTL+ Signal Group Max Unit Figure Notes1,2,3,4 1.20 ns 10, 11 5 0.85 ns 11 5, 8 T22: TVAD: Source Synchronous Data Output Valid After Strobe 0.85 ns 11 5, 8 T23: TVBA: Source Synchronous Address Output Valid Before Strobe 1.88 ns 10 5, 8 T24: TVAA: Source Synchronous Address Output Valid After Strobe 1.88 ns 10 5, 9 T25: TSUSS: Source Synchronous Input Setup Time to Strobe 0.
Intel® Celeron® Processor in the 478-Pin Package Table 16. Miscellaneous Signals AC Specifications T# Parameter Min T35: Asynch GTL+ Input Pulse Width 2 T36: PWRGOOD to RESET# de-assertion time 1 T37: PWRGOOD Inactive Pulse Width T38: PROCHOT# pulse width Max Unit Figure Notes1,2,3,6 BCLKs ms 12 10 BCLKs 12 4 500 us 14 5 s 13 T39: THERMTRIP# Assertion until VCC removal 10 0.5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
Intel® Celeron® Processor in the 478-Pin Package Table 18. TAP Signals AC Specifications Parameter Notes1,2,3,9 Max Unit Figure ns 5 T56: TCK Rise Time 9.5 ns 5 4 T57: TCK Fall Time 9.5 ns 5 4 T58: TMS, TDI Rise Time 8.5 ns 5 4 T55: TCK Period Min 60.0 T59: TMS, TDI Fall Time T61: TDI, TMS Setup Time 8.5 T62: TDI, TMS Hold Time T63: TDO Clock to Output Delay T64: TRST# Assert Time ns 5 4 ns 15 5, 7 3 ns 15 5, 7 3.5 ns 15 6 TCK 14 8 0 0.5 2 NOTES: 1.
Intel® Celeron® Processor in the 478-Pin Package The circuit used to test the AC specifications is shown in Figure 4. Figure 4. AC Test Circuit VCC VCC Rload 2.4nH 600 mils, 42 ohms, 169 ps/in 1.2pF AC Timings test measurements made here. Rload = 50 ohms Figure 5. TCK Clock Waveform Tr *V2 *V3 CLK *V1 T f Tp Tr = T56, T58 (Rise Time) Tf = T57, T59 (Fall Time) Tp = T55 (Period) V1, V2: For rise and fall times, TCK is measured between 20% to 80% points on the waveform.
Intel® Celeron® Processor in the 478-Pin Package . Figure 6.
Intel® Celeron® Processor in the 478-Pin Package Figure 8. System Bus Common Clock Valid Delay Timings T0 T1 T2 BCLK1 BCLK0 TP Common Clock Signal (@ driver) valid valid TQ TR Common Clock Signal (@ receiver) valid TP = T10: TCO (Data Valid Output Delay) TQ = T11: TSU (Common Clock Setup) TR = T12: TH (Common Clock Hold Time) Figure 9.
Intel® Celeron® Processor in the 478-Pin Package Figure 10. Source Synchronous 2X (Address) Timings T1 2.5 ns 5.0 ns T2 7.5 ns BCLK1 BCLK0 TP ADSTB# (@ driver) TR TH A# (@ driver) valid TJ TH TJ valid TS ADSTB# (@ receiver) TK A# (@ receiver) valid valid TN TM TH = T23: Source Sync. Address Output Valid Before Address Strobe TJ = T24: Source Sync. Address Output Valid After Address Strobe TK = T27: Source Sync. Input Setup to BCLK TM = T26: Source Sync.
Intel® Celeron® Processor in the 478-Pin Package Figure 11. Source Synchronous 4X Timings T0 T1 2.5 ns 5.0 ns T2 7.5 ns BCLK1 BCLK0 DSTBp# (@ driver) TH DSTBn# (@ driver) TA TB TA TD D# (@ driver) DSTBp# (@ receiver) TJ DSTBn# (@ receiver) TC D# (@ receiver) TE TG TE TG TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T27: Source Sync. Setup Time to BCLK TD = T30: Source Sync.
Intel® Celeron® Processor in the 478-Pin Package Figure 13. THERMTRIP# Power Down Sequenc e T39 THERMTRIP# Vcc T39 < 0.5 seconds Note: THERMTRIP# is undefined when RESET# is active Figure 14. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform V Tq T = T38 (PROCHOT# Pulse Width), V=GTLREF q T64 (TRST# Pulse Width), V=0.5*Vcc Figure 15. TAP Valid Delay Timing Waveform TCK V Tx Signal Ts Th V Valid Tx = T63 (Valid Time) Ts = T61 (Setup Time) Th = T62 (Hold Time) V = 0.
Intel® Celeron® Processor in the 478-Pin Package 3.0 System Bus Signal Quality Specifications Source synchronous data transfer requires the clean reception of data signals and their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines.
Intel® Celeron® Processor in the 478-Pin Package Figure 16. BCLK Signal Integrity Waveform Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot 3.2 System Bus Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of AGTL+ layout guidelines that are available in the Platform Design Guidelines.
Intel® Celeron® Processor in the 478-Pin Package Table 21. Ringback Specifications for TAP and PWRGOOD Signal Groups Signal Group Transition Maximum Ringback (with Input Diodes Present) Unit Figure TAP and PWRGOOD 0→1 Vt+ (max) to Vt– (max) V 19 1,2,3 TAP and PWRGOOD 1→0 Vt– (min) to Vt+ (min) V 20 1,2,3 Notes NOTES: 1. All signal integrity specifications are measured at the processor silicon. 2. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Intel® Celeron® Processor in the 478-Pin Package Figure 19. Low-to-High System Bus Receiver Ringback Tolerance for TAP and PWRGOOD Buffers Vcc Threshold Region to switch receiver to a logic 1. Vt+ (max) Vt+ (min) 0.5 * Vcc Vt- (max) Allowable Ringback Vss Figure 20. High-to-Low System Bus Receiver Ringback Tolerance for TAP and PWRGOOD Buffers Vcc Allowable Ringback Vt+ (min) 0.5 * Vcc Vt- (max) Vt- (min) Threshold Region to switch receiver to a logic 0.
Intel® Celeron® Processor in the 478-Pin Package 3.2.1 Overshoot/Undershoot Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage (or below VSS) as shown in Figure 21. The overshoot/undershoot guidelines limit transitions beyond VCC or VSS due to the fast signal edge rates. The processor can be damaged by repeated overshoot or undershoot events on any input, output, or I/O buffer if the charge is large enough (i.e.
Intel® Celeron® Processor in the 478-Pin Package 3.2.1.3 Activity Factor Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any common clock signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles.
Intel® Celeron® Processor in the 478-Pin Package 3.2.1.5 Determining if a System Meets the Over/Undershoot Specifications The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, AF and magnitude).
Intel® Celeron® Processor in the 478-Pin Package Table 22. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 2.30 –0.585 0.06 0.63 5.00 2.25 –0.535 0.11 1.10 5.00 2.20 –0.485 0.22 2.20 5.00 2.15 –0.435 0.41 4.10 5.00 2.10 –0.385 0.75 5.00 5.00 2.05 –0.335 1.35 5.00 5.00 2.00 –0.285 2.50 5.
Intel® Celeron® Processor in the 478-Pin Package Table 24. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 2.30 –0.585 0.24 2.4 20.0 2.25 –0.535 0.44 4.4 20.0 2.20 –0.485 0.88 8.8 20.0 2.15 –0.435 1.64 16.4 20.0 2.10 –0.385 3.0 20.0 20.0 2.05 –0.335 5.4 20.0 20.0 2.00 –0.285 10.0 20.0 20.0 1.
Intel® Celeron® Processor in the 478-Pin Package Figure 21.
Intel® Celeron® Processor in the 478-Pin Package 4.0 Package Mechanical Specifications The Celeron processor in the 478-pin package is packaged in a Flip-Chip Pin Grid Array (FCPGA2) package. Components of the package include an integrated heat spreader (IHS), processor core, and the substrate which is the pin carrier. Mechanical specifications for the processor are given in this section. See Section 1.1 for a terminology listing.
Intel® Celeron® Processor in the 478-Pin Package Figure 23. Intel® Celeron® Processor in the 478-Pin Package Table 26. Description Table for Processor Dimensions Code Letter A1 Min (mm) 2.266 Nominal (mm) 2.378 0.980 1.080 1.180 B1 30.800 31.000 31.200 B2 30.800 31.000 31.200 C2 Notes 2.490 A2 C1 33.000 Includes Placement Tolerance 33.000 Includes Placement Tolerance D 34.900 35.000 35.100 D1 31.500 31.750 32.000 G1 13.970 Keepin Zone Dimension G2 13.
Intel® Celeron® Processor in the 478-Pin Package Figure 24 details the keep in specification for pin-side components. The Celeron processor in the 478-pin package may contain pin side capacitors mounted to the processor package. Figure 26 details the flatness and tilt specifications for the IHS. Tilt is measured with the reference datum set to the bottom of the processor interposer. Figure 24. Processor Cross-Section and Keep-in FCPGA 2 IHS Substrate 1.25mm 13.
Intel® Celeron® Processor in the 478-Pin Package Figure 26. IHS Flatness Specification IHS SUBSTRATE NOTES: 1. Flatness is specific as overall, not per unit of length. 2. All dimensions are in mm. 4.1 Package Load Specifications Table 27 provides dynamic and static load specifications for the Celeron processor in the 478-pin package IHS. These mechanical load limits should not be exceeded during heatsink assembly, mechanical stress testing, or standard drop and shipping conditions.
Intel® Celeron® Processor in the 478-Pin Package 4.2 Processor Insertion Specifications The Celeron processor in the 478-pin package can be inserted and removed 15 times from a mPGA478B socket that meets the specifications in the Intel® Pentium®4 Processor 478-Pin Socket (mPGA478B) Socket Design Guidelines. 4.3 Processor Mass Specifications Table 28 specifies the processor’s mass. This includes all components which make up the entire processor product. ** Table 28. Processor Mass 4.
Intel® Celeron® Processor in the 478-Pin Package 4.6 Processor Pin-Out Coordinates Figure 28 and Figure 29 show the processor pin coordinates. Figure 28.
Intel® Celeron® Processor in the 478-Pin Package Figure 29.
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Intel® Celeron® Processor in the 478-Pin Package 5.0 Pin Listing and Signal Definitions 5.1 Intel® Celeron® Processor in the 478-Pin Package Pin Assignments Table 30 and Table 31 are pinlists for the Celeron processor in the 478-pin package. Table 30 is a listing of all processor pins ordered alphabetically by pin name. Table 31 is also a listing of all processor pins but ordered by pin number.
Intel® Celeron® Processor in the 478-Pin Package Table 30. Pin Listing by Pin Name Pin Name 58 Pin # A3# K2 A4# K4 A5# L6 A6# K1 A7# Signal Buffer Type Source Synch Direction Table 30.
Intel® Celeron® Processor in the 478-Pin Package Table 30.
Intel® Celeron® Processor in the 478-Pin Package Table 30. Pin Listing by Pin Name Pin Name 60 Pin # Signal Buffer Type Direction Table 30.
Intel® Celeron® Processor in the 478-Pin Package Table 30. Pin Listing by Pin Name Pin Name Pin # Signal Buffer Type Direction Table 30.
Intel® Celeron® Processor in the 478-Pin Package Table 30. Pin Listing by Pin Name Pin Name 62 Pin # Signal Buffer Type Direction Table 30.
Intel® Celeron® Processor in the 478-Pin Package Table 30. Pin Listing by Pin Name Pin Name Pin # Signal Buffer Type Direction Table 30.
Intel® Celeron® Processor in the 478-Pin Package Table 30. Pin Listing by Pin Name Pin Name 64 Pin # VSS T21 VSS VSS Signal Buffer Type Direction Table 30.
Intel® Celeron® Processor in the 478-Pin Package Table 31. Pin Listing by Pin Number Pin # A2 Pin Name THERMTRIP# Signal Buffer Type Asynch GTL+ Direction Output Table 31.
Intel® Celeron® Processor in the 478-Pin Package Table 31. Pin Listing by Pin Number Pin # AB26 66 Pin Name SLP# Signal Buffer Type Direction Table 31.
Intel® Celeron® Processor in the 478-Pin Package Table 31. Pin Listing by Pin Number Pin # Pin Name Signal Buffer Type AE24 VSS Power/Other AE25 DBR# Power/Other AE26 VSS Power/Other AF1 VSS AF2 VCC Direction Table 31.
Intel® Celeron® Processor in the 478-Pin Package Table 31. Pin Listing by Pin Number Pin # 68 Pin Name Signal Buffer Type Direction Table 31.
Intel® Celeron® Processor in the 478-Pin Package Table 31. Pin Listing by Pin Number Pin # F21 Pin Name DSTBP0# Signal Buffer Type Source Synch Direction Input/Output Table 31.
Intel® Celeron® Processor in the 478-Pin Package Table 31. Pin Listing by Pin Number Pin # M25 70 Pin Name VSS Signal Buffer Type Direction Power/Other Table 31.
Intel® Celeron® Processor in the 478-Pin Package Table 31.
Intel® Celeron® Processor in the 478-Pin Package 5.2 Signal Descriptions Table 32. Signal Description (Sheet 1 of 7) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Celeron processor in the 478-pin package system bus.
Intel® Celeron® Processor in the 478-Pin Package Table 32. Signal Description (Sheet 2 of 7) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
Intel® Celeron® Processor in the 478-Pin Package Table 32. Signal Description (Sheet 3 of 7) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period.
Intel® Celeron® Processor in the 478-Pin Package Table 32. Signal Description (Sheet 4 of 7) Name Type Description The following are the DSTBP data strobes that are used to latch D[63:0]#: Signals Associated Strobe D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# DSTBP[3:0]# Input/ Output FERR# Output FERR# (Floating-point Error) is asserted when the processor detects an unmasked floating-point error.
Intel® Celeron® Processor in the 478-Pin Package Table 32. Signal Description (Sheet 5 of 7) Name LINT[1:0] Type Input Description LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous.
Intel® Celeron® Processor in the 478-Pin Package Table 32. Signal Description (Sheet 6 of 7) Name RESET# Type Input Description Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks.
Intel® Celeron® Processor in the 478-Pin Package Table 32. Signal Description (Sheet 7 of 7) Name Description TESTHI[12:8] TESTHI[5:0] Input TESTHI[12:8] and TESTHI[5:0] must be connected to a VCC power source through a resistor for proper processor operation. See Section 2.4 for more details. THERMDA Other Thermal Diode Anode. See Section 7.3.1. THERMDC Other Thermal Diode Cathode. See Section 7.3.1.
Intel® Celeron® Processor in the 478-Pin Package 6.0 Thermal Specifications and Design Considerations The Celeron processor in the 478-pin package uses an integrated heat spreader (IHS) for heatsink attachment that is intended to provide for multiple types of thermal solutions. This section provides data necessary for development of a thermal solution. See Figure 30 for an exploded view of an example thermal solution for the Celeron processor in the 478-pin package. This is for illustration purposes.
Intel® Celeron® Processor in the 478-Pin Package 6.1 Thermal Specifications Table 33 specifies the thermal design power dissipation envelope for the Celeron processor in the 478-pin package. Analysis indicates that real applications are unlikely to cause the processor to consume the maximum possible power consumption. Intel recommends that system thermal designs target the “Thermal Design Power” indicated in Table 33 instead of “Max Processor Power.” The Thermal Monitor feature (refer to Section 7.
Intel® Celeron® Processor in the 478-Pin Package 6.2 Thermal Analysis 6.2.1 Thermal Solution Performance Refer to the Intel® Pentium® 4 Processor in the 478-pin Package Thermal Design Guidelines. 6.2.2 Measurements For Thermal Specifications 6.2.2.1 Processor Case Temperature Measurement The maximum and minimum case temperatures (TC) for the Celeron processor in the 478-pin package are specified in Table 33.
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Intel® Celeron® Processor in the 478-Pin Package 7.0 Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Celeron processor in the 478-pin package samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 34. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Intel® Celeron® Processor in the 478-Pin Package The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Power Down state, the processor will process bus snoops. Figure 32. Stop Clock State Machine HALT Instruction and HALT Bus Cycle Generated 2. Auto HALT Power Down State BCLK running. Snoops and interrupts allowed.
Intel® Celeron® Processor in the 478-Pin Package 7.2.3 Stop-Grant State—State 3 When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state.
Intel® Celeron® Processor in the 478-Pin Package 7.2.5 Sleep State—State 5 The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state.
Intel® Celeron® Processor in the 478-Pin Package 7.3 Thermal Monitor The Thermal Monitor feature found in the Celeron processor in the 478-pin package allows system designers to design lower cost thermal solutions without compromising system integrity or reliability.
Intel® Celeron® Processor in the 478-Pin Package If automatic mode is disabled the processor will be operating out of specification and cannot be guaranteed to provide reliable results. Regardless of enabling of the automatic or On-Demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 135 °C.
Intel® Celeron® Processor in the 478-Pin Package 8.0 Boxed Processor Specifications The Celeron processor in the 478-pin package will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from motherboards and standard components. The boxed Celeron processor in the 478-pin package will be supplied with a cooling solution.
Intel® Celeron® Processor in the 478-Pin Package 8.1 Mechanical Specifications 8.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Celeron processor in the 478-pin package. The boxed processor will be shipped with an unattached fan heatsink. Figure 33 shows a mechanical representation of the boxed Celeron processor in the 478-pin package. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Intel® Celeron® Processor in the 478-Pin Package Figure 35. Top View Space Requirements for the Boxed Processor 8.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 6.0 and the Intel® Pentium® 4 Processor in the 478-pin Package Thermal Design Guidelines for details on the processor weight and heatsink requirements. 8.1.
Intel® Celeron® Processor in the 478-Pin Package The target load applied by the clips to the processor heat spreader for Intel’s reference design is 75 ± 15 lbf (maximum load is constrained by the package load capability). It is normal to observe a bow or bend in the board due to this compressive load on the processor package and socket. The level of bow or bend depends on the motherboard material properties and component layout.
Intel® Celeron® Processor in the 478-Pin Package Table 37. Fan Heatsink Power and Signal Specifications Description Min Typ Max +12 V: 12 volt fan power supply 10.2 12 13.8 V 740 mA IC: Fan current draw SENSE: SENSE frequency 2 Unit pulses per fan revolution Notes see note NOTE: Motherboard should pull this pin up to VCC with a resistor. Figure 37.
Intel® Celeron® Processor in the 478-Pin Package 8.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor. 8.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor’s temperature specification is also function of the thermal design of the entire system, and ultimately the responsibility of the system integrator.
Intel® Celeron® Processor in the 478-Pin Package Figure 39. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View) 8.3.2 Variable Speed Fan The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
Intel® Celeron® Processor in the 478-Pin Package Table 38. Boxed Processor Fan Heatsink Set Points Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed Notes 33 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. 40 When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
Intel® Celeron® Processor in the 478-Pin Package 9.0 Debug Tools Specifications Refer to the ITP700 Debug Port Design Guide and the appropriate Platform Design Guide for information regarding debug tools specifications. 9.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Celeron processor in the 478-pin package systems.
Intel® Celeron® Processor in the 478-Pin Package 98 Datasheet
Intel® Celeron® Processor in the 478-Pin Package, Rev 0.8 1.0 1.1 1.2 Introduction......................................................................................................................... 9 Terminology .......................................................................................................... 9 1.1.1 Processor Packaging Terminology ........................................................ 10 References ..........................................................................
8Intel® Celeron® Processor in the 478-Pin Package, Rev 0.8 6.2.2 7.0 7.1 7.2 7.3 8.0 8.1 8.2 8.3 9.0 9.1 100 Measurements For Thermal Specifications ............................................81 6.2.2.1 Processor Case Temperature Measurement.............................81 Features ........................................................................................................................... 83 Power-On Configuration Options.................................................................
Intel® Celeron® Processor in the 478-Pin Package, Rev 0.8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 10336 Typical Vcciopll, Vcca and Vssa Power Distribution........................................... 16 Phase Lock Loop (PLL) Filter Requirements...................................................... 17 Vcc Static and Transient Tolerance.................................................................... 24 AC Test Circuit.................
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Intel® Celeron® Processor in the 478-Pin Package, Rev 0.8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 10336 Reference Documents ........................................................................................ 11 Voltage Identification Definition .......................................................................... 15 System Bus Pin Groups......................................................................................
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