R Intel® Celeron® Processor in the 478-Pin Package Specification Update October 2006 Notice: The Intel® Celeron® Processor in the 478-Pin Package may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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R Contents Revision History .................................................................................................................. 4 Preface ................................................................................................................................ 6 Summary Tables of Changes ............................................................................................. 8 General Information .....................................................................................
Revision History R Revision History Version 4 Description Date -001 Initial release. May 2002 -002 Added erratum AC35. Added Documentation Changes AC4- AC5. Updated processor identification information table. June 2002 -003 Added erratum AC37. Added Documentation Changes AC3- AC12. July 2002 ® ® September 2002 -004 Updated with Intel Celeron Processor on 0.13 Micron Process and in the 478-Pin Package. Added erratum AC38. Updated Erratum AC17. Added Documentation Changes AC3- AC24.
Revision History R Version Description Date -023 Added Erratum AC65 December 2004 -024 • Added specification clarification AC1. April 2005 -025 • Changed the Errata ID tag from “V” to “AC”. Updated Summary table of changes. Updated Microcode Update Guide and .PDB file guide. Added Erratum AC66. October 2005 -026 • Updated erratum AC40. January 2006 -027 • Updated document numbers for Software Developers Manuals. -028 • Added erratum AC67 and AC68. Updated Summary Table of Changes.
Preface R Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface R Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number Errata are design defects or errors. Errata may cause the Intel® Celeron® processor in the 478-pn package behavior to deviate from published specifications.
Summary Tables of Changes R Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications, or Documentation Changes that apply to the listed component steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes R Note: Each Specification Update item is prefixed with a capital letter to distinguish the product.
Summary Tables of Changes R 10 NO.
Summary Tables of Changes R NO.
Summary Tables of Changes R NO.
Summary Tables of Changes R NO. E0 nC1 nD1 Plans AC69 X X X NoFix NO. E0 nC1 nD1 ERRATA Debug Status Register (DR6) Breakpoint Condition Detected Flags May be set Incorrectly SPECIFICATION CHANGES No update for this Month NO. E0 nC1 nD1 SPECIFICATION CLARIFICATIONS No Update for this month. NO.
General Information R General Information This section contains top marking information for the Intel® Celeron® processor in the 478-pn package. Figure 1. Example Markings for the Intel® Celeron® Processor on 0.13 Micron Process and/or in the 478-Pin Package S-Spec/Country of Assy FPO -2-D Matrix Mark i m © ‘03 Celeron® 2A GHZ/512/400/1.
Component Identification Information R Component Identification Information The Intel® Celeron® processor in the 478-pn package processor may be identified by the following values. 1 2 3 Family Model Brand 1111b 0001b 00001010b 1111b 0010b 00001010b NOTES: 1.
Component Identification Information R Table 1. Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information 16 S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature SL6RV C1 128K 0F27h 2 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.0 4, 8, 9 SL6VR D1 128K 0F29h 2 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.0 4, 8, 9 SL6VY D1 128K 0F29h 2 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.0 2, 4, 8 SL6RT C1 128K 0F27h 2.10 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.
Component Identification Information R Table 1. Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature SL6W2 D1 128K 0F29h 2.20 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.0 2, 6, 8 SL6XJ C1 128K 0F27h 2.30 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.0 6, 8 SL6WC D1 128K 0F29h 2.30 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.0 6, 8, 9 SL6WD D1 128K 0F29h 2.30 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.
Component Identification Information R Table 1. Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature SL6VV C1 128K 0F27h 2.60 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.0 8, 11 SL77U D1 128K 0F29h 2.70 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.0 2, 8 SL77S D1 128K 0F29h 2.70 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.0 8 SL77T D1 128K 0F29h 2.80 GHz/ 400 MHz FC-PGA2 31.0 mm , rev 1.
Errata R Errata AC1. I/O Restart in SMM May Fail after Simultaneous Machine Check Exception (MCE) Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the processor will signal a Machine Check Exception (MCE). If the instruction is directed at a device that is powered down, the processor may also receive an assertion of SMI#.
Errata R AC3. Uncacheable (UC) Code in Same Line As Write Back (WB) Data May Lead to Data Corruption Problem: When both code (being accessed as UC or WC) and data (being accessed as WB) are aliased into the same cache line, the UC fetch will cause the processor to self-snoop and generate an implicit writeback. The data supplied by this implicit writeback may be corrupted due to the way the processor handles self-modifying code.
Errata R AC6. FSW May Not Be Completely Restored after Page Fault on FRSTOR or FLDENV Instructions Problem: If the FPU operating environment or FPU state (operating environment and register stack) being loaded by an FLDENV or FRSTOR instruction wraps around a 64-Kbyte or 4-Gbyte boundary and a page fault (#PF) or segment limit fault (#GP or #SS) occurs on the instruction near the wrap boundary, the upper byte of the FPU status word (FSW) might not be restored.
Errata R AC9. Processor May Hang Due to Speculative Page Walks to Non-Existent System Memory Problem: A load operation that misses the Data Translation Lookaside Buffer (DTLB) will result in a pagewalk. If the page-walk loads the Page Directory Entry (PDE) from cacheable memory and that PDE load returns data that points to a valid Page Table Entry (PTE) in uncacheable memory the processor will access the address referenced by the PTE.
Errata R AC12. Performance Counter May Contain Incorrect Value after Being Stopped Problem: If a performance counter is stopped on the precise internal clock cycle where the intermediate carry from the lower 32 bits of the counter to the upper eight bits occurs, the intermediate carry is lost. Implication: When this erratum occurs, the performance counter will contain a value about 4 billion (232) less than it should.
Errata R AC15. Debug Mechanisms May Not Function As Expected Problem: Certain debug mechanisms may not function as expected on the processor.
Errata R AC16. Machine Check Architecture Error Reporting and Recovery May Not Work As Expected Problem: When the processor detects errors it should attempt to report and/or recover from the error. In the situations described below, the processor does not report and/or recover from the error(s) as intended. • When a transaction is deferred during the snoop phase and subsequently receives a Hard Failure response, the transaction should be removed from the bus queue so that the processor may proceed.
Errata R AC17. Processor May Timeout Waiting for a Device to Respond after 0.67 Seconds Problem: The PCI 2.1 target initial latency specification allows two seconds for a device to respond during initialization-time. The processor may timeout after only approximately 0.67 seconds. When the processor times out it will hang with IERR# asserted. PCI devices that take longer than 0.67 seconds to initialize may not be initialized properly. Implication: System may hang with IERR# asserted.
Errata R AC19. IA32_MC1_STATUS MSR ADDRESS VALID Bit May Be Set When No Valid Address Is Available Problem: The processor should only log the address for L1 parity errors in the IA32_MC1_STATUS MSR if a valid address is available. If a valid address is not available, the ADDRESS VALID bit in the IA32_MC1_STATUS MSR should not be set.
Errata R AC22. SQRTPD and SQRTSD May Return QNaN Indefinite Instead of Negative Zero Problem: When DAZ mode is enabled, and a SQRTPD or SQRTSD instruction has a negative denormal operand, the instruction will return a QNaN indefinite when the specified response should be a negative zero. Implication: When this erratum occurs, the instruction will return a QNaN indefinite when a negative zero is expected.
Errata R AC24. Write Combining (WC) Load May Result in Unintended Address on System Bus Problem: When the processor performs a speculative write combining (WC) load, down the path of a mispredicted branch, and the address happens to match a valid UnCacheable (UC) address translation with the Data Translation Look-Aside Buffer, an unintended UnCacheable load operation may be sent out on the system bus. Implication: When this erratum occurs, an unintended load may be sent on system bus.
Errata R AC27. Processor Issues Inconsistent Transaction Size Attributes for Locked Operation Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8-byte load lock onto the system bus. A subsequent 8-byte store unlock is expected, but instead a 4-byte store unlock occurs.
Errata R AC30. When the Processor Is in the System Management Mode (SMM), Debug Registers May Be Fully Writeable Problem: When in System Management Mode (SMM), the processor executes code and stores data in the SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the processor should block writes to the reserved bit locations. Due to this erratum, the processor may not block these writes. This may result in invalid data in the reserved bit locations.
Errata R AC33. CR2 May Be Incorrect or an Incorrect Page Fault Error Code May Be Pushed onto Stack after Execution of an LSS Instruction Problem: Under certain timing conditions, the internal load of the selector portion of the LSS instruction may complete with potentially incorrect speculative data before the load of the offset portion of the address completes.
Errata R AC36. L2 Cache May Contain Stale Data in the Exclusive State Problem: If a cacheline (A) is in Modified (M) state in the write-combining (WC) buffers and in the Invalid (I) state in the L2 cache and its adjacent sector (B) is in the Invalid (I) state and the following scenario occurs: 1. A read to B misses in the L2 cache and allocates cacheline B and its associated second-sector pre-fetch into an almost full bus queue, 2.
Errata R AC38. Glitches on Address or Data Strobe Signals May Cause System Shutdown Problem: When a Machine Check Exception is generated due to a glitch on the address or data strobe signals, the exception may be reported repeatedly, resulting in system shutdown. Implication: If a glitch occurs on the address or data strobe signals, an operating system shutdown will occur if Machine Check Exceptions (MCE) are enabled. IERR# assertion and shutdown will occur if MCE is disabled.
Errata R AC41. Store to Load Data Forwarding may Result in Switched Data Bytes Problem: If in a short window after an instruction that updates a segment register has executed, but has not yet retired, there is a load occurring to an address, that matches a recent previous store operation, but the data size is smaller than the size of the store, the resulting data forwarded from the store to the load may have some of the lower bytes switched.
Errata R AC44. Re-Mapping the APIC Base Address to a Value Less Than or Equal to 0xDC001000 May Cause IO and Special Cycle Failure Problem: Remapping the APIC base address from its default can cause conflicts with either I/O or special cycle bus transactions. Implication: Either I/O or special cycle bus transactions can be redirected to the APIC, instead of appearing on the front-side bus. Workaround: Use any APIC base addresses above 0xDC001000 as the relocation address.
Errata R AC47. Changes to CR3 Register Do Not Fence Pending Instruction Page Walks Problem: When software writes to the CR3 register, it is expected that all previous/outstanding code, data accesses and page walks are completed using the previous value in CR3 register. Due to this erratum, it is possible that a pending instruction page walk is still in progress, resulting in an access (to the PDE portion of the page table) that may be directed to an incorrect memory address.
Errata R AC50. Memory Type of the Load Lock Different from Its Corresponding Store Unlock Problem: A use-once protocol is employed to ensure that the processor in a multi-agent system may access data that is loaded into its cache on a Read-for-Ownership operation at least once before it is snooped out by another agent. This protocol is necessary to avoid a multi-agent livelock scenario in which the processor cannot gain ownership of a line and modify it before that data is snooped out by another agent.
Errata R AC53. PWRGOOD and TAP Signals Maximum Input Hysteresis Higher Than Specified Problem: The maximum input hysteresis for the PWRGOOD and TAP input signals is specified at 350 mV. The actual value could be as high as 800 mV. Implication: The PWRGOOD and TAP inputs may switch at different levels than previously documented specifications. Intel has not observed any issues in validation or simulation as a result of this erratum. Workaround: None identified.
Errata R AC56. A Timing Marginality in the Instruction Decoder Unit May Cause an Unpredictable Application Behavior and/or System Hang Problem: A timing marginality may exist in the clocking of the instruction decoder unit which leads to a circuit slowdown in the read path from the Instruction Decode PLA circuit. This timing marginality may not be visible for some period of time.
Errata R AC59. Machine Check Exceptions May Not Update Last-Exception Record MSRs (LERs) Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine Check Exceptions occur. Implication: When this erratum occurs, the LER may not contain information relating to the machine check exception. They will contain information relating to the exception prior to the machine check exception. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.
Errata R AC62. With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP Exception May Take Single Step Trap before Retirement of Instruction Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for external events to occur, including a transition to a lower power state. When resuming from the lower power state, it may be possible to take the single step trap before the execution of the original FP instruction completes.
Errata R and BLW transactions, or (2) all HITM snoop results without regard to the transaction type and snoop results’ source. Workaround: 1. The central agent can issue a bus cycle that causes a cache line to be invalidated (Bus Read Invalidate Line (BRIL) or BWIL transaction) in response to a processor-generated BWIL (or BLW) transaction to insure complete invalidation of the associated cache line.
Errata R AC67. Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero) to emulates real-address mode address wraparound at 1 megabyte. However, if all of the following conditions are met, address bit 20 may not be masked.
Errata R • Implication: Any debug register access ("MOV DRx, r32" or "MOV r32, DRx") results in a general-detect exception condition. Due to this erratum the breakpoint condition detected flags may be set incorrectly. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.
Specification Changes R Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Celeron® Processor in the 478-Pin Package Datasheet • Intel® 64 and IA-32 Intel® Architectures Software Developer’s Manual, Volumes 1, 2-A, 2B, 3-A, and 3-B All Specification Changes will be incorporated into a future version of the appropriate Celeron processor documentation.
Specification Clarifications R Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel® Celeron® Processor in the 478-Pin Package Datasheet • Intel® 64 and IA-32 Intel® Architectures Software Developer’s Manual, Volumes 1, 2-A, 2B, 3-A, and 3-B All Specification Clarifications will be incorporated into a future version of the appropriate Celeron processor documentation. 1.
Specification Clarifications R internal processor clock cycle is determined by the current core-clock to bus-clock ratio. Intel® SpeedStep® technology transitions may also impact the processor clock. • For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]): the time-stamp counter increments at a constant rate. That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by the frequency at which the processor is booted.
Specification Clarifications R • The processor is asleep as a result of being halted or because of a power-management scheme. There are different levels of sleep. In the some deep sleep levels, the time-stamp counter stops counting. There are three ways to count processor clock cycles to monitor performance. These are: • Non-halted clockticks — Measures clock cycles in which the specified logical processor is not halted and is not in any power-saving state.
Documentation Changes R Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Celeron® Processor in the 478-Pin Package Datasheet • Intel® 64 and IA-32 Intel® Architectures Software Developer’s Manual, Volumes 1, 2-A, 2B, 3-A, and 3-B All Documentation Changes will be incorporated into a future version of the appropriate Celeron processor documentation.
