Intel® Celeron® Mobile Processor Dual-Core on 45-nm Process Datasheet For Platforms Based on Mobile Intel® 4 Series Express Chipset Family September 2009 Document Number: 321111-003
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Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 8 1.2 References ......................................................................................................... 9 2 Low Power Features ................................................................................................ 11 2.
Figures 1 2 3 4 5 6 Package-Level Low-Power States ................................................................................11 Core Low-Power States .............................................................................................12 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) .................30 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) .................31 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ...............
Revision History Document Number Revision Number 321111 -001 • Initial Release November 2008 321111 -002 • Added T3000, T3100, T3300, and T3500 processors June 2009 Description Date • Added specifications for SFF processor SU2300 • Added C4 state support information for SU2300 SFF processor • Added Speedstep technology suppport information for SU2300 SFF processor • details: • Chapter 1: updated feature list for SFF processor • Section 2.
Datasheet
Introduction 1 Introduction This document provides electrical, mechanical, and thermal specifications for the Intel® Celeron® Mobile Processor Dual-Core T1x00, Intel(R) Celeron Processors T3x00 and Intel(R) Celeron Dual-core SFF Processors. The processor supports the Mobile Intel® 4 Series Express Chipset and Intel® 82801IBM (ICH9M) Controller-Hub Based Systems.
Introduction 1.1 Terminology Term 8 Definition # A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Datasheet Document Document Number Intel® Celeron® Dual-Core T1x00 Processors Specification Update for Platforms Based on Mobile Intel® 4 Series Express Chipset Family See http:// www.intel.com/design/ mobile/specupdt/ 319734.
Introduction 10 Datasheet
Low Power Features 2 Low Power Features 2.1 Clock Control and Low Power States The processor supports the C1/AutoHALT, C1/MWAIT, C2, C3 and some support the C4 core low-power states, along with their corresponding package-level states for power management. See Chapter 3 to see if C4 is supported. These package states include Normal, Stop Grant, Stop Grant Snoop, Sleep, and Deep Sleep.
Low Power Features Figure 2.
Low Power Features 2.1.1.3 C1/MWAIT Powerdown State C1/MWAIT is a low-power state entered when the processor core executes the MWAIT instruction. Processor behavior in the C1/MWAIT state is identical to the C1/AutoHALT state except that there is an additional event that can cause the processor core to return to the C0 state: the Monitor event. See the Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 2A/2B: Instruction Set Reference for more information. 2.1.1.
Low Power Features Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# causes the processor to immediately initialize itself, but the processor stays in Stop-Grant state.
Low Power Features 2.1.2.5 Deep Sleep State Deep Sleep state is a very low-power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings.
Low Power Features • The processor controls voltage ramp rates internally to ensure glitch-free transitions. • Low transition latency and large number of transitions possible per second: — Processor core (including L2 cache) is unavailable for up to 10 μs during the frequency transition. — The bus protocol (BNR# mechanism) is used to block snooping.
Low Power Features 2.4 Processor Power Status Indicator (PSI#) Signal The PSI# signal is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the processor uses for determining when to assert PSI# is different from the algorithm used in previous processors.
Low Power Features 18 Datasheet
Electrical Specifications 3 Electrical Specifications 3.1 Power and Ground Pins For clean, on-chip power distribution, the processor has a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.
Electrical Specifications Table 2. 20 Voltage Identification Definition (Sheet 2 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 0 1 0 1 1 0 1.2250 0 0 1 0 1 1 1 1.2125 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.
Electrical Specifications Table 2. Datasheet Voltage Identification Definition (Sheet 3 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.
Electrical Specifications Table 2. 3.4 Voltage Identification Definition (Sheet 4 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 1 1 0 1 0 0 0.0500 1 1 1 0 1 0 1 0.0375 1 1 1 0 1 1 0 0.0250 1 1 1 0 1 1 1 0.0125 1 1 1 1 0 0 0 0.0000 1 1 1 1 0 0 1 0.0000 1 1 1 1 0 1 0 0.0000 1 1 1 1 0 1 1 0.0000 1 1 1 1 1 0 0 0.0000 1 1 1 1 1 0 1 0.0000 1 1 1 1 1 1 0 0.0000 1 1 1 1 1 1 1 0.
Electrical Specifications 3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the appropriate chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3. Table 3. 3.
Electrical Specifications Table 4. FSB Pin Groups Signal Group Signals1 Type AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#3, DPWR# Signals AGTL+ Source Synchronous I/O Synchronous to assoc.
Electrical Specifications 3.8 CMOS Signals CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for more than four BCLKs in order for the processor to recognize them. See Section 3.10 for the DC specifications for the CMOS signal groups. 3.
Electrical Specifications 3.10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and signal pin assignments. Table 7 through Table 10 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages.
Electrical Specifications Table 6. DC Voltage and Current Specifications for the T3x00 Celeron Processors Symbol Parameter Min VCC VCC of the Processor Core VCC,BOOT Default VCC Voltage for Initial Power Up VCCP AGTL+ Termination Voltage VCCA PLL Supply Voltage ICCDES Typ 0.8 ICC for processors Recommended Design Targets: Max Unit Notes 1.25 V 1, 2 V 2, 8 1.20 1.00 1.05 1.10 V 1.425 1.5 1.575 V 47 A ICC for processors Processor 5 A Frequency Die Variant T3000 1.
Electrical Specifications Table 7. DC Voltage and Current Specifications for the T1x00 Celeron Mobile Processors Symbol Parameter VCC VCC of the Processor Core VCC,BOOT Default VCC Voltage for Initial Power Up VCCP AGTL+ Termination Voltage VCCA PLL Supply Voltage ICCDES ICC for processors Recommended Design Targets: Min Typ Max Unit Notes 0.95 1.15 1.30 V 1, 2 V 2, 8 1.20 1.00 1.05 1.10 V 1.425 1.5 1.
Electrical Specifications Table 8 lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest and lowest core operating frequencies supported on the Genuine Intel Processor. Unless specified otherwise, all specifications for the processor are at Tjunction =100 ºC.
Electrical Specifications 5. 6. 7. 8. 9. 10. 800-MHz FSB supported Measured at the bulk capacitors on the motherboard. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. This is a power-up peak current specification, which is applicable when VCCP is high and VCC core is low. This is a steady-state Icc current specification, which is applicable when both VCCP and VCC core are high.
Electrical Specifications Table 10. AGTL+ Signal Group DC Specifications Symbol VCCP GTLREF RCOMP RODT Parameter I/O Voltage Typ Max Unit 1.00 1.05 1.10 V V 6 27.78 Ω 10 Ω 11 Reference Voltage Compensation Resistor Notes1 Min 2/3 VCCP 27.23 Termination Resistor 27.5 55 VIH Input High Voltage GTLREF+0.10 VCCP VCCP+0.10 V 3,6 VIL Input Low Voltage -0.10 0 GTLREF-0.10 V 2,4 VOH Output High Voltage VCCP-0.
Electrical Specifications Table 11. CMOS Signal Group DC Specifications Symbol VCCP Parameter I/O Voltage Min Typ Max Unit 1.00 1.05 1.10 V Notes1 VIH Input High Voltage 0.7*VCCP VCCP VCCP+0.1 V 2 VIL Input Low Voltage CMOS -0.10 0.00 0.3*VCCP V 2 VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2 VOL Output Low Voltage -0.10 0 0.1*VCCP V 2 IOH Output High Current 1.5 4.1 mA 5 IOL Output Low Current 1.5 4.
Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information 4.1 Package Mechanical Specifications The processor is available in a 1-MB, 478-pin Micro-FCPGA package. The package mechanical dimensions, keep-out zones, processor mass specifications, and package loading specifications are shown in Figure 3 through Figure 6. The SFF processor (ULV DC) is available 956-ball Micro-FCBGA packages. The package mechanical dimensions are shown in Figure 7.
Package Mechanical Specifications and Pin Information Figure 3. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) h Bottom View Top View Front View Side View & ' %( ! "# $% $ ) P Detail A 34 + ,- 1--1 .0.2 1/ * * * * 1 1 1 1 1 1 )1.
Package Mechanical Specifications and Pin Information Figure 4. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) "# $ %& ' Side View ( ( $ %& ' Top View ø0.305±0.25 ø0.406 M C A B ø0.
Package Mechanical Specifications and Pin Information Figure 5. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) Bottom View Top View Front View Side View & ' %( ! "# $% $ ) P Detail A 36 + , 1--1 .0.2 1/ * * , .
Package Mechanical Specifications and Pin Information Figure 6. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) "# $ %& ' Side View ( ( $ %& ' Top View ø0.305±0.25 ø0.406 M C A B ø0.
: FRONT VIEW TOP VIEW ! "#$%& %! '()* +,-!&./00 A /! DETAIL SIDE VIEW B DETAIL 2 3 ; 4 : 1 3 ; 4 : 1 8 + 6 2 8 + 6 2 (Solder Resist Opening) ø0.39±0.02 (Metal Diameter) BOTTOM VIEW ø0.46±0.
Package Mechanical Specifications and Pin Information 4.2 Processor Pinout and Pin List Table 13 shows the top view pinout of the Intel Celeron Dual-Core processor. The pin list, arranged in two different formats, is shown in the following pages. Table 13.
Package Mechanical Specifications and Pin Information Table 14.
Package Mechanical Specifications and Pin Information Table 15.
Package Mechanical Specifications and Pin Information Table 16.
Package Mechanical Specifications and Pin Information Table 17.
Package Mechanical Specifications and Pin Information Table 18.
Package Mechanical Specifications and Pin Information Table 19. Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Name (Sheet 3 of 16) Pin Number Signal Buffer Type Direction BR0# F1 Common Clock Input/ Output BSEL[0] B22 CMOS Output BSEL[1] B23 CMOS Output BSEL[2] C21 CMOS COMP[0] R26 COMP[1] Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Name (Sheet 5 of 16) Pin Number Signal Buffer Type Direction D[37]# T22 Source Synch Input/ Output D[38]# U25 Source Synch D[39]# U23 D[40]# Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Name (Sheet 7 of 16) Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Name (Sheet 9 of 16) Pin Number Signal Buffer Type VCC AA13 Power/Other VCC AA15 VCC Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Name (Sheet 11 of 16) Pin Number Signal Buffer Type VCC E12 Power/Other VCC E13 VCC Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Name (Sheet 13 of 16) Pin Number Signal Buffer Type VSS AC14 Power/Other VSS AC16 VSS Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Name (Sheet 15 of 16) Pin Number Signal Buffer Type VSS F16 Power/Other VSS F19 VSS F22 Pin Name Table 19.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Number (Sheet 2 of 17) Pin Number Signal Buffer Type VSS A8 Power/Other VCC A9 VCC A10 Pin Name Table 20.
Package Mechanical Specifications and Pin Information Table 20.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Number (Sheet 6 of 17) Pin Number Signal Buffer Type Direction VID[2] AE5 CMOS Output PSI# AE6 CMOS VSSSENSE AE7 Power/Other Pin Name Table 20.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Number (Sheet 8 of 17) Pin Number Signal Buffer Type Direction BSEL[0] B22 CMOS Output BSEL[1] B23 CMOS Output VSS B24 Pin Name Table 20.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Number (Sheet 10 of 17) Pin Number Signal Buffer Type VCC E12 Power/Other VCC E13 VSS Table 20.
Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Number (Sheet 12 of 17) Pin Number Signal Buffer Type VSS H6 Power/Other VSS H21 Power/Other D[12]# H22 Source Synch Pin Name Direction Input/ Output Input/ Output D[15]# H23 Source Synch VSS H24 Power/Other DINV[0]# H25 Source Synch Input/ Output Table 20.
Package Mechanical Specifications and Pin Information Table 20.
Package Mechanical Specifications and Pin Information Table 20.
Package Mechanical Specifications and Pin Information Table 21.
Package Mechanical Specifications and Pin Information Ball Number Signal Name Ball Number D[20]# R41 D[58]# BC35 D[21]# W41 D[59]# BC39 D[22]# N43 D[60]# BA41 D[23]# U41 D[61]# BB40 D[24]# AA41 D[62]# BA35 D[25]# AB40 D[63]# AU43 D[26]# AD40 DBR# J7 D[27]# AC41 DBSY# J1 D[28]# AA43 DEFER# N5 D[29]# Y40 DINV[0]# P40 D[30]# Y44 DINV[1]# R43 D[31]# T44 DINV[2]# AJ41 D[32]# AP44 DINV[3]# BC37 D[33]# AR43 DPRSTP# G7 D[34]# AH40 DPSLP# B8 D[35]# AF4
Package Mechanical Specifications and Pin Information Signal Name Ball Number Signal Name Ball Number PSI# BD10 VCC AB18 PWRGOOD E7 VCC AB20 REQ[0]# R1 VCC AB22 REQ[1]# R5 VCC AB24 REQ[2]# U1 VCC AB26 REQ[3]# P4 VCC AB28 REQ[4]# W5 VCC AB30 RESET# G5 VCC AB32 RS[0]# K2 VCC AC33 RS[1]# H4 VCC AD16 RS[2]# K4 VCC AD18 RSVD01 V2 VCC AD20 RSVD02 Y2 VCC AD22 RSVD03 AG5 VCC AD24 RSVD04 AL5 VCC AD26 RSVD05 J9 VCC AD28 RSVD06 F4 VCC AD30 RSVD07
Package Mechanical Specifications and Pin Information Ball Number Signal Name Ball Number VCC AJ33 VCC AT24 VCC AK16 VCC AT26 VCC AK18 VCC AT28 VCC AK20 VCC AT30 VCC AK22 VCC AT32 VCC AK24 VCC AT34 VCC AK26 VCC AU33 VCC AK28 VCC AV14 VCC AK30 VCC AV16 VCC AK32 VCC AV18 VCC AL33 VCC AV20 VCC AM14 VCC AV22 VCC AM16 VCC AV24 VCC AM18 VCC AV26 VCC AM20 VCC AV28 VCC AM22 VCC AV30 VCC AM24 VCC AV32 VCC AM26 VCC AY14 VCC AM28 VCC AY16
Package Mechanical Specifications and Pin Information Signal Name Ball Number Signal Name Ball Number VCC BB20 VCC H22 VCC BB22 VCC H24 VCC BB24 VCC H26 VCC BB26 VCC H28 VCC BB28 VCC H30 VCC BB30 VCC H32 VCC BB32 VCC J33 VCC BD14 VCC K16 VCC BD16 VCC K18 VCC BD18 VCC K20 VCC BD20 VCC K22 VCC BD22 VCC K24 VCC BD24 VCC K26 VCC BD26 VCC K28 VCC BD28 VCC K30 VCC BD30 VCC K32 VCC BD32 VCC L33 VCC D16 VCC M16 VCC D18 VCC M18 VCC D20
Package Mechanical Specifications and Pin Information Signal Name Ball Number Signal Name Ball Number VCC T18 VCCP AB10 VCC T20 VCCP AB12 VCC T22 VCCP AB14 VCC T24 VCCP AB36 VCC T26 VCCP AB38 VCC T28 VCCP AC7 VCC T30 VCCP AC9 VCC T32 VCCP AC11 VCC U33 VCCP AC13 VCC V16 VCCP AC35 VCC V18 VCCP AC37 VCC V20 VCCP AD14 VCC V22 VCCP AE7 VCC V24 VCCP AE9 VCC V26 VCCP AE11 VCC V28 VCCP AE13 VCC V30 VCCP AE35 VCC V32 VCCP AE37 VCC W33 VCC
Package Mechanical Specifications and Pin Information Signal Name Ball Number Signal Name Ball Number VCCP AK14 VCCP F14 VCCP AK36 VCCP F34 VCCP AK38 VCCP F36 VCCP AL7 VCCP G11 VCCP AL9 VCCP G13 VCCP AL11 VCCP G35 VCCP AL13 VCCP H12 VCCP AL35 VCCP H14 VCCP AL37 VCCP H36 VCCP AN7 VCCP J11 VCCP AN9 VCCP J13 VCCP AN11 VCCP J35 VCCP AN13 VCCP J37 VCCP AN35 VCCP K10 VCCP AN37 VCCP K12 VCCP AP10 VCCP K14 VCCP AP12 VCCP K36 VCCP AP36 VCCP
Package Mechanical Specifications and Pin Information Signal Name Ball Number Signal Name Ball Number VCCP R11 VSS A21 VCCP R13 VSS A23 VCCP R35 VSS A25 VCCP R37 VSS A27 VCCP T14 VSS A29 VCCP U7 VSS A31 VCCP U9 VSS A39 VCCP U11 VSS A41 VCCP U13 VSS AA3 VCCP U35 VSS AA15 VCCP U37 VSS AA17 VCCP V10 VSS AA19 VCCP V12 VSS AA21 VCCP V14 VSS AA23 VCCP V36 VSS AA25 VCCP V38 VSS AA27 VCCP W7 VSS AA29 VCCP W9 VSS AA31 VCCP W11 VSS AA39
Package Mechanical Specifications and Pin Information Ball Number Signal Name Ball Number Signal Name VSS AD34 VSS AJ3 VSS AD36 VSS AJ15 VSS AD38 VSS AJ17 VSS AD42 VSS AJ19 VSS AE3 VSS AJ21 VSS AE15 VSS AJ23 VSS AE17 VSS AJ25 VSS AE19 VSS AJ27 VSS AE21 VSS AJ29 VSS AE23 VSS AJ31 VSS AE25 VSS AJ39 VSS AE27 VSS AK6 VSS AE29 VSS AK8 VSS AE31 VSS AK34 VSS AE39 VSS AK42 VSS AF6 VSS AL3 VSS AF8 VSS AL15 VSS AF34 VSS AL17 VSS AF42 VSS
Package Mechanical Specifications and Pin Information Signal Name Ball Number Signal Name Ball Number VSS AN21 VSS AU23 VSS AN23 VSS AU25 VSS AN25 VSS AU27 VSS AN27 VSS AU29 VSS AN29 VSS AU31 VSS AN31 VSS AU35 VSS AN39 VSS AU37 VSS AP6 VSS AU39 VSS AP8 VSS AV6 VSS AP34 VSS AV12 VSS AP42 VSS AV34 VSS AR3 VSS AV36 VSS AR15 VSS AV42 VSS AR17 VSS AV44 VSS AR19 VSS AW1 VSS AR21 VSS AW3 VSS AR23 VSS AW9 VSS AR25 VSS AW11 VSS AR27 VSS
Package Mechanical Specifications and Pin Information Ball Number Signal Name Ball Number VSS B6 VSS BC41 VSS B36 VSS BD4 VSS B42 VSS BD6 VSS BA1 VSS BD36 VSS BA3 VSS BD38 VSS BA9 VSS BD40 VSS BA11 VSS C3 VSS BA13 VSS C11 VSS BA15 VSS C15 VSS BA17 VSS C17 VSS BA19 VSS C19 VSS BA21 VSS C21 VSS BA23 VSS C23 VSS BA25 VSS C25 VSS BA27 VSS C27 VSS BA29 VSS C29 VSS BA31 VSS C31 VSS BA33 VSS C39 VSS BA39 VSS D2 VSS BA43 VSS D6 VSS
Package Mechanical Specifications and Pin Information Signal Name Ball Number Signal Name Ball Number VSS F44 VSS L21 VSS G1 VSS L23 VSS G3 VSS L25 VSS G9 VSS L27 VSS G15 VSS L29 VSS G17 VSS L31 VSS G19 VSS L39 VSS G21 VSS M6 VSS G23 VSS M8 VSS G25 VSS M10 VSS G27 VSS M12 VSS G29 VSS M34 VSS G31 VSS M36 VSS G37 VSS M38 VSS H6 VSS M42 VSS H10 VSS N3 VSS H34 VSS N15 VSS H38 VSS N17 VSS H42 VSS N19 VSS J3 VSS N21 VSS J15 VSS
Package Mechanical Specifications and Pin Information Signal Name Ball Number Signal Name Ball Number VSS R29 VSS Y6 VSS R31 VSS Y8 VSS R39 VSS Y10 VSS T6 VSS Y12 VSS T8 VSS Y34 VSS T10 VSS Y36 VSS T12 VSS Y38 VSS T34 VSS Y42 VSS T36 VSSSENSE BC13 VSS T38 VSS T42 VSS U3 VSS U5 VSS U15 VSS U17 VSS U19 VSS U21 VSS U23 VSS U25 VSS U27 VSS U29 VSS U31 VSS U39 VSS V6 VSS V8 VSS V34 VSS V42 VSS W3 VSS W15 VSS W17 VSS W19 VSS W21
Package Mechanical Specifications and Pin Information 74 Datasheet
Package Mechanical Specifications and Pin Information 4.3 Alphabetical Signals Reference Table 22. Signal Description (Sheet 1 of 7) Name A[35:3]# A20M# Type Description Input/ Output A[35:3]# (Address) define a 236-byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB.
Package Mechanical Specifications and Pin Information Table 22. Name Signal Description (Sheet 2 of 7) Type Description BSEL[2:0] Output BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency.
Package Mechanical Specifications and Pin Information Table 22. Name Signal Description (Sheet 3 of 7) Type Description DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent inverts the data bus signals if more than half the bits, within the covered group, would change level in the next cycle.
Package Mechanical Specifications and Pin Information Table 22. Name FERR#/PBE# Signal Description (Sheet 4 of 7) Type Output Description FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating point when the processor detects an unmasked floatingpoint error.
Package Mechanical Specifications and Pin Information Table 22. Name LINT[1:0] Signal Description (Sheet 5 of 7) Type Description Input LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Intel® Pentium® processor. Both signals are asynchronous.
Package Mechanical Specifications and Pin Information Table 22. Name Signal Description (Sheet 6 of 7) Type Description RESET# Input Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents deasserts their outputs within two clocks.
Package Mechanical Specifications and Pin Information Table 22. Name Signal Description (Sheet 7 of 7) Type Description Output The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor stops all execution when the junction temperature exceeds approximately 125 °C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin.
Package Mechanical Specifications and Pin Information 82 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features.
Thermal Specifications and Design Considerations 3. 4. 5. 6. 7. 8. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for details. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. At Tj of 100 oC At Tj of 50 oC At Tj of 35 oC 512-KB L2 cache Table 25.
Thermal Specifications and Design Considerations 5.1.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal diode, with its collector shorted to ground. The thermal diode can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard or a stand-alone measurement kit.
Thermal Specifications and Design Considerations Table 27. Thermal Diode Parameters Using Diode Model Symbol IFW Parameter Min Typ Max Unit Notes 200 µA 1 Ω 2, 3, 5 Forward Bias Current 5 n Diode Ideality Factor 1.000 1.009 1.050 RT Series Resistance 2.79 4.52 6.24 2, 3, 4 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias.
Thermal Specifications and Design Considerations Table 28. Thermal Diode Parameters Using Transistor Model Symbol Parameter Min IFW Forward Bias Current IE Emitter Current nQ Transistor Ideality 5 5 0.997 Beta RT Typ 1.001 0.3 Series Resistance 2.79 4.52 Max Unit Notes 200 μA 1,2 200 μA 1 1.005 3,4,5 0.760 3,4 6.24 Ω 3,6 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 27. 3.
Thermal Specifications and Design Considerations If the ntrim value used to calculate the Toffset differs from the ntrim value used to in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset can be adjusted by calculating nactual and then recalculating the offset using the ntrim as defined in the temperature sensor manufacturer’s datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 29. Table 29. 5.1.
Thermal Specifications and Design Considerations Intel Thermal Monitor 1 and 2 can co-exist within the processor. If both Intel Thermal Monitor 1 and 2 bits are enabled in the auto-throttle MSR, Intel Thermal Monitor 2 takes precedence over Intel Thermal Monitor 1.
Thermal Specifications and Design Considerations Unlike traditional thermal devices, the DTS will output a temperature relative to the maximum supported operating temperature of the processor (TJ,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the DTS will always be at or below TJ,max. Catastrophic temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the DTS MSR.
Thermal Specifications and Design Considerations When PROCHOT# is driven by an external agent, if only Intel Thermal Monitor 1 is enabled on both cores, then both processor cores will have their core clocks modulated. If Intel Thermal Monitor 2 is enabled on both cores, then both processor cores will enter the lowest programmed Intel Thermal Monitor 2 performance state.
Thermal Specifications and Design Considerations 92 Datasheet
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Coordination of Core-Level Low-Power States at the Package Level................................. 11 Voltage Identification Definition ................................................................................ 19 BSEL[2:0] Encoding for BCLK Frequency ..................................................................... 23 FSB Pin Groups.........................................................................................
2 Datasheet
1 2 3 4 5 6 7 Package-Level Low-Power States ............................................................................... 11 Core Low-Power States ............................................................................................. 12 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ................ 34 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ................ 35 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2).....................
2 Datasheet
1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 8 1.2 References ......................................................................................................... 9 2 Low Power Features ................................................................................................ 11 2.
2 Datasheet
