Intel® Celeron® Dual-Core Processor T1x00 Series Specification Update For Platforms Based on Mobile Intel® 965 Express Chipset April 2008 Document Number: 319735-001
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Contents Preface ...............................................................................................................................5 Identification Information ......................................................................................................7 Summary Tables of Changes ................................................................................................10 Errata .......................................................................................................
Revision History Document Number Revision 319735 -001 Description Initial release Date April 2008 § 4 Specification Update
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents and Related Documents tables. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (for example, core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number. QDF Number is a several digit code that is used to distinguish between engineering samples. These processors are used for qualification and early design validation.
Identification Information Identification Information Component Identification via Programming Interface The Intel Celeron Dual-Core processor stepping can be identified by the following register contents: Family1 Model2 Model for A-1 step 0110 1111 10000 NOTES: 1.
Identification Information Component Marking Information Figure 1. Intel® Celeron® Dual-Core Processor (Micro-FCPGA/FCBGA) Sample Markings SAMPLE MARK EXAMPLE: Group 1 Line 1: Unit Identifier* --Group 1 Line 2: FPO QDF# ES Group 2 Line 1: INTEL (m) © ’05 Group 2 Line 2: ATPO Serial Number For Pb-Free: Group 2 Line 1: INTEL (m) © ’05 (e1) * Intel Celeron Dual-Core processors have a unit identifier of LF80537 for Micro-FCPGA parts. Figure 2.
Identification Information Table 1. Intel Celeron Dual-Core Processor – Mobile Intel 965 Express Chipset Family Component Markings QDF#/ S-Spec Processor Number Package Processor Stepping FSB (MHz) Speed HFM/LFM (GHz) Q9AB T1400 Micro-FCBGA M-0 533 1.73 SLAQL T1400 Micro-FCBGA M-0 533 1.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed CPU steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Note: Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates: A = Dual-Core Intel® Xeon® processor 7000 sequence C = Intel® Celeron® processor D = Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor Q6000 sequence AL = Dual-Core Intel® Xeon® processor 7100 series AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® Dual-Core processor AO = Quad-Core Intel® Xeon® processor 3200 series AP = Dual-Core Intel® Xeon® processor 3000 series AQ = Intel® Pentium® Dual-Core Desktop processor E2000 sequence AR = Intel® Celeron® Processor 500 series AS = Intel® Xeon® processor 7200,
Summary Tables of Changes Errata for Intel Celeron Dual Core Processors for Platforms Based on Mobile Intel 965 Express Chipset Family Stepping Stepping Stepping Number Plans ERRATA X No Fix Writing the Local Vector Table (LVT) When an Interrupt Is Pending May Cause an Unexpected Interrupt X X No Fix LOCK# Asserted during a Special Cycle Shutdown Transaction May Unexpectedly Deassert X X X No Fix Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May Be Incorrect
Summary Tables of Changes Stepping Stepping Stepping Number AH19 Plans E-1 M-0 G-0 X X X ERRATA No Fix Code Segment Limit Violation May Occur On 4-GB Limit Check AH20 Fixed FP Inexact-Result Exception Flag May Not Be Set AH21 Fixed Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not Be Flushed by RSM instruction before Restoring the Architectural State from SMRAM AH22 Fixed Sequential Code Fetch to Non-canonical Address May Have Nondeterministic Results AH23 Fixed VM
Summary Tables of Changes Stepping Stepping Stepping Number Plans E-1 M-0 ERRATA G-0 AH39 Fixed Cache Data Access Request from One Core Hitting a Modified Line in the L1 Data Cache of the Other Core May Cause Unpredictable System Behavior AH40 Fixed PREFETCHh Instruction Execution under Some Conditions May Lead to Processor Livelock AH41 Fixed PREFETCHh Instructions May Not Be Executed when Alignment Check (AC) Is Enabled AH42 Fixed Upper 32 Bits of the FPU Data (Operand) Pointer in the FXS
Summary Tables of Changes Stepping Stepping Stepping Number Plans ERRATA E-1 M-0 G-0 AH60 X X X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode AH61 X X X No Fix A Thermal Interrupt Is Not Generated when the Current Temperature Is Invalid AH62 X X X No Fix CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early AH63 AH64 Removed Erratum X X X AH65 No Fix Returning to Real Mode from SMM with
Summary Tables of Changes Stepping Stepping Stepping Number Plans E-1 M-0 ERRATA G-0 AH82 Fixed Debug Register May Contain Incorrect Information on a MOVSS or POPSS Instruction followed by SYSRET AH83 X X X No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled AH84 X X X No Fix Non-Temporal Data Store May Be Observed in Wrong Program Order AH85 X X X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame AH86 X X Fixed
Summary Tables of Changes Stepping Stepping Stepping Number Plans E-1 M-0 ERRATA G-0 AH102 Fixed Performance Monitoring Event BR_INST_RETIRED May Count CPUID Instructions as Branches AH103 X X X No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over Count AH104 X X X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware Fixed False Level One Data Cache Parity Machine-Check Exceptions May Be Signaled AH105 AH106 X X X No Fi
Summary Tables of Changes Stepping Stepping Stepping Number Plans E-1 M-0 ERRATA G-0 Errata Affecting Only Intel Celeron Dual-Core Processor on Mobile Intel 965 Express Chipset Family AH1P X X Plan Fix VM Exit Due to Virtual APIC-Access May Clear RF AH2P X X Fixed VMCALL Failure Due to Corrupt MSEG Location May Cause VM Exit to Load the Machine State Incorrectly AH3P X X Fixed Fixed Function Performance Counters MSR_PERF_FIXED_CTR1 (30AH) and MSR_PERF_FIXED (30BH) Are Not Cleared When the
Errata Errata AH1. Writing the Local Vector Table (LVT) When an Interrupt Is Pending May Cause an Unexpected Interrupt Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set.
Errata AH4. Exception Record (LER) MSRVERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR Problem: The LER MSR may be unexpectedly updated, if the resultant value of the Zero Flag (ZF) is zero after executing the following instructions. 1. VERR (ZF=0 indicates unsuccessful segment read verification) 2. VERW (ZF=0 indicates unsuccessful segment write verification) 3. LAR (ZF=0 indicates unsuccessful access rights load) 4.
Errata AH7. General Protection Fault (#GP) for Instructions Greater Than 15 Bytes May Be Preempted Problem: When the processor encounters an instruction that is greater than 15 bytes in length, a #GP is signaled when the instruction is decoded. Under some circumstances, the #GP fault may be preempted by another lower priority fault (for example, Page Fault (#PF)). However, if the preempting lower priority faults are resolved by the operating system and the instruction retried, a #GP fault will occur.
Errata AH11. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memorybased APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, for example.
Errata AH14. LER MSRs May Be Incorrectly Updated Problem: The LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH) may contain incorrect values after any of the following: • Either STPCLK#, NMI (Non-Maskable Interrupt), or external interrupts • CMP or TEST instructions with an uncacheable memory operand followed by a conditional jump. • STI/POP SS/MOV SS instructions followed by CMP or TEST instructions and then by a conditional jump.
Errata AH16. Performance Monitoring Event for Number of Reference Cycles When the Processor Is Not Halted (3CH) Does Not Count According to the Specification Problem: The CPU_CLK_UNHALTED performance monitor with mask 1 counts bus clock cycles instead of counting the core clock cycles at the maximum possible ratio. The maximum possible ratio is computed by dividing the maximum possible core frequency by the bus frequency.
Errata AH18. Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Problem: Software which is written so that multiple agents can modify the same shared unaligned memory location at the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boundary.
Errata AH20. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is not exactly representable in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally set by the processor. Under certain rare conditions, this bit may not be set when this rounding occurs.
Errata AH21. Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not Be Flushed by RSM instruction before Restoring the Architectural State from SMRAM Problem: The Resume from System Management Mode (RSM) instruction does not flush global pages from the Data Translation Look-Aside Buffer (DTLB) prior to reloading the saved architectural state.
Errata AH24. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations Problem: Under certain conditions as described in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, section Out-of-Order Stores For string operations in Pentium 4, Intel Xeon, and P6 Family Processors, the processor performs REP MOVS or REP STOS as fast strings.
Errata AH26. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur it is possible that the load portion of the instruction is executed before the exception handler is entered. 1. If an instruction that performs a memory load causes a code segment limit violation. 2. If a waiting X87 floating-point (FP) instruction or MMX™ technology instruction that performs a memory load has a floating-point exception pending. 3.
Errata AH28. EIP May Be Incorrect after Shutdown in IA-32e Mode Problem: When the processor is going into shutdown state the upper 32 bits of the instruction pointer may be incorrect. This may be observed if the processor is taken out of shutdown state by NMI#. Implication: A processor that has been taken out of the shutdown state may have an incorrect EIP. The only software which would be affected is diagnostic software that relies on a valid EIP. Workaround: None identified.
Errata AH31.
Errata AH33. Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results Problem: The act of one processor, or system bus master, writing data into a currently executing code segment of a second processor with the intent of having the second processor execute that data as code is called cross-modifying code (XMC). XMC that does not force the second processor to execute a synchronizing instruction, prior to execution of the new code, is called unsynchronized XMC.
Errata AH35. Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64-KB limit while the processor is operating in 16-bit mode or if a memory address exceeds the 4-GB limit while the processor is operating in 32-bit mode.
Errata AH38. FXSAVE/FXRSTOR Instructions Which Store to the End of the Segment and Cause a Wrap to a Misaligned Base Address (Alignment <= 0x10h) May Cause FPU Instruction or Operand Pointer Corruption Problem: If a FXSAVE/FXRSTOR instruction stores to the end of the segment causing a wrap to a misaligned base address (alignment <= 0x10h), and one of the following conditions is satisfied: 1. 32-bit addressing, obtained by using address-size override, when in 64-bit mode 2.
Errata AH41. PREFETCHh Instructions May Not Be Executed When Alignment Check (AC) Is Enabled Problem: PREFETCHT0, PREFETCHT1, PREFETCHT2 and PREFETCHNTA instructions may not be executed when Alignment Check is enabled. Implication: PREFETCHh instructions may not perform the data prefetch if Alignment Check is enabled. Workaround: Clear the AC flag (Bit 18) in the EFLAGS register and/or the AM bit (Bit 18) of Control Register CR0 to disable alignment checking.
Errata AH44. Performance Monitor IDLE_DURING_DIV (18h) Count May Not Be Accurate Problem: Performance monitoring events that count the number of cycles the divider is busy and no other execution unit operation or load operation is in progress may not be accurate. Implication: The counter may reflect a value higher or lower than the actual number of events. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AH45.
Errata AH47. SYSCALL Immediately after Changing EFLAGS.TF May Not Behave According to the New EFLAGS.TF Problem: If a SYSCALL instruction follows immediately after EFLAGS.TF was updated and IA32_FMASK.TF (bit 8) is cleared, then under certain circumstances SYSCALL may behave according to the previous EFLAGS.TF. Implication: When the problem occurs, SYSCALL may generate an unexpected debug exception, or may skip an expected debug exception. Workaround: Mask EFLAGS.TF by setting IA32_FMASK.TF (bit 8).
Errata AH50. IA32_FMASK Is Reset during an INIT Problem: IA32_FMASK MSR (0xC0000084) is reset during INIT. Implication: If an INIT takes place after IA32_FMASK is programmed, the processor will overwrite the value back to the default value. Workaround: Operating system software should initialize IA32_FMASK after INIT. Status: For the steppings affected, see the Summary Tables of Changes. AH51.
Errata AH53. IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly Problem: The IO_SMI bit in SMRAM's location 7FA4H is set to "1" by the CPU to indicate a System Management Interrupt (SMI) occurred as the result of executing an instruction that reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly set by: • A non-I/O instruction. • SMI is pending while a lower priority event interrupts. • A REP I/O read. • An I/O read that redirects to MWAIT.
Errata AH55. Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable Behavior Problem: Memory type aliasing occurs when a single physical page is mapped to two or more different linear addresses, each with different memory type. Memory type aliasing with the memory types WB and WT may cause the processor to perform incorrect operations leading to unpredictable behavior. Implication: Software that uses aliasing of WB and WT memory types may observe unpredictable behavior.
Errata AH58. MOV To/From Debug Registers Causes Debug Exception Problem: When in V86 mode, if a MOV instruction is executed to/from a debug register, a general-protection exception (#GP) should be generated. However, in the case when the general detect enable flag (GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead.
Errata AH60. LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms.
Errata AH64. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable System Behavior Problem: Returning back from SMM mode into real mode while EFLAGS.VM is set in SMRAM may result in unpredictable system behavior. Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in unpredictable system behavior. Intel has not observed this behavior in commerciallyavailable software. Workaround: SMM software should not change the value of EFLAGS.
Errata AH67.
Errata AH70. PMI May Be Delayed to Next PEBS Event Problem: After a PEBS (Precise Event-Based Sampling) event, the PEBS index is compared with the PEBS threshold, and the index is incremented with every event. If PEBS index is equal to the PEBS threshold, a PMI (Performance Monitoring Interrupt) should be issued. Due to this erratum, the PMI may be delayed by one PEBS event. Implication: Debug Store Interrupt Service Routines may observe delay of PMI occurrence by one PEBS event.
Errata AH73. An Asynchronous MCE during a Far Transfer May Corrupt ESP Problem: If an asynchronous machine check occurs during an interrupt, call through gate, FAR RET or IRET and in the presence of certain internal conditions, ESP may be corrupted. Implication: If the MCE (Machine Check Exception) handler is called without a stack switch, then a triple fault will occur due to the corrupted stack pointer, resulting in a processor shutdown.
Errata AH75. B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint Problem: B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly cleared when the following sequence happens: 1. POP instruction to SS (Stack Segment) selector. 2. Next instruction is FP (Floating Point) that gets FP assist followed by code breakpoint. Implication: B0-B3 bits in DR6 may not be properly cleared. Workaround: None identified.
Errata AH78. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: The SIMD_INST_RETIRED (Event: C7H) is used to track retired SSE instructions. Due to this erratum, the processor may also count other types of instructions resulting in values higher than the number of actual retired SSE instructions. Implication: The event monitor instruction SIMD_INST_RETIRED may report count higher than expected. Workaround: None identified.
Errata AH81. A MOV Instruction from CR8 Register with 16-Bit Operand Size Will Leave Bits 63:16 of the Destination Register Unmodified Problem: Moves to/from control registers are supposed to ignore REW.W and the 66H (operand size) prefix. In systems supporting Intel Virtualization Technology, when the processor is operating in VMX non-root operation and “use TPR shadow” VM-execution control is set to 1, a MOV instruction from CR8 with a 16 bit operand size (REX.
Errata AH84. Non-Temporal Data Store May Be Observed in Wrong Program Order Problem: When non-temporal data is accessed by multiple read operations in one thread while another thread performs a cacheable write operation to the same address, the data stored may be observed in wrong program order (i.e., later load operations may read older data). Implication: Software that uses non-temporal data without proper serialization before accessing the non-temporal data may observe data in wrong program order.
Errata AH87. Unaligned Accesses to Paging Structures May Cause the Processor to Hang Problem: When an unaligned access is performed on paging structure entries, accessing a portion of two different entries simultaneously, the processor may livelock. Implication: When this erratum occurs, the processor may livelock causing a system hang. Workaround: Do not perform unaligned accesses on paging structure entries. Status: For the steppings affected, see the Summary Tables of Changes. AH88.
Errata AH90. Page Access Bit May Be Set Prior to Signaling a Code Segment Limit Fault Problem: If code segment limit is set close to the end of a code page, then due to this erratum the memory page Access bit (A bit) may be set for the subsequent page prior to general protection fault on code segment limit.
Errata AH93. EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after Shutdown Problem: When the processor is going into shutdown due to an RSM inconsistency failure, EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be asserted. This may be observed if the processor is taken out of shutdown by NMI#. Implication: A processor that has been taken out of shutdown may have an incorrect EFLAGS, CR0 and CR4. In addition the EXF4 signal may still be asserted.
Errata AH96. Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL Is Counted Incorrectly for PMULUDQ Instruction Problem: Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL (Event select 0B3H, Umask 01H) counts the number of SIMD packed multiply micro-ops executed. The count for PMULUDQ micro-ops might be lower than expected. No other instruction is affected. Implication: The count value returned by the performance monitoring event SIMD_UOP_TYPE_EXEC.MUL may be lower than expected.
Errata AH98. Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #PF Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to both code #DB (Debug Exception) and code Segment Limit Violation #GP (General Protection Fault).
Errata AH99. Performance Monitoring Event CPU_CLK_UNHALTED.REF May Not Count Clock Cycles According to the Processors Operating Frequency Problem: Performance Counter MSR_PERF_FIXED_CTR2 (MSR 30BH) that counts CPU_CLK_UNHALTED.REF clocks should count these clock cycles at a constant rate that is determined by the maximum resolved boot frequency, as programmed by BIOS. Due to this erratum, the rate is instead set by the maximum core-clock to busclock ratio of the processor, as indicated by hardware.
Errata AH101. (E)CX May Get Incorrectly Updated When Performing Fast String REP STOS with Large Data Structures Problem: When performing Fast String REP STOS commands with data structures [(E)CX*Data Size] larger than the supported address size structure (64 KB for 16-bit address size and 4 GB for 32-bit address size) some addresses may be processed more than once.
Errata AH103. Performance Monitoring Event MISALIGN_MEM_REF May Over Count Problem: Performance monitoring event MISALIGN_MEM_REF (05H) is used to count the number of memory accesses that cross an 8-byte boundary and are blocked until retirement. Due to this erratum, the performance monitoring event MISALIGN_MEM_REF also counts other memory accesses. Implication: The performance monitoring event MISALIGN_MEM_REF may over count.
Errata AH106. A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask Problem: The TLB (Translation Lookaside Buffer) may indicate a wrong memory type on a memory access to a large page (2M/4M Byte) following the recovery from a #GP (General Protection Fault) due to a WRMSR to one of the IA32_MTRR_PHYSMASKn MSRs with reserved bits set. Implication: When this erratum occurs, a memory access may get an incorrect memory type leading to unexpected system operation.
Errata AH108. Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Problem: Logging of a branch record or a PEBS (precise-event-based-sampling) record to the DS (debug store) save area that overlaps with the APIC access page may lead to unpredictable behavior. Implication: Guest software configured to log branch records or PEBS records cannot specify the DS (debug store) save area within the APIC-access page.
Errata AH110. BIST Failure after Reset Problem: The processor may show an erroneous BIST (built-in self test) result in bit [17] of EAX register when coming out of reset. Implication: When this erratum occurs, an erroneous BIST failure will be reported in EAX bit [17]. This failure can be ignored since it is not accurate. Workaround: It is possible for BIOS to workaround this erratum by masking off bit [17] of the EAX register after coming out of reset.
Errata AH113 Use of Memory Aliasing with Inconsistent Memory Type May Cause a System Hang or a Machine Check Exception Problem: Software that implements memory aliasing by having more than one linear addresses mapped to the same physical page with different cache types may cause the system to hang or to report a machine check exception (MCE). This would occur if one of the addresses is non-cacheable and used in a code segment and the other is a cacheable address.
Errata AH115 VM Exit with Exit Reason “TPR Below Threshold” Can Cause the Blocking by MOV/POP SS and Blocking by STI Bits to Be Cleared in the Guest Interruptibility-State Field Problem: As specified in Section, “VM Exits Induced by the TPR Shadow”, in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, a VM exit occurs immediately after any VM entry performed with the “use TPR shadow", "activate secondary controls”, and “virtualize APIC accesses” VM-execution controls all set
Errata AH117 RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Problem: RSM instruction execution, under certain conditions triggered by a complex sequence of internal processor micro-architectural events, may lead to processor hang, or unexpected instruction execution results.
Errata AH120 IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error Reporting Enable Correctly Problem: IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to indicate whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at the time of the last update to the IA32_MC1_STATUS MSR. Due to this erratum, IA32_MC1_STATUS MSR bit[60] instead reports the current value of the IA32_MC1_CTL MSR enable bit.
Errata Erratum Affecting Only Intel Core 2 Duo Mobile Processors on Mobile Intel 965 Express Chipset Family AH1P. VM Exit Due to Virtual APIC-Access May Clear RF Problem: RF (Resume Flag), Bit 16 of the EFLAGS/RFLAGS register, is used to restart instruction execution without getting an instruction breakpoint on the instruction following a debug breakpoint exception.
Errata AH4P Removed Erratum AH5P VTPR Access May Lead to System Hang Problem: The logical processor may hang if an instruction performs a VTPR access and the next instruction to be executed is located on a different code page. Implication: Software running VMX non-root operation may cause a logical processor to hang if the virtual-machine monitor (VMM) sets both the “use TPR shadow” and “virtualize APIC accesses” VM-execution controls.
Specification Changes Specification Changes AP1: The following specification change is incorporated in the Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor for Platforms based on Intel® 965 Express Chipset Family – Electrical, Mechanical, and Thermal Specification (EMTS) – Rev. 2.7, Table 27.
Specification Changes § 70 Specification Update
Specification Clarifications Specification Clarifications AH1. Removed AH2. Removed AH3. Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Section 10.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide will be modified to include the presence of page table structure caches, such as the page directory cache, which Intel processors implement.
Documentation Changes Documentation Changes Note: Documentation changes for Intel® 64 and IA-32 Architectures Software Developer’s Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file. http://www.intel.com/design/processor/specupdt/252046.htm .
