Intel® Celeron® Processor Specification Update Release Date: August 2007 Document Number: 243748-051 The Intel® Celeron® processor may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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CONTENTS REVISION HISTORY....................................................................................................................................... ii PREFACE ....................................................................................................................................................... vi ® ® Specification Update for the Intel Celeron Processor................................................................................... 1 GENERAL INFORMATION......................
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE REVISION HISTORY Date of Revision Version Description April 1998 -001 This document is the first Specification Update for the Intel® Celeronc processor. May 1998 -002 Added Errata 24 through 28. June 1998 -003 Updated S-spec Table. Updated Summary Table of Changes. Updated Erratum 2 and 26. Added Errata 29 and 30. Added Documentation Changes 7 through 12. Added Specification Clarification 6 and 7. July 1998 -004 Updated S-spec Table.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE REVISION HISTORY Date of Revision Version Description August 1999 -017 Added Documentation Change C2. Updated Preface paragraph. Updated Codes Used in Summary Table. Updated column heading in Errata, Documentation Changes, Specification Clarifications and Specification Changes tables. October 1999 -018 Added ‘Brand Id’ to Identification Information table. Updated Processor Identification Information Table. Added Errata C46.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE REVISION HISTORY Date of Revision Version Description July 2001 -035 Updated the Intel® Celeron® Processor Identification Information table. Updated the Summary of Errata table. August 2001 -036 Added Errata C79 and C80. Updated the Summary of changes section. August 2001 -037 Out of cycle release. Updated the Intel® Celeron® Processor Identification Information table October 2001 -038 Updated the identification information section with 0.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE REVISION HISTORY Date of Revision August 2007 Version -051 Description Updated Summary Table of Changes. Added Erratum C111.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE PREFACE This document is an update to the specifications contained in the following documents: • Pentium® II Processor Developer’s Manual (Order Number 243502) • P6 Family of Processors Hardware Developer’s Manual (Order Number 244001) • Intel® Celeron® Processor Datasheet (Document Number 243658) • Intel® 64 and Intel IA-32 Architectures Software Developer’s Manual, Volumes 1, 2-A, 2-B, 3-A and 3-B (Document numbers 253665, 253666, 253667, 253668, and
Specification Update for the Intel® Celeron® Processor GENERAL INFORMATION Intel® Celeron® Processor and Boxed Intel® Celeron® Processor Markings (S.E.P. Package) Static White Silkscreen marks Dynamic laser mark area NOTES: • SYYYY = S-spec Number. FFFFFFFF = FPO # (Test Lot Traceability #). COA = Country of Assembly.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor and Boxed Intel® Celeron® Processor Markings (PPGA Package) Top Bottom intel ® celeronTM i AAAAAAAZZZ LLL SYYYY Country of Origin FFFFFFFF-XXXX M C ’98 NOTES: AAAAAAA = Product Code ZZZ = Processor Speed (MHz) LLL = Integrated Level-Two Cache Size (in Kilobytes) SYYYY = S-Spec Number FFFFFFFF-XXXX = Assembly Lot Tracking Number 2-D Matrix Mark Intel UCC# Order Code (Product - speed) S Number Lot Number (dat
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor and Boxed Intel® Celeron® Processor Markings (FC-PGA/FC-PGA2 Package) FC-PGA 370 Pin Package GRP1LN1: INTEL (m)(c) '01_-_{COO} GRP1LN2: {Core Freq}/{Cache}/{Bus Freq}/{Voltage} GRP2LN1: {FPO}-{S/N} GRP2LN2: CELERON {S-Spec} FC-PGA2 370 Pin Package GRP1LN1 GRP1LN2 GRP2LN1 GRP2LN2 GRP1LN1: INTEL (m)(c) '01_-_{Country of Origin} GRP1LN2: {Core freq}/{Cache}/{Bus Freq}/{Voltage} GRP2LN1: {FPO}-{S/N} GRP2LN2: CELERON {S-Spec} 3
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE IDENTIFICATION INFORMATION Complete identification information of the Celeron processor can be found in the Intel Processor Identification and the CPUID Instruction application note (Document Number 241618).
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor Identification Information S-Spec Core Stepping L2 Cache Size (Kbytes) SL2SY A0 0 SL2YN A0 SL2YP CPUID Speed (MHz) Core/Bus Package and Revision 0650h 266/66 SEPP Rev. 1 0 0650h 266/66 SEPP Rev. 1 A0 0 0650h 300/66 SEPP Rev. 1 Notes 1 SL2Z7 A0 0 0650h 300/66 SEPP Rev. 1 SL2TR A1 0 0651h 266/66 SEPP Rev. 1 1 SL2QG A1 0 0651h 266/66 SEPP Rev. 1 SL2X8 A1 0 0651h 300/66 SEPP Rev.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor Identification Information 6 S-Spec Core Stepping L2 Cache Size (Kbytes) SL3A2 B0 128 SL37X B0 SL3BA CPUID Speed (MHz) Core/Bus Package and Revision 0665h 400/66 PPGA 128 0665h 400/66 PPGA B0 128 0665h 433/66 PPGA SL3BS B0 128 0665h 433/66 PPGA SL3EH B0 128 0665h 466/66 PPGA SL3FL B0 128 0665h 466/66 PPGA SL3FY B0 128 0665h 500/66 PPGA SL3LQ B0 128 0665h 500/66 PPGA SL3FZ B0 128
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor Identification Information S-Spec Core Stepping L2 Cache Size (Kbytes) SL48F B0 128 SL4EG B0 SL4P8 CPUID Speed (MHz) Core/Bus Package and Revision 0683h 700/66 FC-PGA 128 0683h 700/66 FC-PGA 2 C0 128 0686h 700/66 FC-PGA 2, 4, 5 SL4P2 C0 128 0686h 700/66 FC-PGA 2, 4, 5 SL4P7 C0 128 0686h 733/66 FC-PGA 4, 5 Notes SL4P3 C0 128 0686h 733/66 FC-PGA 2, 4, 5 SL52Y D0 128 068Ah 733/66 FC-PG
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor Identification Information 8 S-Spec Core Stepping L2 Cache Size (Kbytes) SL634 D0 128 CPUID Speed (MHz) Core/Bus Package and Revision Notes 068Ah 950/100 FC-PGA2 2,8,14
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor Identification Information S-Spec Core Stepping L2 Cache Size (Kbytes) SL5XT D0 128 SL5XQ D0 SL5XU CPUID Speed (MHz) Core/Bus Package and Revision Notes 068Ah 1 GHz/100 FC-PGA 8,11 128 068Ah 1 GHz/100 FC-PGA 2, 8,11 D0 128 068Ah 1.10 GHz/100 FC-PGA 8, 9 SL5XR D0 128 068Ah 1.10 GHz/100 FC-PGA 2, 8,9 SL5VQ A1 256 06B1h 1.10A GHz/100 FC-PGA2 2,12,13 SL5ZE A1 256 06B1h 1.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Intel® Celeron® Processor Identification Information S-Spec Core Stepping L2 Cache Size (Kbytes) CPUID SL6C6 B1 256 06B4h SL6JU B1 256 SL6C5 B1 SL6JV B1 Package and Revision Notes 1.40 GHz/100 FC-PGA2 14, 15 06B4h 1.40 GHz/100 FC-PGA2 2,14, 15 256 06B4h 1.50 GHz/100 FC-PGA2 1,3, 19 256 06B4h 1.50 GHz/100 FC-PGA2 1,3, 19 Speed (MHz) Core/Bus NOTES: 1. This is a boxed Celeron processor with an attached fan heatsink. 2.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE SUMMARY OF CHANGES The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Celeron processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE ® AC = Intel Celeron® Processor in 478 Pin Package ® AD = Intel Celeron® D processor on 65 nm process ® ® AE = Intel Core™ Duo Processor and Intel Core™ Solo processor on 65 nm process ® ® AF = Dual-Core Intel Xeon processor LV ® ® AG = Dual-Core Intel Xeon Processor 5100 Series AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology ® Δ ® Δ AI = Intel Core™2 Extreme Processor X6800 and Intel Core™2 Duo Desktop Processor E6000 and Δ
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO. CPUID/Stepping 665h 683h 686h B0 B0 C0 68Ah D0 6B1h A1 6B4h B1 C53 X X X X X NoFix FLUSH# servicing delayed while waiting for STARTUP_IPI in 2-way MP systems C54 X X X X X NoFix Double ECC error on read may result in BINIT# C55 X X X X X NoFix MCE due to L2 parity error gives L1 MCACOD.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE * Fix will be only on Celeron processors with CPUID=068xh.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Documentation Changes CPUID/Stepping 665h 683h 686h B0 B0 C0 X X X C22 650h A0 X 651h A1 X 660h A0 X C23 X X X X X C24 X X X X X NO.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Specification Clarifications CPUID/Stepping SPECIFICATION CLARIFICATIONS 651h A1 X 660h A0 X 665h B0 X 683h B0 X 686h C0 X 68Ah D0 X 6B1h A1 X 6B4h B1 X Plans C1 650h A0 X Doc PWRGOOD inactive pulse width C2 X X X X X X X X X Doc Floating-point opcode clarification C3 X X X X X X X X X Doc MTRR initialization clarification C4 X X X X X X X X X Doc Non-AGTL+ output low current clarification NO.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Specification Changes CPUID/Stepping 665h 683h 686h B0 B0 C0 X X X 68Ah D0 X C2 X X X C3 X X X NO.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE ERRATA C1. FP Data Operand Pointer May Be Incorrectly Calculated After FP Access Which Wraps 64-Kbyte Boundary in 16-Bit Code Problem: The FP Data Operand Pointer is the effective address of the operand associated with the last noncontrol floating-point instruction executed by the machine.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE b) causes the page table Access or Dirty (A/D) bits to be modified, the breakpoint information for the MOVSS or POPSS will be lost. Previous Celeron processors retain this information under these boundary conditions. Case 3: If they occur after a MOVSS or POPSS instruction, the INTn, INTO, and INT3 instructions zero the DR6.bi bits (bits B0 through B3), clearing pending breakpoint information, unlike previous In Celeron processors.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C4. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is not exactly representable in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally set by the processor. Under certain rare conditions, this bit may not be set when this rounding occurs.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C6. I/O Restart in SMM May Fail After Simultaneous MCE Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the Celeron processor will signal a machine check exception (MCE). If the instruction is directed at a device which is powered down, the processor may also receive an assertion of SMI#.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C9. LBER May Be Corrupted After Some Events Problem: The last branch record (LBR) and the last branch before exception record (LBER) can be used to determine the source and destination information for previous branches or exceptions. The LBR contains the source and destination addresses for the last branch or exception, and the LBER contains similar information for the last branch taken before the last exception.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C11. Potential Early Deassertion of LOCK# During Split-Lock Cycles Problem: During a split-lock cycle there are four bus transactions: 1st ADS# (a partial read), 2nd ADS# (a partial read), 3rd ADS# (a partial write), and the 4th ADS# (a partial write). Due to this erratum, LOCK# may deassert one clock after the 4th ADS# of the split-lock cycle instead of after the 4th RS# assertion corresponding to the 4th ADS# has been sampled.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Status: For the steppings affected see the Summary of Changes at the beginning of this section. C13. Reporting of Floating-Point Exception May Be Delayed Problem: The Celeron processor normally reports a floating-point exception for an instruction when the next ® floating-point or Intel MMX™ technology instruction is executed.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C15. Built-in Self Test Always Gives Nonzero Result Problem: The Built-in Self Test (BIST) of the Celeron processor does not give a zero result to indicate a passing test. Regardless of pass or fail status, bit 6 of the BIST result in the EAX register after running BIST is set. Implication: Software which relies on a zero result to indicate a passing BIST will indicate BIST failure.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C18. Snoop Cycle Generates Spurious Machine Check Exception Problem: The processor may incorrectly generate a Machine Check Exception (MCE) when it processes a snoop access that does not hit the L1 data cache. Due to an internal logic error, this type of snoop cycle may still check data parity on undriven data lines. The processor generates a spurious machine check exception as a result of this unnecessary parity check.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE 3. The unmasked floating-point exception case only occurs if the store is the first MMX technology instruction in an MMX technology routine and the previous floating-point routine exited with an unmasked floatingpoint exception pending.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Workaround: If the chipset and third party agents used with the Celeron processor do not optimize their arbitration latency as described above, no action is required. For the 66 MHz Celeron processor, no action is required. Status: For the steppings affected see the Summary of Changes at the beginning of this section. C22.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C23. MOVD Following Zeroing Instruction Can Cause Incorrect Result Problem: An incorrect result may be calculated after the following circumstances occur: 1. A register has been zeroed with either a SUB reg, reg instruction or an XOR reg, reg instruction, 2. A value is moved with sign extension into the same register’s lower 16 bits; or a signed integer multiply is performed to the same register’s lower 16 bits, 3.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Workaround: There are two possible workarounds for this erratum: 1. Rather than using the MOVSX-MOVD or CBW-MOVD pairing to handle one variable at a time, use the sign extension capabilities (PSRAW, etc.) within MMX technology for operating on multiple variables. This would result in higher performance as well. 2.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C25. Read Portion of RMW Instruction May Execute Twice Problem: When the Celeron processor executes a read-modify-write (RMW) arithmetic instruction, with memory as the destination, it is possible for a page fault to occur during the execution of the store on the memory operand after the read operation has completed but before the write operation completes.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Status: For the steppings affected see the Summary of Changes at the beginning of this section. C28.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C30. Upper Four PAT Entries Not Usable With Mode B or Mode C Paging Problem: The Page Attribute Table (PAT) contains eight entries, which must all be initialized and considered when setting up memory types for the Celeron processor. However, in Mode B or Mode C paging, the upper four entries do not function correctly for 4-Kbyte pages.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C32. Misprediction in Program Flow May Cause Unexpected Instruction Execution Problem: To optimize performance through dynamic execution technology, the P6 architecture has the ability to predict program flow. In the event of a misprediction, the processor will normally clear the incorrect prediction, adjust the EIP to the correct location, and flush out any instructions it may have fetched from the misprediction.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Workaround: All bus agents that support system bus ECC must disable it when a 2:1 ratio is used. Status: For the steppings affected see the Summary of Changes at the beginning of this section. C35.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C37. SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment Selector” to SS and CS Registers Problem: According to the processor specification, attempting to load a null segment selector into the CS and SS segment registers should generate a General Protection Fault (#GP).
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C39. Far Jump to New TSS With D-bit Cleared May Cause System Hang Problem: A task switch may be performed by executing a far jump through a task gate or to a new Task State Segment (TSS) directly.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C41. UC Write May Be Reordered Around a Cacheable Write Problem: After a write occurs to a UC (uncacheable) region of memory, there exists a small window of opportunity where a subsequent write transaction targeted for a UC memory region may be reordered in front of a write targeted to a region of cacheable memory. This erratum can only occur during the following sequence of bus transactions: 1. A write to memory mapped as UC occurs 2.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C43. Internal Cache Protocol Violation May Cause System Hang Problem: A Celeron processor-based system may hang due to an internal cache protocol violation. During multiple transactions targeted at the same cacheline, there exists a small window of time such that the processor's internal timings align to create a livelock situation. The scenario, which results in the erratum, is summarized below: Scenario: 1. A snoopable transaction is issued to address A.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C45. Machine Check Exception May Occur Due to Improper Line Eviction in the IFU Problem: The Celeron processor is designed to signal an unrecoverable Machine Check Exception (MCE) as a consistency checking mechanism.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C47. Task Switch May Cause Wrong PTE and PDE Access Bit to be Set Problem: If an operating system executes a task switch via a Task State Segment (TSS), and the TSS is wholly or partially located within a clean page (A and D bits clear) and the GDT entry for the new TSS is either misaligned across a cache line boundary or is in a clean page, the accessed and dirty bits for an incorrect page table/directory entry may be set.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C49. Deadlock May Occur Due To Illegal-Instruction/Page-Miss Combination Problem: Intel's 32-bit Instruction Set Architecture (ISA) utilizes most of the available op-code space; however some byte combinations remain undefined and are considered illegal instructions. Intel processors detect the attempted execution of illegal instructions and signal an exception. This exception is handled by the operating system and/or application software.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C51. Floating-Point Exception Condition May be Deferred Problem: A floating-point instruction that causes a pending floating-point exception (ES=1) is normally signaled by the processor on the next waiting FP/MMX™ technology instruction. In the following set of circumstances, the exception may be delayed or the FSW register may contain a wrong value: 1.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C53. FLUSH# Servicing Delayed While Waiting for STARTUP_IPI in 2-way MP Systems Problem: In a 2-way MP system, if an application processor is waiting for a startup inter-processor interrupt (STARTUP_IPI), then it will not service a FLUSH# pin assertion until it has received the STARTUP_IPI. Implication: After the 2-way MP initialization protocol, only one processor becomes the bootstrap processor (BSP).
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C55. MCE Due to L2 Parity Error Gives L1 MCACOD.LL Problem: If a Cache Reply Parity (CRP) error, Cache Address Parity (CAP) error, or Cache Synchronous Error (CSER) occurs on an access to the Celeron processor’s L2 cache, the resulting Machine Check Architectural Error Code (MCACOD) will be logged with ‘01’ in the LL field. This value indicates an L1 cache error; the value should be ‘10’, indicating an L2 cache error.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C57. Mixed Cacheability of Lock Variables Is Problematic in MP Systems Problem: This errata only affects multiprocessor systems where a lock variable address is marked cacheable in one processor and uncacheable in any others. The processors which have it marked uncacheable may stall indefinitely when accessing the lock variable. The stall is only encountered if: • One processor has the lock variable cached, and is attempting to execute a cache lock.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C59. Potential Loss of Data Coherency During MP Data Ownership Transfer Problem: In MP systems, processors may be sharing data in different cache lines, referenced as line A and line B in the discussion below. When this erratum occurs (with the following example given for a 2-way MP system with processors noted as ‘P0’ and ‘P1’), P0 contains a shared copy of line B in its L1. P1 has a shared copy of Line A.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C61. Memory Ordering Based Synchronization May Cause a Livelock Condition in MP Systems Problem: In an MP environment, the following sequence of code (or similar code) in two processors (P0 and P1) may cause them to each enter an infinite loop (livelock condition): P0 P1 MOV [xyz], EAX (1) wait1: MOV EBX, [abc] . CMP EBX, val1 . JNE wait1 .
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C62. Processor May Assert DRDY# on a Write With No Data Problem: When a MASKMOVQ instruction is misaligned across a chunk boundary in a way that one chunk has a mask of all 0’s, the processor will initiate two partial write transactions with one having all byte enables deasserted.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Status: For the steppings affected, see the Summary of Changes at the beginning of this section. C66. MASKMOVQ Instruction Interaction with String Operation May Cause Deadlock Problem: Under the following scenario, combined with a specific alignment of internal events, the processor may enter a deadlock condition: 1. A store operation completes, leaving a write-combining (WC) buffer partially filled. 2.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE or IMUL AX, word ptr (opcode 0F AF /r) or IMUL AX, BX, 16 (opcode 6B /r ib) or IMUL AX, word ptr , 16 (opcode 6B /r ib) or IMUL AX, 8 (opcode 6B /r ib) or IMUL AX, BX, 1024 (opcode 69 /r iw) or IMUL AX, word ptr , 1024 (opcode 69 /r iw) or IMUL AX, 1024 (opcode 69 /r iw) or CBW 3. MOVD MM0, EAX or CVTSI2SS MM0, EAX Note that the values for immediate byte/words are merely representative (i.e.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE *Note: MOV EAX, EAX is used here in a generic sense. Again, EAX can be substituted with any 32-bit register. Status: For the steppings affected see the Summary of Changes at the beginning of this section. C68. Snoop Probe During FLUSH# Could Cause L2 to be Left in Shared State.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C70. Selector for the LTR/LLDT Register May Get Corrupted Problem: The internal selector portion of the respective register (TR, LDTR) may get corrupted if, during a small window of LTR or LLDT system instruction execution, the following sequence of events occur: 1. Speculative write to a segment register that might follow the LTR or LLDT instruction 2.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C73. Memory Aliasing with Inconsistent A and D bits May Cause Processor Deadlock Problem: In the event that software implements memory aliasing by having two Page Directory Entries(PDEs) point to a common Page Table Entry(PTE) and the Accessed and Dirty bits for the two PDEs are allowed to become inconsistent, the processor may become deadlocked. Implication: This erratum has not been observed with commercially available software.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C76. Machine Check Exception may Occur When Interleaving Code Between Different Memory Types Problem: A small window of opportunity exists where code fetches interleaved between different memory types may cause a machine check exception. A complex set of micro-architectural boundary conditions is required to expose this window. Implication: Interleaved instruction fetches between different memory types may result in a machine check exception.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C79. The instruction Fetch Unit (IFU) May Fetch Instructions Based Upon Stale CR3 Data After a Write to CR3 Register Problem: Under a complex set of conditions, there exists a one clock window following a write to the CR3 register where-in it is possible for the iTLB fill buffer to obtain a stale page translation based on the stale CR3 data.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C82. Incorrect Assertion of THERMTRIP# Signal Problem: The internal control register bit responsible for operation of the Thermtrip circuit functionality may power up in a non-initialized state. As a result, THERMTRIP# may be incorrectly asserted during de-assertion of RESET# at nominal operating temperatures.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Figure 1 Celeron® on 0.13 Micron Processor 256K Platforms Workaround 2.5V R1 330 ohm PW RGD R2 PGA370 510 ohm R4 For Production Boards: Depopulate R5 To use ITP: Install R5, Depopulate R4 TCK 0 ohm R3 1.3K ohm R5 39 ohm ITP TCK • The example workaround circuit assumes that the PWRGD inputs into the processors are open collector.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C83. Under Some Complex Conditions, the Instructions in the shadow of a JMP FAR may be Unintentionally Executed and Retired Problem: If all of the following events happen in sequence it is possible for the system or application to hang or to execute with incorrect data. 1.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C85. Lock Data Access that Spans Two Pages May Cause the System to Hang Problem: An instruction with lock data access that spans across two pages may, given some rare internal conditions, hang the system. Implication: When this erratum occurs, the system may hang. Intel has not observed this erratum with any commercially available software or system. Workaround: A lockable data access should always be aligned.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C87. The FXSAVE, STOS, or MOVS Instructions May Cause a Store Ordering Violation When Data Crosses a Page with a UC Memory Type Problem: If the data from an FXSAVE, STOS, or MOVS instruction crosses a page boundary from WB to UC memory type and this instruction is immediately followed by a second instruction that also issues a store to memory, the final data stores from both instructions may occur in the wrong order.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system. Workaround: Avoid code that wraps around segment limit. Status: C90. Problem: For the steppings affected, see the Summary Tables of Changes.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Status: For the steppings affected, see the Summary Tables of Changes. C92.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Problem: A load from memory type USWC may get its data internally forwarded from a pending store. As a result, the expected load may never be issued to the external bus. Implication: When this erratum occurs, a USWC Load request may be satisfied without being observed on the external bus. There are no known usage models where this behavior results in any negative side-effects. Workaround: Do not use memory type USWC for memory that has read side-effects.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Implication: This erratum may cause an unexpected stack overflow. Workaround: User mode code should not count on being able to recover from illegal accesses to memory regions protected with supervisor only access when using FP instructions. Status: For the steppings affected, see the Summary Tables of Changes. C97.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. C100.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE • a linear address has bit 20 set • the address references a large page • A20M# is enabled Implication: When A20M# is enabled and an address references a large page the resulting translated physical address may be incorrect. This erratum has not been observed with any commercially available operating system.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or PE) registers before writing to memory early in BIOS code to clear all the global entries from TLB. Status: For the steppings affected, see the Summary Table of Changes. C104.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE • INT1 instruction; • Code breakpoint the DR6 BS (Single Step, bit 14) flag may be incorrectly set. Implication: The BS flag may be incorrectly set for non-single-step #DB exception. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes C106. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Problem: The ENTER instruction is used to create a procedure stack frame.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C108: INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions Problem: The INVLPG instruction may not completely invalidate Translation Look-aside Buffer (TLB) entries for large pages (2M/4M) when both of the following conditions exist: • Address range of the page being invalidated spans several Memory Type Range Registers (MTRRs) with different memory types specified • INVLPG operation is preceded by a Page Assist Event (Page Faul
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C111 Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum, if only a small number of MMX instructions (including EMMS) are executed immediately after the last FP instruction, an FP to MMX transition may not be counted.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE DOCUMENTATION CHANGES The Documentation Changes listed in this section apply to the following documents: • Pentium® II Processor Developer’s Manual • P6 Family of Processors Hardware Developer's Manual • Intel® Celeron® Processor Datasheet • Intel Architecture Software Developer’s Manual, Volumes 1, 2, and 3 All Documentation Changes will be incorporated into a future version of the appropriate Celeron processor documentation. C1.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C2. Executing the SSE2 Variant on a Non-SSE2 Capable Processor In Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference the section for each of the following instructions states that executing the instruction in real or protected mode on a processor for which the SSE2 feature flag returned by CPUID is 0 (SSE2 not supported by the processor) will result in the generation of an undefined opcode exception (#UD). This is incorrect.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE It should state: "If FOP code compatibility mode is enabled, the FOP is defined as it has always been in previous IA32 implementations (always defined as the FOP of the last non-transparent FP instruction executed before a FSAVE/FSTENV/FXSAVE). If FOP code compatibility mode is disabled (default), FOP is only valid if the last non-transparent FP instruction executed before a FSAVE/FSTENV/FXSAVE had an unmasked exception." C5.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C7. EFLAGS Register Correction The Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture Section 3.7.2, Figure 3.7. “EFLAGS Register” currently states: Bit 11 “OF” as “X” It should state: Bit 11 “OF” as “S” C8. PSE-36 Paging Mechanism The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide Chapter 3, Section 3.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C9. 0x33 Opcode The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Appendix A, Table A-2, the opcode corresponding to 0x33 currently states: Gb, Ev It should state: Gv, Ev Also, Page 3-791, XOR-Logical Exclusive OR, the two entries for opcode 33 currently state: Opcode 33 /r 33 /r Instruction XOR r16,r/m16 XOR r32,r/m32 Description r8 XOR r/m8 r8 XOR r/m8 It should state: Opcode C10.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C12. Errors in Instruction Set Reference The following changes will be made to the Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference: 1. Page 3-586 “PMULUDQ—Multiply Packed Unsigned Doubleword Integers” currently states: 66 OF F4 /r PMULUDQ xmm1, xmm2/m128 It should state: 66 0F F4 /r PMULUDQ xmm1, xmm2/m128 2.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE PMOVMSKB (66) Gd, Vdq 5. Page A-10, Table A-3, Two-byte Opcode Map:80H-7FH (First Byte is 0FH). Entry F7 currently states: MASKMOVQ Ppi, Qpi MASKMOVQU (66) Vdq, Wdq It should state: MASKMOVQ Ppi, Qpi MASKMOVDQU (66) Vdq, Wdq 6. Page A-11, Table A-3, Two-byte Opcode Map:88H-7FH (First Byte is 0FH). The title table currently states: Table A-3. Two-byte Opcode Map:88H-7FH (First Byte is FFH) It should state: Table A-3.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE PMULH – Packed multiplication It should state: PMULHW – Packed multiplication, store high word 10. Page B-21, Table B-12, MMX Instruction Formats and Encodings (Contd.). Add instruction PMULHUW : PMULHUW – Packed multiplication, store high word (unsigned) mmxreg2 to mmxreg1 memory to mmxreg 0000 1111: 1110 0100: 11 mmxreg1 mmxreg2 0000 1111: 1110 0100: mod mmxreg r/m 11. Page B-21, Table B-12, MMX Instruction Formats and Encodings (Contd.).
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE 15. Page B-41, Table B-19, Formats and Encodings of the SSE2 SIMD Integer Instruction. Entry PMULL currently states: PMULL – Packed multiplication It should state: PMULLW – Packed multiplication, store low word C13. RSM Instruction Set Summary The Intel Architecture Software Developer's Manual, Vol 1: Basic Architecture Section 5.8 "INSTRUCTION SET SUMMARY” currently states: RSM Return from system management mode (SSM) It should state: RSM C14.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C15.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C16.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C17. Omission of Dependency Between BTM and LBR The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide Chapter 15, Section 5.3, on page 15-15 currently states: 15.5.3.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C18. I/O Permissions Bitmap Base Addy > 0xDFFF Does not Cause #GP(0) Fault The Intel Architecture Software Developer's Manual, Vol 1: Basic Architecture, page 12-6, section 12.5.2, last paragraph currently states: If the I/O bit map base address is greater than or equal to the TSS segment limit, there is no I/O permission map, and all I/O instructions generate exceptions when the CPL is greater than the current IOPL.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C20. Figure 15-12 PEBS Record Format The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide Section 15.9.6 " Programming the Performance Counters for Non-Retirement Events" page 15 - 37, Figure 15-12, first row currently states: 63 0 EFLAGS It should state: 31 0 EFLAGS C21. I/O Permission Bit Map The Intel Architecture Software Developer's Manual, Vol 1: Basic Architecture Chapter 12, section 12.5.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C22. Cache Description The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Table 3-10, the "sectored, 64 byte line size" description is used for the following descriptors: 0x22, 0x23, 0x79, 0x7a, 0x7b, 0x7c. This description will change to "dual-sectored line, 64 byte sector size" for clarity. C23.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE IF CPU supports MCE THEN IF CPU supports MCA THEN IF IA32_ MCG_CAP.MCG_CTL_P = 1 (* IA32_MCG_CTL register is present *) IA32_MCG_CTL FFFFFFFFFFFFFFFFH; (* enables all MCA features *) FI; COUNT <-- IA32_MCG_CAP.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Example . In addition, when using P6 family processors, the software must set MCi_STATUS registers to 0 when doing a soft-reset. Machine-Check Initialization Pseudocode Check CPUID Feature Flags for MCE and MCA support IF CPU supports MCE THEN IF CPU supports MCA THEN IF (IA32_MCG_CAP.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE FOR error-reporting banks (0 through MAX_BANK_NUMBER) DO IA32_MCi_STATUS <-- 0; OD ELSE FOR error-reporting banks (0 through MAX_BANK_NUMBER) DO (Optional for BIOS and OS) Log valid errors (OS only) IA32_MCi_STATUS <-- 0; OD FI FI FI Setup the Machine Check Exception (#MC) handler for vector 18 in IDT Set the MCE bit (bit 6) in CR4 register to enable Machine-Check Exceptions FI 96
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE SPECIFICATION CLARIFICATIONS The Specification Clarifications listed in this section apply to the following documents: • Pentium® II Processor Developer’s Manual • P6 Family of Processors Hardware Developer's Manual • Intel® Celeron® Processor Datasheet • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 1, 2A, 2B, 3A and 3B.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Instruction Set Reference Section Opcode Instruction Addition to Page Addition “Comments” section FSTCW/FNSTCW-Store Control Word 9B D9 /7 FSTCW m2byte Add “Comments” section with clarification phrase 3-250 FSTENV/FNSTENV-Store FPU Environment 9B D9 /6 FSTENV m14/28byte Add “Comments” section with clarification phrase 3-253 FSTSW/FNSTSW-Store Status Word 9B DD /7 FSTSW m2byte 3-256 9B DF E0 FSTSW AX Add “Comments” section with clarification
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE SPECIFICATION CHANGES The Specification Changes listed in this section apply to the following documents: • Pentium® II Processor Developer’s Manual • P6 Family of Processors Hardware Developer's Manual • Intel® Celeron® Processor Datasheet • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 1, 2A, 2B, 3A and 3B. All Specification Changes will be incorporated into a future version of the appropriate Celeron processor documentation.
INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE C3. Processor Thermal Specification Change and TDP Redefined The Thermal Design Power (TDP) for Celeron processors has been redefined. Table 2 details TDP for Celeron processors. The updated TDP values are based on device characterization and do not reflect any silicon design changes to lower processor power consumption.
