Intel® PXA250 and PXA210 Applications Processors Design Guide February, 2002 Order Number: 278523-001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Contents Contents 1 Introduction.................................................................................................................................1-1 1.1 1.2 2 System Memory Interface ..........................................................................................................2-1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 Overview............................................................................................................................2-1 SDRAM Interface ..............
Contents 5 MultiMediaCard (MMC)...............................................................................................................5-1 5.1 5.2 6 AC97 ............................................................................................................................................6-1 6.1 6.2 7 7.2 Schematics ........................................................................................................................7-1 7.1.1 Signal Description...........................
Contents A.1 A.2 A.3 B Example Form Factor Reference Design Schematic Diagrams ............................................ B-1 B.1 B.2 C Schematic Diagram .......................................................................................................... C-1 PXA250 Processor Card Schematic Diagram ......................................................................... D-1 D.1 E Notes .........................................................................................................
Contents Figures 1-1 Applications Processor Block Diagram......................................................................................1-2 1-2 PXA250 Applications Processor ..............................................................................................1-11 1-3 PXA210 Applications Processor ..............................................................................................1-15 2-1 General Memory Interface Configuration .......................................................
Contents 2-7 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications ..........................................2-9 2-8 Variable Latency I/O Interface AC Specifications ....................................................................2-10 2-9 Card Interface (PCMCIA or Compact Flash) AC Specifications ..............................................2-13 2-10Minimum and Maximum Trace Lengths for the SDRAM Signals.............................................2-18 3-1 LCD Controller Data Pin Utilization..
Contents viii PXA250 and PXA210 Applications Processors Design Guide
1 Introduction Table 1-1. Revision History Date Revision Description Nov 2000 0.1 Initial Release: RS-Intel® PXA250 Platform Design Guide Nov 2000 0.2 Second draft Jan 2001 0.3 May 2001 0.6 Added reference to PXA210 and performed editorial clean-up. February 2002 1.0 Public Release Corrected name of FFRTS in Table 1-4. Reorganized Table 1-4 and Table 1-5 for readability.
Introduction s Figure 1-1. Applications Processor Block Diagram RTC Color or Grayscale LCD Controller OS Timer 2 IS I2C AC97 DMA Controller and Bridge General Purpose I/O Int. Controller Clocks & Power Man.
Introduction • System memory interface — 100 MHz SDRAM — 4 MB to 256 MB of SDRAM memory — Support for 16, 64, 128, or 256 Mbit DRAM technologies — 4 Banks of SDRAM, each supporting 64 MB of memory — Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh) — Supports as many as 6 static memory devices (SRAM, Flash, or VLIO) • • • • • • • • • • • • • PCMCIA/Compact Flash card control pins LCD Controller pins Full Function UART Bluetooth UART MMC Controller pins SSP Pins USB
Introduction • • • • 1.2.2 I2C Controller pins PWM pins 2 dedicated GPIOs pins Integrated JTAG support Signal Pin Descriptions Table 1-3 defines the signal descriptions for the applications processor. Table 1-3. Signal Pin Descriptions (Sheet 1 of 7) Name Type Description Memory Controller Pins MA[25:0] OCZ MD[15:0] ICOCZ Memory data bus. D[15:0] are used for 16-bit and 32-bit data modes. ICOCZ Memory data bus. D[31:16]: These signals are the upper memory data bus address bits.
Introduction Table 1-3. Signal Pin Descriptions (Sheet 2 of 7) Name nCS[5]/ GPIO[33] nCS[4]/ GPIO[80] nCS[3]/ GPIO[79] Type Description ICOCZ ICOCZ ICOCZ Static chip selects. These signals are chip selects to static memory devices such as ROM and Flash. They are individually programmable in the memory configuration registers. nCS[5:3] may be used with variable data latency variable latency I/O devices. See Note [2] nCS[2]/ GPIO[78] nCS[1]/ GPIO[15] ICOCZ ICOCZ nCS[0] ICOCZ Static chip select 0.
Introduction Table 1-3. Signal Pin Descriptions (Sheet 3 of 7) Name nPREG/ GPIO[55] Type ICOCZ Description PCMCIA register select. Output signal that indicates the target address is attribute space, on a memory transaction. This signal has the same timing as address.
Introduction Table 1-3. Signal Pin Descriptions (Sheet 4 of 7) Name Type Description MMDAT ICOCZ Multimedia Card Data Pin (I/O) MMCCLK/GP[6] ICOCZ MMC clock. (output) Clock signal for the MMC Controller. MMCCS0/GP[8] ICOCZ MMC chip select 0. (output) Chip select 0 for the MMC Controller. MMCCS1/GP[9] ICOCZ MMC chip select 1. (output) Chip select 1 for the MMC Controller.
Introduction Table 1-3. Signal Pin Descriptions (Sheet 5 of 7) Name Type Description I2C Data signal (bidirectional). SDA ICOCZ Bidirectional signal. When it is driving, it functions as an open collector device and requires a pull up resistor. As an input, it expects standard CMOS levels.
Introduction Table 1-3. Signal Pin Descriptions (Sheet 6 of 7) Name Type Description VDD Fault. Active low input. nVDD_FAULT IC nVDD_FAULT causes the applications processor to enter Sleep Mode. nVDD_FAULT is ignored after a wakeup event until the power supply timer completes (approximately 10 ms). use the nVDD_FAULT signal to flag a low battery. Minimum assertion time for nVDD_FAULT is 1 ms. Hard reset. Active low input.
Introduction Table 1-3. Signal Pin Descriptions (Sheet 7 of 7) Name Type Description VSSN SUP Ground supply for memory bus and PCMCIA pins. Connect these pins to the common ground plane on the PCB. BATT_VCC SUP Backup battery connection. Connect this pin to the backup battery supply. If a backup battery is not required then this pin may be connected to the common 3.3v supply on the PCB. NOTES: 1. Not pinned out for the PXA210 applications processor. 2.
Introduction Figure 1-2.
Introduction Table 1-4.
Introduction Table 1-4.
Introduction Table 1-4.
Introduction φ Figure 1-3.
Introduction Table 1-5.
Introduction Table 1-5.
Introduction 1-18 PXA250 and PXA210 Applications Processors Design Guide
System Memory Interface 2 This section is the design guidelines for the system memory interface. 2.1 Overview The external memory bus interface for the applications processor supports: • • • • • • • • • 100 MHz SDRAM at 3.3 V 100 MHz SDRAM at 2.
System Memory Interface Figure 2-1.
System Memory Interface Table 2-1. Memory Address Map 2.
System Memory Interface Figure 2-2.
System Memory Interface 2.4 SDRAM Support Table 2-2 shows the SDRAM memory types and densities that are supported by the applications processor. . Table 2-2.
System Memory Interface 2.5 SDRAM Address Mapping SDRAM Address Mapping is shown in Table 2-3 and Table 2-4. Table 2-3.
System Memory Interface Table 2-4.
System Memory Interface Memory types are programmable through the memory interface configuration registers. Six chip selects control the static memory interface, nCS<5:0>. All are configurable for nonburst ROM or Flash memory, burst ROM or Flash, SRAM, or SRAM-like variable latency I/O devices. The variable latency I/O interface differs from SRAM in that it allows the data ready input signal (RDY) to insert a variable number of memory-cycle-wait states.
System Memory Interface Table 2-6. BOOT_SEL Definitions (Sheet 2 of 2) BOOT_SEL Boot From . . . 2.6.3 2 1 0 1 0 1 1 16-bit Synchronous Mask ROM (64 Mbits) 1 1 0 2 16-bit Synchronous Mask ROMs = 32-bits (64 Mbits each) 1 1 1 1 16-bit Synchronous Mask ROM (64 Mbits) SRAM / ROM / Flash / Synchronous Fast Flash Memory Options Table 2-7 contains the AC specification for SRAM / ROM / Flash / Synchronous Fast Flash. Table 2-7.
System Memory Interface data has been latched, the address may change on the next rising edge of MEMCLK or any cycles thereafter. The nOE or nPWE signal de-asserts one MEMCLK after data is latched. Before a subsequent data beat, nOE or nPWE remains deasserted for RDN+1 memory cycles. The chip select and byte selects, DQM[3:0], remain asserted for one memory cycle after the burst’s final nOE or nPWE deassertion.
System Memory Interface Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 2 of 2) MEMCKLK Symbol Description 99.5 118.0 132.7 147.5 165.9 Units Notes tvlioDSW MD(31:0), DQM(3:0) write data setup to nPWE asserted 10 8.5 7.5 6.8 6 ns, 1 tvlioDSWH MD(31:0), DQM(3:0) write data setup to nPWE de-asserted 20 17 15 13.6 12 ns, 2 tvlioDHW MD(31:0), DQM(3:0) hold after nPWE de-asserted 10 8.5 7.5 6.
System Memory Interface Figure 2-4.
System Memory Interface Figure 2-5. Expansion Card External Logic for a One-Socket Configuration PXA250 Socket 0 MD<15:0> D<15:0> DIR nOE RD/nWR GPIO nPCD0 nCD<1> GPIO PSKTSEL nPCD1 nCD<2> PRDY_BSY0 PADDR_EN0 RDY/nBSY GPIO GPIO MA<25:0> A<25:0> nPWE nWE nPREG nREG nCE<2:1> nOE nIOR nIOW nPCE<2:1> nPOE nPIOR nPIOW 5V to 3.3V nWAIT nPWAIT 5V to 3.3V nIOIS16 nIOIS16 Table 2-9.
System Memory Interface Table 2-9. Card Interface (PCMCIA or Compact Flash) AC Specifications (Sheet 2 of 2) MEMCKLK Symbol Description 99.5 118.0 132.7 147.5 165.9 Units Notes tcardDH MD(31:0) hold after nPWE, nPOE, nPIOW, or NPIOR de-asserted 10 8.5 7.5 6.8 6 ns, 1 tcardCMD nPWE, nPOE, nPIOW, or nPIOR command assertion 30 25.5 22.5 20.4 18 ns, 1 NOTE: 1. These numbers are minmums. They can be much larger based on the programmable Card Interface timing registers. 2.6.
System Memory Interface Figure 2-6.
System Memory Interface Figure 2-7.
System Memory Interface 2.7 System Memory Layout Guidelines 2.7.1 System Memory Topologies (Min and Max Simulated Loading) Figure 2-8, Figure 2-9, Figure 2-10, and Figure 2-11 are the topologies that where simulated to develop the trace length recommendations in Section 2.7.2. These topologies are for reference only. Figure 2-8. CS, CKE, DQM, CLK, MA minimum loading topology CS, CKE, DQM, CLK, MA SDRAM Figure 2-9.
System Memory Interface Figure 2-11. MD maximum loading topology SDRAM SDRAM MD AUX 2.7.2 AUX AUX AUX System Memory Recommended Trace Lengths Table 2-10 details the minimum and maximum trace lengths that were simulated for the applications processor. These trace lengths are not the absolute trace lengths that will work given the loading conditions. The trace lengths in Table 2-10 are measured from the applications processor to the individual component pins.
3 LCD Display Controller This chapter describes sample hardware connections from the PXA250 applications processor to various types of LCD controllers. Active (TFT) as well as passive (DSTN) displays are discussed as well as single and dual panel displays. These should not be considered the only possible ways to connect an LCD panel to the PXA250 applications processor, but should serve as a reference to assist with hardware design considerations.
LCD Display Controller Table 3-1. LCD Controller Data Pin Utilization (Sheet 2 of 2) Color/ Monochrome Panel Color Single/ Dual Panel Dual Double-Pixel Mode Screen Portion Pins Top L_DD<7:0> Bottom L_DD<15:8> N/A NOTE: 1. Double pixel data mode (DPD)=1. For passive displays, the pins described in Table 3-2 are required connections between the PXA250 applications processor and your LCD panel. Table 3-2.
LCD Display Controller Figure 3-1. Single Panel Monochrome Passive Display Typical Connection D0 D1 D2 D3 L_DD0 - Top left L_DD1 L_DD2 L_DD3 LCD Display PXA250 Processor L_PCLK L_LCLK L_FCLK L_BIAS 3.2.1.2 Pixel_Clock Line_Clock Frame_Clock Bias Passive Monochrome Single Panel Displays, Double-Pixel Data Figure 3-2 shows typical connections for a single-panel-monochrome passive display using double-pixel data mode. Figure 3-2.
LCD Display Controller Figure 3-3. Passive Monochrome Dual Panel Displays Typical Connection L_DD0 - Top left for upper panel L_DD1 L_DD2 L_DD3 PXA250 Processor L_PCLK L_LCLK L_FCLK L_BIAS L_DD4 - Top left for lower panel L_DD5 L_DD6 L_DD7 3.2.1.4 DU_0 DU_1 DU_2 DU_3 Pixel_Clock Line_Clock Frame_Clock Bias DL_0 DL_1 DL_2 DL_3 Upper Panel LCD Display Lower Panel Passive Color Single Panel Displays Figure 3-4 is a typical single-panel-color passive display connection. Figure 3-4.
LCD Display Controller Figure 3-5. Passive Color Dual Panel Displays Typical Connection L_DD0 L_DD1 L_DD2 L_DD3 L_DD4 L_DD5 - Top left Blue for upper panel L_DD6 - Top left Green for upper panel L_DD7 - Top left Red for upper panel DU_0 DU_1 DU_2 DU_3 DU_4 DU_5 DU_6 DU_7 Upper Panel PXA250 Processor L_PCLK L_LCLK L_FCLK L_BIAS L_DD8 L_DD9 L_DD10 L_DD11 L_DD12 L_DD13 - Top left Blue for lower panel L_DD14 - Top left Green for lower panel L_DD15 - Top left Red for lower panel 3.
LCD Display Controller Table 3-3. Active Display Pins Required PXA250 Pin LCD Panel Pin PIn Type1 Definition L_DD<15:0> R<4:0>,G<5:0>, B<4:0> Output Data lines used to transmit the 16 bit data values to the LCD display. L_PCLK Clock Output Pixel Clock - used by the LCD display to clock the pixel data into the line shift register. In active mode this clock transitions constantly.
LCD Display Controller Note: This example shows 6 red, 6 green and 6 blue bits on the LCD panel. However, different active display panels might have more or different data lines. Consult the LCD panel manufacturer’s datasheet for the actual data lines. Figure 3-6. Active Color Display Typical Connection L_DD0 L_DD1 L_DD2 L_DD3 L_DD4 - MSB of Blue L_DD5 L_DD6 L_DD7 L_DD8 L_DD9 L_DD10 - MSB of Green PXA250 Processor L_DD11 L_DD12 L_DD13 L_DD14 L_DD15 - MSB of Red L_PCLK L_LCLK L_FCLK L_BIAS 3.
LCD Display Controller Table 3-4. PXA250 LCD Controller Ball Positions (Sheet 2 of 2) Pin Name Ball Position L_DD12 A3 L_DD13 A2 L_DD14 C3 L_DD15 B3 L_FCLK E8 L_LCLK D8 L_PCLK B8 Bias A8 3.5 Additional Design Considerations 3.5.1 Contrast Voltage Many displays, both active and passive, include a pin for adjusting the display contrast voltage. This is a variable analog voltage that is supplied to the panel via an voltage source on the system board.
LCD Display Controller However, typical transfer rates are considerably less than 83 Mhz. For example, an 800x600 color active display running at 75 Hz requires a transfer rate of approximately 36 MHz. To determined this, calculate the number of pixels (800 x 600 = 480,000) and multiply by the screen refresh rate (75 Hz). Since active panels replace 1 pixel of data with every clock cycle this determines the final transfer rate.
LCD Display Controller 3-10 PXA250 and PXA210 Applications Processor Design Guide
4 USB Interface 4.1 Self Powered Device Figure 4-1 shows the USB interface connection for a self-powered device. The 0 ohm resistors are optional, and if not used, then connect USB UDC+ directly to the device UDC+ and connect USB UDC- directly to device UDC-. The device UDC+ and UDC- pins match the impedance of a USB cable, 90 ohms, without the use of external series resistors.
USB Interface detected. When an interrupt occurs, software must read the GPIOn pin to determine if the cable is connected or not. GPIOn is 1 if the cable is connected or 0 if the cable is disconnected. If a USB connect is detected, then software enables the UDC peripheral and drives a 1 onto the GPIOx pin to indicate to the host PC a fast USB device is connected.
5 MultiMediaCard (MMC) The MultiMediaCard (MMC) is a low cost data storage and communication media. The MMC supports the translation protocol from a standard MMC or Serial Peripheral Interface (SPI) bus to an application bus. The MMC controller in the applications processor is compliant with The MultiMediaCard System Specification, Version 2.1. The only exception is one and three byte data transfers are not supported. The MMC controller is capable of communicating with a card in MMC or SPI mode.
MultiMediaCard (MMC) 5.1.2 How to Wire Notice in the example schematic (Figure 5-1, “Applications Processor MMC and SDCard Signal Connections” on page 5-3) an SDCard socket is used. The signals on the socket are defined in Table 5-2. Table 5-2.
MultiMediaCard (MMC) Figure 5-1. Applications Processor MMC and SDCard Signal Connections DC3P3V J10 R147 Bottom Mount DAT2 SA_MMCMD CD_DAT3 1 CMD 2 VSS1 3 6 7 R225 0K SA_MMDAT 8 DC3P3V DC3P3V DNI IF SD DNI IF SD 12 R227 47.5K CD COMM DNI IF MMC 100K VSS2 R150 11 0.
MultiMediaCard (MMC) Three other signals shown on the connector are COMM and the mechanical switches write protect (WP) and card detect (CD). WP and CD are both connected to COMM via a mechanical switch inside the socket when a device is inserted. Three other signals shown on the connector are COMM and the mechanical switches WP and CD.
MultiMediaCard (MMC) Warning: 5.1.3 Connecting VSS2 to something other than the power supply ground violates The MultiMediaCard System Specification, Version 2.1. Because the MMC specification does not state that VSS1 and VSS2 must be connected internal to the MMC device, the design in Figure 5-1 may not work with all MMC devices. Use caution when using the card detection method shown in Figure 5-1. Simplified Schematic Figure 5-2 shows another SDCard socket.
MultiMediaCard (MMC) 5.1.4 Pull-up and Pull-down Table 5-4 and Table 5-5 show the pull-up and pull-down resistors required for SDCard and MMC devices according to their respective specifications. Table 5-4. SDCard Pull-up and Pull-down Resistors Signal Min Max pull-up 10kΩ 100kΩ DAT0-DAT3 pull-up 10kΩ 100kΩ WP1 pull-up — — CMD Pull-up or Pull-down Remark Prevents bus floating Prevents bus floating Any value sufficient to prevent bus floating NOTE: 1.
6 AC97 The AC97 controller unit (ACUNIT) connects audio chips and codecs to the applications processor. It uses a six-wire interface to transmit and receive data from AC97 2.0 compliant codecs. The AC97 port is a bidirectional, serial PCM digital stream. A maximum of two codecs may be connected to the ACUNIT. 6.1 Schematics The schematics for an AC97 connection are shown in Figure 6-1. The primary codec supplies the 12.288 MHz clock to the AC97.
AC97 6.2 Layout Because of the analog/digital nature of the codecs, it is important that proper mixed-signal layout procedures be followed. Intel recommends you follow the layout recommendations given in your Codec datasheet. Some general recommendations are: • Use a separate power supply for the analog audio portion of the design. • Place a digital power/ground plane keep-out underneath the analog portion. Use a separate analog ground plane. You can create an island inside the keep-out.
I2C 7 The Inter-Integrated Circuit (I2C) bus interface unit lets the applications processor serve as a master and slave device residing on the I2C bus. The I2C bus is a serial bus developed by Philips Corporation consisting of a two-pin interface. SDA is the serial data line and SCL is the serial clock line. Using the I2C bus lets the applications processor interface to other I2C peripherals and microcontrollers for system management functions.
I2C 7.1.2 Digital-to-Analog Converter (DAC) Figure 7-1 shows the schematic for connecting the I2C interface to a Linear Technology micropower DAC. The DAC output is connected to the buck converter feedback path and is controlled by the I2C bus interface unit. The DAC can modify the voltage of the feedback path, which effects the processor core voltage. Figure 7-1. Linear Technology DAC with I2C Interface DC3P3V R165 1.
I2C . Figure 7-2. Using an Analog Switch to Allow a Second CF Card DC3P3V U26 MAX4547 SA_I2C_SCL SA_I2C_SDA SA_I2C_ENAB 8 COM_1 7 IN_7 4 COM_7 3 IN_2 V* 2 NC_1 1 NC_2 5 GND 6 CF_I2C_SCL CI_I2C_SDA AAAF A8750-01 7.1.4 Pull-Ups and Pull-Downs The I2C Bus Specification, available from Philips Corporation, states: The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter maximum permissible rise time for the Fast-mode I2C-bus.
I2C The actual value of the pull-up is system dependant and a guide is presented in the I2C Bus Specification on determining the maximum and minimum resistors to use when the system is intended for standard or fast-mode I2C bus devices. 7.2 Utilized Features The applications processor I2C bus interface unit is compatible with the two pin interface developed by Phillips Corporation. A complete list of features and capabilities can be found in the I2C Bus Specification.
8 Power and Clocking 8.1 Operating Conditions Table 8-1 shows voltage, frequency, and temperature specifications for the applications processor for four different ranges. The temperature specification for each range is constant; the frequency range is operation voltage dependent. On a prototype design, the VCC/PLL_VCC regulator should have a range from 0.85 V to 1.65 V. PLL_VCC and VCC must be connected together on the board or driven by the same supply. Table 8-1.
Power and Clocking 8.2 Electrical Specifications Table 8-2 provides the Absolute Maximum ratings for the applications processor. These parameters may not be exceeded or the part may be permanently damaged. Operation at Absolute Maximum Ratings is not guaranteed. Table 8-2. Absolute Maximum Ratings Symbol Description Min Max TS Storage Temperature -40° C 125° C VSS_O Offset Voltage between any two VSS pins (VSS, VSSQ, VSSN) -0.3 V 0.3 V -0.3 V 0.
Power and Clocking Since few systems operate at maximum loading, performance, and voltage, a more optimal system design requires more typical power consumption parameters. These parameters are important when considering battery size and optimizing regulator efficiency. Typical systems operate with fewer modules active and at nominal voltage and load.
Power and Clocking Table 8-3. Power Consumption Specifications (Sheet 2 of 2) Description Min1 Typical1 Max1 Power from VCCN Supply, High Range (PXA250 applications processor) — 115 mW 250 mW @3.3V Power from VCCN Supply, High Range (PXA250 applications processor) — 160 mW 440 mW PT_IDLE_H Total Power, IDLE Mode, High Range — 135mW — Symbol PVCCN_HB @2.
Power and Clocking Table 8-4. 32.768 kHz Oscillator Specifications (Sheet 2 of 2) Symbol tS_XT Description Stabilization Time Min Typical Max 2s — 10 s 20 MΩ — — Board Specifications RP_XT Parasitic Resistance, TXTAL/TEXTAL to any node CP_XT Parasitic Capacitance, TXTAL/TEXTAL, total — — 5 pF COP_XT Parasitic Shunt Capacitance, TXTAL to TEXTAL — — 0.4 pF To drive the 32.
Power and Clocking • Drive the PEXTAL pin with a digital signal that has a low level near 0 V and a high level near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 1 V per 100 ns. The maximum current drawn by the external clock source when the clock is at its maximum positive voltage should be about 1 mA. • Float the PXTAL pin or drive it complementary to the PEXTAL pin, using the same voltage level, slew rate, and input current restrictions.
Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs.
Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs.
Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 4 of 6) Pin Pin Count Alt_fn 1-(in) Alt_fn 2-(in) Alt_fn 1-(out) Alt_fn 2-(out) Signal Description and Comments Power Supply GP11 1 3.6 MHz 3.
Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs.
Power and Clocking Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 6 of 6) Pin Pin Count Alt_fn 1-(in) Alt_fn 2-(in) Alt_fn 1-(out) Alt_fn 2-(out) LDD[15] GP73 Signal Description and Comments Power Supply LCD data pin 15 1 VCCQ MBGNT memory controller grant GP74 1 LCD_FCL LCD Frame clock K VCCQ GP75 1 LCD_LCL LCD line clock K VCCQ GP76 1 LCD_PCL LCD Pixel clock K VCCQ GP77 1 LCD_AC BIAS LCD AC Bias VCCQ PXTAL 1 3.6Mhz Crystal input 0.8 * VCC PEXTAL 1 3.
Power and Clocking Note: If Hardware Reset is entered during Sleep Mode, the proper power-supply stabilization times and nRESET timing requirements indicated in Table 8-7, “Power-On Timing Specifications” on page 8-12 must be observed. Figure 8-1.
Power and Clocking Figure 8-2. Hardware Reset Timing tDHW_NRESET nRESET tDHW_OUT nRESET_OUT tDHW_OUT_A Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted or PXA250 enters Sleep Mode Table 8-8. Hardware Reset Timing Specifications Symbol Description tDHW_NRESET Minimum assertion time of nRESET tDHW_OUT_A Delay between nRESET Asserted and nRESET_OUT Asserted tDHW_OUT Delay between nRESET deasserted and nRESET_OUT deasserted 8.5.4 Min Typical Max 0.
Power and Clocking Table 8-9. GPIO Reset Timing Specifications Symbol Description Min Typical Max tA_GP[1] Minimum assert time of GP[1]1 in 3.6864 MHz input clock cycles 4 cycles — — tDGP_OUT_A Delay between GP[1] Asserted and nRESET_OUT Asserted in 3.
Power and Clocking Table 8-10. Sleep Mode Timing Specifications (Sheet 2 of 2) Symbol Description Min Typical Max tD_FAULT Delay between PWR_EN asserted and nVDD_FAULT deasserted — — 10 ms tDSM_OUT Delay between PWR_EN asserted and nRESET_OUT deasserted, OPDE Set 28.0 ms — 80 ms tDSM_OUT_O Delay between PWR_EN asserted and nRESET_OUT deasserted, OPDE Clear 10.35 ms — 10.5 ms 8.
Power and Clocking Table 8-12. Variable Latency I/O Interface AC Specifications (3.3 V) MEMCLK Frequency (MHz) Symbol Description Notes 99.5 118.0 132.7 147.5 165.9 Variable Latency IO Interface (VLIO) (Asynchronous) tvlioAS MA(25:0) setup to nCS asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 tvlioASRW MA(25:0) setup to nOE or nPWE asserted 10 ns 8.5 ns 7.5 ns 6.8 ns 6 ns 1 tvlioAH MA(25:0) hold after nOE or nPWE deasserted 10 ns 8.5 ns 7.5 ns 6.
Power and Clocking Table 8-14. Synchronous Memory Interface AC Specifications (3.
Power and Clocking Table 8-15. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (2.5 V) MEMCLK Frequency (MHz) Symbol Description Notes 99.5 118.0 132.7 147.5 165.
Power and Clocking Table 8-16. Variable Latency I/O Interface AC Specifications (2.5 V) MEMCLK Frequency (MHz) Symbol Description Notes 99.5 118.0 132.7 147.5 165.
Power and Clocking Table 8-18. Synchronous Memory Interface AC Specifications (2.
Power and Clocking • Provide power gating switches for the CF, LCD, backlight, RS-232, MMC, Radio, and audio amplifier subsystems • • • • • 8.7.1.1 Provide a high-efficiency 5.5 V supply rail for LCD and other devices Provide a high-efficiency 3.3 V supply rail for I/O and general system power Provide a high-efficiency 0.8 – 1.
Power and Clocking Figure 8-5. Example Form Factor Reference Design Power System Design LDO ON/OFF LDO ON/OFF MMC_VDD Audio AMP Audio_DC3P3V LDO ON/OFF 3.3V LDO ON/OFF LCD_DC3P3V LDO ON/OFF LCD_DC5V LDO ON/OFF 3.2V LDO ON/OFF CF_VDD LDO ON/OFF 3.3V LCD_DC4V LCD_DC15V Boost Converter MAX633 LCD_DC14V- LCD_DC11P7V- Boost Converter LTC1308A DC_5P5V LDO 3.2 V DC_3P3V LDO 3.3 V DC_CORE Buck Converter LTC1878 Wall Input Current Limited 8.7.2 Battery Charger LTC1730 battery 0.8 - 1.
Power and Clocking 8.7.4 I/O 3.3 V Power A simple LDO linear regulator supplies the 3.3V rail. The Analog Devices ADP3335 is chosen for its very low drop-out – 200 mV at 500 mA and 110 mV at 200 mA. So typically, the input cut-off voltage for this device is about 3.3 V + 0.11 V = 3.41 V. The power is drawn directly from the Li+ battery. For a 3.6 V battery, this device has a 82% efficiency. There are four zones of operation for the Li+ battery: • • • • 4.1 – 3.8 V zone 10% of the time; 3.7 – 3.
Power and Clocking 8-24 PXA250 and PXA210 Applications Processors Design Guide
9 JTAG/Debug Port 9.1 Description The JTAG/Debug port is essentially several shift registers, with the destination controlled by the TMS pin and data I/O with TDI/TDO. nTRST provides initialization of the test logic. JTAG is testable via the IEEE 1149.1. Many use JTAG to control the address/data bus for Flash programming. JTAG is also a hardware debug port. 9.2 Schematics All JTAG pins, except for nTRST and TCK, are directly connected.
JTAG/Debug Port 9.3 Layout Use the JTAG/Debug the port layout recommendations given in ARM’s application note, MultiICE System Design Considerations, Application Note 72. The recommended connector is a 2x10way, 2.54 mm pitch pin header, shown in Figure 9-1. If board space is critical, use a small form-factor receptacle with a smaller pitch. Then use a cable interface that has a wire “dongle” with a 2.54 mm pitch pin header on one end and the smaller pitch connector on the other.
SA-1110/Applications Processor Migration A The Intel® PXA250 an PXA210 applications processors represent the next generation follow-on to Intel® StrongARM* SA-1110 product. This appendix highlights the migration path needed to change an SA-1110 design to one that uses the applications processor.
SA-1110/Applications Processor Migration — Intel® XScale™ microarchitecture — Debugging - Cache attributes - Other Features - Conclusion A.1 SA-1110 Hardware Migration Issues A.1.1 Hardware Compatibility The majority of the features provided in the SA-1110 are also provided in the PXA250 applications processor. However, with the additional functionality of the PXA250 applications processor, the two devices are not pin compatible and cannot occupy the same socket.
SA-1110/Applications Processor Migration Table A-1.
SA-1110/Applications Processor Migration A.1.3 Power Delivery Although both products are tolerant to 3.3 V inputs and outputs, there is a difference in the supply voltage that drives the transistors of the microprocessor megacell. The PXA250 applications processor takes advantage of lower supply voltages to offer substantial power consumption savings. A design using SA-1110 has a supply voltage of 1.55 V to 1.75 V. The PXA250 applications processor is rated to 1.4 V maximum.
SA-1110/Applications Processor Migration You can program GPIO pins to generate various clocks in both the SA-1110 and the PXA250 applications processors. For example, these are often used in audio codec designs to generate clocks. The inter-relationships of some of these clocks have changed from the SA-1110 to the PXA250 applications processor. You may need to select different GPIO pins and program different configuration registers to provide similar functionality. A.1.
SA-1110/Applications Processor Migration A.2.1 Software Compatibility Because the PXA250 applications processor uses Intel® XScale™ microarchitecture, the PXA250 applications processor has a different pipeline length relative to the SA-1110. This effects code performance when migrating between the two devices varies because of the number of clock cycles needed for execution. Any application that relies on specific cycle counts, or has specific timing components, will show a difference in performance.
SA-1110/Applications Processor Migration You must choose memory clocks, LCD clock rates, audio clocks and interfaces, which GPIOs are actually connected to hardware, and many more. There are no easy solutions here, the device space of the PXA250 applications processor is very diverse and a number of selections must be made in software to select your particular hardware functionality. All software that controls registers will need to be updated.
SA-1110/Applications Processor Migration A.3.1 Intel® XScale™ Microarchitecture The PXA250 applications processor is a system on a chip that includes Intel’s new microprocessor megacell. This includes Intel® Superpipelined Technology and a new optimized cache architecture that allows program execution to continue despite data cache misses.
SA-1110/Applications Processor Migration Additional software is required to access these benefits. A similar story is true for AC’97, I2C, GPIOs, MMC and others. The benefits are substantial, but new hardware and software will be necessary to effectively use the PXA250 applications processor. A.3.5 Conclusion Although most application software will migrate unchanged between SA-1110 and the PXA250 applications processors, the underlying microarchitectures are radically different.
SA-1110/Applications Processor Migration A-10 PXA250 and PXA210 Applications Processors Design Guide
Example Form Factor Reference Design Schematic Diagrams B B.1 Notes The example form factor reference design schematics in this appendix have known issues and assumptions that need to be assessed for each board design. This appendix documents the issues that have been discovered and provides revision data for the schematics. This appendix also points out some of the design specific assumptions that were made in designing this board.
A B C D 8 8 1 2-3 4 5 6 7 8 9 10 11 12 13 14 15 16 Copyright 2002 Intel Corporation 5 4 Description Example Form Factor Reference Design for PXA250 6 3 2 7 6 5 4 3 Date: Size B 2 Tuesday, February 05, 2002 PXA250 Processor Reference Design Cover Sheet PXA250 Processor SDRAM, System Configuration Register Intel Flash Memory (BGA) Buffer, CPLD, Board Control Register Transceivers Audio Codec, Audio AMP Headset Jack, Microphone, Stereo Jack, Speaker, Dual Axis Accelerometer, IrDA, USB B
A B C D 8 SA_A21 SA_A22 SA_A23 SA_A24 SA_A25 {4,5,7} {4,5,7} {4,5,7} {4,5,7} {6,7} MMC_WP MMC_CS0 {11,13} nMMC_DETECT {11} {11} SA_MMCCLK {11} SA_MMDAT {11} SA_MMCMD {11} RADIO_RXD_C {11} {11} RADIO_DCD {11} RADIO_DSR {11} RADIO_DTR RADIO_RI SA_A20 {4,5,7} {11} SA_A19 SA_A15 SA_A16 {4,5,7} {4,5,7} SA_A18 SA_A14 {4,5,7} {4,5,7} SA_A13 {4,5,7} {4,5,7} SA_A12 {4,5,7} SA_A17 SA_A11 {4,5,7} {4,5,7} SA_A9 SA_A10 {5,7} SA_A8 {5,7} {4,5,7} SA_A7 {5,7} SA_A4
A B DC3P3V 3 4 S1 MR VCC 8 GND RESET MAX811TEUS-T U3 {13} nVDD_FAULT RESET 7A 1 2 3 4 3.6864Mhz Y4 681 R271 RESET Y2 VIN MAX6328 GND U2 7 {12} 1 1 DC_PLL DC3P3V {15} {15} {10,11,15} 6 nRESET_IN DC3P3V DC3P3V DC_CORE BOOT_SEL_0 BOOT_SEL_1 BOOT_SEL_2 {12,13} SA_PWR_EN {12} PLL_SENSE 3 32.768KHZ 2 MAX6328XR27-T-SC 2 1 DNI Y1 3.
A B C SA_A10 SA_A11 SA_A12 SA_A13 SA_A14 SA_A15 SA_A16 SA_A17 SA_A18 SA_A19 SA_A20 SA_A21 SA_A24 DC3P3V 8 {2,7} SA_SDCLK_1 {2,6} SA_SDCKE_1 {2,5,7} SA_A23 {2,5,7} SA_A22 {2,7} SA_DQM_2 {2,7} SA_DQM_3 {2,7} SA_nSDCS_0 {2,5,6,7,10} SA_nWE {2,5,6,7} SA_nSDCAS {2,6,7} SA_nSDRAS {2,5,7} {2,5,7} {2,5,7} {2,5,7} {2,5,7} {2,5,7} {2,5,7} {2,5,7} {2,5,7} {2,5,7} {2,5,7} {2,5,7} {2,5,7} SA_SDCLK_1 SA_SDCKE_1 SA_A23 SA_A22 SA_DQM_0 SA_DQM_1 C19 DC3P3V {2,7} {2,6} {2,5,7} {2,5,7} {2,7} {2,7} SA_nSDCS_0 SA_n
A B C 8 {2,4,6,7} SA_nSDCAS {2,15} SA_SDCLK_0 0 R56 0 R54 DNI {6} 7 DNI CS_AWS nFLASH_BOOT_CS SA_nOE SA_nWE FLASH_nRP {2,7} {2,4,6,7,10} {13} 0 DC3P3V R53 D {2,6} {2,6} {2,7} {2,7} {2,7} {2,7} {2,7} {2,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} {2,4,7} 0 SA_A2 SA_A3 SA_A4 SA_A5 SA_A6 SA_A7 SA_A8 SA_A9 SA_A10 SA_A11 SA_A12 SA_A13 SA_A14 SA_A15 SA_A16 SA_A17 SA_A18 SA_A19 SA_A20 SA_A21 SA_A22 SA_A23 SA_A24 {2,6}
A B C {15} {2,4,7} {2} {2,4,5,7} CF_nBUS_ON SA_SDCLK_2 nNEP_FLASH_CS XCV_DATA_DIR CPLD1_TDI MBGNT_CF_IRQ SWAP_FLASH SA_nSDRAS SA_nSDCS_2 SA_nSDCAS 8 SA_A3 SA_A2 SA_A1 SA_A0 CF_nPWAIT CF_nIOIS16 SA_nPREG SA_nPCE_1 {7} nVX_CF_OE {3,10,11,13} JTAG_TMS {10,15} nNEP_REG_CS {2,4,5,7,10} SA_nWE {7} nXCV_DATA_OE {7} XCV_ADD_DIR {10,15} CF_IRQ_LVL2OE {3,11,13,15} nRESET_OUT {5} nFLASH_BOOT_CS {2} {15} {7} {10,11} {3,15} DC3P3V C25 {7} nVX_CF_OE {2,5} {2,5} {2} {2} {10} {10} {2,15} {2,15} SA_nSDCS_2
A B C SA_nOE SA_A10 SA_A9 SA_A8 SA_A7 SA_A6 SA_A5 SA_A4 {2,5} {2,4,5} {2,5} {2,5} {2,5} {2,5} {2,5} {2,5} 8 {2,4} SA_SDCLK_1 {2,6} SA_A25 {2,4,5} SA_A24 {2,4,5} SA_A23 {2,4,5} SA_A22 {2,4,5} SA_A21 {2,4,5} SA_A20 {2,4,5} SA_A19 {2,4,5,6,10} SA_nWE {2,4} SA_DQM_0 {2,4} SA_DQM_1 {2,4} SA_DQM_2 {2,4,6} SA_nSDRAS {2,4} SA_DQM_3 {2,4,5,6} SA_nSDCAS {2,4} SA_nSDCS_0 SA_A18 SA_A17 SA_A16 SA_A15 SA_A14 SA_A13 SA_A12 SA_A11 {2,4,5} {2,4,5} {2,4,5} {2,4,5} {2,4,5} {2,4,5} {2,4,5} {2,4,5} 4 10 15 21 28 34 39
A B C CF_AUD {9} AUDIO3P3V {11} RADIO_SPKRP {10} {13,15} SYSCLK 8 R282 SA_BITCLK {2} SA_SYNC {2} SA_SDATA_OUT {2} {2} SA_SDATA_IN {14} {14} {14} TSPX R101 1 R104 1 2 TSMY TSMX TSPY R100 1 1 4.7UF 4.7UF C131 {14} 10K 2 C141 + 2 J1 1 {2} SA_nAC97_RESET R14 2 1 C57 0 47.5 0.1UF C58 R71 DNI 4.7UF D 0 R93 1 J2 + {9} 7 0 + MICGND MICIN 47.5 R73 R91 {9,11} C54 C43 C53 C74 22pF 4.7UF C72 24.
A B {8} 1 2 8 AUDIO3P3V C80 C R117 J5 0 Microphone R110 0.1UF 2 1 0.1UF C77 3 2 1 8 MICGND R106 2 1 C79 TIP SHA 4.7UF 2 2.5mm COM T2 ST 7 LCC8 YOUT XOUT YCAP XCAP ADXL202E Dual Axis Accelerometer VDD U20 4 5 6 7 R123 100K R120 100K 0 3 5 1 MICIN RING SHB GND R149 HEADSET JACK J4 Dual Axis Acelerometer {8,11} 1.5K 4 + + {8} 6 + RADIO_MICP {11} L_OUT_A L_OUT_B Headset Jack C81 237K MIC_PWR C3 10 0.
A B C CF_nPWAIT {6} RS232_ON {6} 8 SA_FF_RXD SA_FF_DCD SA_FF_DSR SA_FF_RI SA_FF_CTS {2,15} {2} {2} {2} {2} {2,15} SA_FF_TXD {2} SA_FF_RTS {2} SA_FF_DTR 0.1UF C89 0.
A B C 8 J10 CHECK !! DAT2 DAT1 DAT0 VSS2 CLK VDD VSS1 CMD CD_DAT3 Bottom Mount {13} DC3P3V 8 7 6 5 4 3 2 1 9 MMC_ON 7 DC5P5V {2} 47.5K R150 3 2 1 EN GND LE33 DNI IF SD DNI SA_TDO JTAG_nTRST nRESET_IN 6 + DNI IF MMC DNI IF SD DC3P3V MMC_PWR {3,10} {3} 4 0 R225 DNI IF MMC {3,10,15} BYP 5 {2} MMC_PWR SA_MMCMD CARD Selection Resistors and Values RES SD MMC R226 DNI 0 R227 DNI 100K R225 0 DNI R228 100K DNI C91 MIC5207-3.3BM5 3.
A B C {3,8,10,11,13,14} VBATT DNI R169 8 150K 100K R157 R161 22UF C102 47.5K R158 4 6 8 7 3 2 1 ADP3335ARM-3.3 LFE GND NR 4 5 OUT_3 OUT_2 OUT_1 BYP ADP3335 LEAA SHUTDOWN IN_2 IN_1 U32 EN GND MIC5207-BM5 ADJ LDO REG 180ma VIN VOUT U31 7 1 3 4 6 3 2 1 5 1308A VC SHDN LBI LBO FB SW 7 8 2 5 + DC3P3V {3,8,10,11,13} VBATT LT1308A GND VIN DC3P3V 11-TM104-NP 976K 6 R163 1 2 3 4 5 6 7 8 9 10 0.
A B 8 7 5 6 3 4 1 2 DC3P3V 100K R171 100K C105 4A 4Y 5A 5Y 6A 6Y VDD SN74HCT04PWR GND 3A 3Y 2A 2Y 1A 1Y SN74HCT04D Hex Inv U34 {10} {3} CF_nCD2 11 10 13 12 14 9 8 L_PCLK {14} LCD_ENAB {14} LCD_NCLK {14} LCD_B5 {14} LCD_B2 {14} LCD_B3 {14} LCD_B4 {3} nVDD_FAULT {15} VDD_FAULT 0.1UF R214 0.1UF C107 R213 0.
A B C D LCD_R2 LCD_R4 LCD_G1 LCD_G3 LCD_G5 LCD_B0 LCD_B2 LCD_B4 {13} {13} {13} {13} {13} {13} {13} {13} 8 LCD_DC3P3V LCD_ENAB LCD_R0 {13} {13} LCD_NCLK {13} L_DC1P15V L_DC2P1V L_DC3P3V R178 R183 R188 R193 L_DC3P1V 17.4K L_DC1P9V 30.
A B C D 8 VX_SDCLK_1 {7} VX_A22 VX_A24 {7} {7} VX_nSDCS_0 VX_nSDCAS VX_nSDRAS BOOT_SEL_0 SA_SDCKE_0 BOOT_SEL_1 VX_SDCKE_1 VX_A8 VX_A10 VX_A12 VX_A14 VX_A16 VX_A18 VX_A20 {7,10} {7,10} {7} {7} {7} {7} {7} {7} {7} {7} {3} {2} {3} {6} VX_A2 VX_A4 VX_A6 {6,10} {7,10} {7,10} VX_D26 VX_D28 VX_D30 {7} {7} {7} {3,9} {2,10,12} {2,10,12} DVAL_1 DVAL_0 DREQ_0 8 {3,10} GPIO_0 USB_WAKE SA_I2C_SDA SA_I2C_SCL {11} {11} {11} SA1111_IRQ_CF_BVD1 {10,12} IN_PWR {2,6} SA_nIOIS16 {2,6} SA_nPWAIT {2} SA_PSK
7 6 5 4 4 3 3 PXA250 Processor Reference Design 2 Sheet 16 1 1 of 16 Rev 2.07 Pg.
Example Form Factor Reference Design Schematic Diagrams B-18 PXA250 and PXA210 Applications Processors Design Guide
BBPXA2xx Development Baseboard Schematic Diagram C.1 C Schematic Diagram The BBPXA2xx schematic is on the following pages.
Top level block diagram Processor Card Connector Data Buffers/Transceivers Data Buffers/Transceivers Address BUFFERS/TRANSCEIVERS SPX ADDRESS BUFFERS CONTROL BUFFERS/TRANSCEIVERS X ADDRESS BUFFERS BFR ADDRESS BUFFERS SRAM FLASH ROM REGISTER & CONTROL HEX DISPLAY HIGH HEX DISPLAY LOW LEDs & HEX SWITCHES 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Function 2 Page SA-1111 USB KB/MS BUFFER CONTROL LOGIC LCD BUFFERS IrDA & FF SERIAL & USB CS4201 CODEC UCB1400 CODEC BB TOUCH SCREEN & G
BBPXA2xx Development Baseboard Schematic Diagram C-40 PXA250 and PXA210 Applications Processors Design Guide
PXA250 Processor Card Schematic Diagram D.1 D Schematic Diagram The DCPXA250 processor card schematic is on the following pages.
PAGE PROCESSOR --- PXA250 32-BIT SDRAM CONNECTOR (MEMORY and I/O SIGNALS) CLOCKS JTAG CONNECTOR & PLL and CORE VOLTAGE REGULATORS VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER Visibility Bus Terminators 2 3 4 5 6 7 8 9-11 FUNCTION TABLE OF CONTENTS DCPXA250 Processor Card 32-bit version
PXA210 Processor Card Schematic Diagram E.1 E Schematic Diagram The DCPXA210 processor card schematic is on the following pages.
PAGE PROCESSOR --- PXA210 16-BIT SDRAM CONNECTOR (MEMORY and I/O SIGNALS) CLOCKS JTAG CONNECTOR & PLL and CORE VOLTAGE REGULATORS VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER Visibility Bus Terminators and Signal MUX 2 3 4 5 6 7 8 9-13 FUNCTION TABLE OF CONTENTS DCPXA210 Processor Card 16-bit version
PXA210 Processor Card Schematic Diagram PXA250 and PXA210 Applications Processors Design Guide E-3
