Intel® 82854 Graphics Memory Controller Hub (GMCH) Datasheet Revision 2.
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Contents Contents 1.0 Introduction.................................................................................................................................... 11 1.1 1.2 1.3 2.0 Intel® 82854 GMCH Overview....................................................................................................... 21 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 System Architecture............................................................................................................ 21 2.1.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.9 4.10 4 4.8.4 PCI Status Register ............................................................................................... 53 4.8.5 RID – Register Identification .................................................................................. 54 4.8.6 SUBC – Sub Class Code Register ........................................................................ 54 4.8.7 BCC – Base Class Code Register .................................................
Contents 4.11 5.0 Intel® 82854 GMCH System Address Map..................................................................................111 5.1 5.2 5.3 5.4 6.0 4.10.9 SVID – Subsystem Vendor Identification Register................................................. 97 4.10.10 ID – Subsystem Identification Register .................................................................. 97 4.10.11 CAPPTR – Capabilities Pointer Register ............................................................... 98 4.10.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 6.5 7.0 Power and Thermal Management ............................................................................................... 147 7.1 7.2 7.3 7.4 8.0 Strapping Configuration .................................................................................................... 151 Ballout and Package Information................................................................................................. 153 9.1 9.
Contents Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Intel® 854 Chipset system block diagram (Native Graphic mode) ............................................. 16 Configuration Address Register.................................................................................................. 45 Configuration Data Register ....................................................................................................... 47 PAM Registers..................................................................
Intel® 82854 Graphics Memory Controller Hub (GMCH) 29 30 31 32 33 34 35 36 8 Relation of DBI Bits to Data Bits ............................................................................................... 123 Data Bytes on DDR DIMM Used for Programming DRAM Registers....................................... 125 Dual Display Usage Model (Native Graphic Mode only) .......................................................... 134 DVO Control Data Bits............................................................
Contents Revision History Date Revision Description March 2005 1.0 Initial release of this document. June 2005 2.0 Add support for Genuine Intel® Processor at 1.2 GHz and Genuine Intel® Processor at 1.5 GHz technology.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 10 D15343-003
Introduction 1.0 Introduction This document is the datasheet for the Intel® 82854 Graphics Memory Controller Hub (GMCH). 1.1 Overview The Intel® 854 chipset is a combination of the Intel® 82854 Graphics Memory Controller Hub (GMCH) (Graphics Memory Controller Hub) and ICH4-M (I/O Controller Hub). The Intel 854 Chipset is designed to work with the Ultra Low Voltage (ULV) Intel® Celeron® M processor at 600 MHz with 512 KB of on-die L2 cache on an 0.13 micron process, Genuine Intel® Processor at 1.
Intel® 82854 Graphics Memory Controller Hub (GMCH) System Interrupts • • • • Supports Intel 8259 and front side bus interrupt delivery mechanism Supports interrupts signaled as upstream memory writes from PCI and Hub interface MSI sent to the CPU through the system bus IOxAPIC in ICH4-M provides redirection for upstream interrupts to the system bus Video Stream Decoder • • • • • Hardware motion compensation for MPEG2 All video format decoder (18 ATSC video formats) supported Dynamic Bob and Weave suppor
Introduction Display • Analog display support — 350-MHz integrated 24-bit RAMDAC that can drive a standard progressive scan analog monitor with pixel resolution up to 1600x1200 at 85 Hz and up to 2048x1536 at 75 Hz • Dual independent pipe support — Concurrent: different images and display timings on each display device — Simultaneous: same images and display timings on each display device • DVO (DVOB and DVOC) support — Digital video out ports DVOB and DVOC with 165-MHz dot clock on each 12-bit interface
Intel® 82854 Graphics Memory Controller Hub (GMCH) • 3D graphics engine — 3D setup and render engine — Enhanced Hardware Binning Instruction Set supported — Zone rendering — High quality performance texture engine — Viewpoint transform and perspective divide — Triangle lists, strips and fans support — Indexed vertex and flexible vertex formats — Pixel accurate fast scissoring and clipping operation — Backface culling support — Direct 3D support — Anti-Aliased lines support — Sprite points support — Provide
Introduction — Dithering — Line and full-scene anti-aliasing — 16- and 24-bit Z buffering — 16- and 24-bit W buffering — 8-bit Stencil buffering — Double and triple render buffer support — 16- and 32-bit color — Destination alpha — Vertex cache — Optimal 3D resolution supported — Fast Clear support — ROP support Hub Interface to ICH4-M • 266-MB/s point-to-point Hub interface to ICH4-M • 66-MHz base clock Graphic Power Management • Dynamic Frequency Switching • Memory Self-Refresh during C3 • Intel Display
Intel® 82854 Graphics Memory Controller Hub (GMCH) Package 732-pin Micro-FCBGA (37.5 x 37.5 mm) Figure 1. Intel® 854 Chipset system block diagram (Native Graphic mode) Intel® Celeron® M Processor VGA 400 MHz 512 MB DDR Memory Down 333 MHz Intel® 82854 (GMCH) VGA DVO TV ADD Slot IDE 6 USB LAN PHY USB 2.0/1.
Introduction 1.2 Terminology Table 1.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 18 Intel 82801DBM ICH4-M The component contains the primary PCI interface, LPC interface, USB 2.0, ATA-100, AC’97, and other I/O functions. It communicates with the Intel® 82854 GMCH over a proprietary interconnect called the Hub interface. Throughout this datasheet, the Intel 82801DBM ICH4-M component will be referred to as the ICH4-M IPI Inter Processor Interrupt LCD Liquid Crystal Display MSI Message Signaled Interrupts.
Introduction 1.3 Reference Documents Table 2. Reference Documents D15343-003 Document Location Intel® Celeron® M Processor Datasheet http://www.intel.com/design/mobile/datashts/300302.htm Ultra Low Voltage Intel(R) Celeron(R) M Processor at 600 MHz Addendum to the Intel(R) Celeron(R) M Processor Datasheet http://developer.intel.com/design/intarch/datashts/ 301753.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 20 D15343-003
Intel® 82854 GMCH Overview 2.0 Intel® 82854 GMCH Overview 2.1 System Architecture The Intel® 82854 GMCH includes a processor interface, DDR SDRAM interface, display interface, and Hub interface. Combined with the ULV Intel® Celeron® M Processor or Genuine Intel® Processor, and an ICH4M, it provides many of the functions required to deliver the features below: • • • • • 2.1.1 Overall system software platform Graphic overlay function for the GUI and 3-D graphics for gaming.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 2.2 Processor Host Interface The Intel® 82854 GMCH supports the Intel Celeron M Processor, and Genuine Intel Processor. Key features of the front side bus (FSB) are: • • • • • • • • • • • 2.3 Support for a 400-MHz system bus frequency. Source synchronous double pumped address (2X) Source synchronous quad pumped data (4X) Front side bus interrupt delivery Low voltage swing Vtt (1.05 ~ 1.
Intel® 82854 GMCH Overview The GMCH system memory architecture is optimized to maintain open pages (up to 16-KB page size) across multiple rows. As a result, up to 16 pages across four rows is supported. To complement this, the GMCH will tend to keep pages open within rows, or will only close a single bank on a page miss. The GMCH supports only four bank memory technologies. 2.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 2.6 Hub Interface A proprietary interconnect connects the GMCH to the ICH4-M. All communication between the GMCH and the ICH4-M occurs over the Hub interface 1.5. The Hub interface runs at 66 MHz (266-MB/s). 2.7 Address Decode Policies Host initiated I/O cycles are positively decoded to the GMCH configuration space and subtractively decoded to the Hub interface.
Intel® 82854 GMCH Overview 2.8 GMCH Clocking The GMCH has the following clock input/output pins: • 400-MHz, spread spectrum, low voltage differential BCLK, BCLK# for front side bus (FSB) • 66-MHz, 3.3-V GCLKIN for Hub interface buffers • Six pairs of differential output clocks (SCK[5:0], SCK[5:0]#), 200/266 MHz, 2.5 V for system memory interface • 48-MHz, non-Spread Spectrum, 3.3-V DREFCLK for the Display Frequency Synthesis • 8-MHz or 66-MHz, Spread Spectrum, 3.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 2.9 System Interrupts The GMCH supports both the legacy Intel 8259 Programmable Interrupt delivery mechanism and the Intel Celeron M processor FSB interrupt delivery mechanism. The serial APIC Interrupt mechanism is not supported. The Intel 8259 Interrupt delivery mechanism support consists of flushing in bound Hub interface write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the Hub interface.
Signal Description 3.0 Signal Description This section describes the Intel® 82854 GMCH signals. These signals are arranged in functional groups according to their associated interface. The following notations are used to describe the signal type. Notation Description I Input pin O Output pin I/O Bi-directional Input/Output pin The signal description also includes the type of buffer used for the particular signal: Note: D15343-003 Buffer Description AGTL+ Open Drain AGTL+ interface signal.
Intel® 854 Graphics Memory Controller Hub (GMCH) 3.1 Host Interface Signals Table 5. Host Interface Signal Descriptions Signal Name Type Description ADS# I/O AGTL+ Address Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. The GMCH can assert this signal for snoop cycles and interrupt messages. BNR# I/O AGTL+ Block Next Request: Used to block the current request bus owner from issuing a new request.
Signal Description DRDY# I/O Data Ready: Asserted for each cycle that data is transferred. AGTL+ HA[31:3]# I/O AGTL+ Host Address Bus: HA[31:3]# connects to the CPU address bus. During processor cycles the HA[31:3]# are inputs. The GMCH drives HA[31:3]# during snoop cycles on behalf of Hub interface. HA[31:3]# are transferred at 2x rate. Note that the address is inverted on the CPU bus. HADSTB[1:0]# I/O AGTL+ Host Address Strobe: HA[31:3]# connects to the CPU address bus.
Intel® 854 Graphics Memory Controller Hub (GMCH) RS[2:0]# 30 O AGTL+ Response Status: Indicates the type of response according to the following the table: RS[2:0]# Response type 000 Idle state 001 Retry response 010 Deferred response 011 Reserved (not driven by GMCH) 100 Hard Failure (not driven by GMCH) 101 No data response 110 Implicit Write back 111 Normal data response D15343-003
Signal Description 3.2 DDR SDRAM Interface Table 6. DDR SDRAM Interface Descriptions Signal Name SCS[3:0]# Type O SSTL_2 Description Chip Select: These pins select the particular DDR SDRAM components during the active state. NOTE: There is one SCS# per DDR-SDRAM Physical DDR DIMM device row. These signals can be toggled on every rising System Memory Clock edge (SCMDCLK).
Intel® 854 Graphics Memory Controller Hub (GMCH) O SMAB[5,4,2,1] SSTL_2 O SDM[8:0] SSTL_2 O RCVENOUT# Memory Address Copies: These signals are identical to SMA[5,4,2,1] and are used to reduce loading for selective CPC(clock-per-command). These copies are not inverted. Data Mask: When activated during writes, the corresponding data groups in the DDR SDRAM are masked. There is one SDM for every eight data lines. SDM can be sampled on both edges of the data strobes. Clock Output: Reserved, NC.
Signal Description 3.4 Clocks Table 8. Clock Signals Signal Name Type Description Host Processor Clocking BCLK I BCLK# CMOS Differential Host Clock In: These pins receive a buffered host clock from the external clock synthesizer. This clock is used by all of the GMCH logic that are in the Host clock domain (Host, Hub and system memory). The clock is also the reference clock for the graphics core PLL. This is a low voltage differential input.
Intel® 854 Graphics Memory Controller Hub (GMCH) DPMS I DVO Display Power Management Signaling: This signal is used only in mobile systems to act as the DREFCLK in certain power management states (i.e., Display Power Down Mode); DPMS Clock is used to refresh video during S1-M. Clock Chip is powered down in S1-M. DPMS should come from a clock source that runs during S1-M and needs to be 1.5 V. So, an example would be to use a 1.5-V version of SUSCLK from ICH4-M.
Signal Description 3.5 Internal Graphics Display Signals The IGD has support for DVOB/C interfaces, and an Analog CRT port.Digital Video Output B (DVOB) Port. 3.5.1 Digital Video Output B (DVOB) Port Table 9. Digital Video Output B (DVOB) Port Signal Descriptions Name DVOBD[11:0] Type O DVO Description DVOB Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOBCLK and DVOBCLK#. This provides 24-bits of data per clock period.
Intel® 854 Graphics Memory Controller Hub (GMCH) 3.5.2 Digital Video Output C (DVOC) Port Table 10. Digital Video Output C (DVOC) Port Signal Descriptions Name DVOCD[11:0] Type O DVO Description [Native Graphic Mode] DVOC Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOCCLK and DVOCCLK#. This provides 24-bits of data per clock period. In dual channel mode, this provides the upper 12-bits of pixel data.
Signal Description Table 11. DVOB and DVOC Port Common Signal Descriptions Name Type Description I DVOBCINTR# DVO I ADDID[7:0] DVO DVOBC Interrupt: This pin is used to signal an interrupt, typically used to indicate a hot plug or unplug of a digital display. ADDID[7:0]: These pins are used to communicate to the Video BIOS when an external device is interfaced to the DVO port. Note: Bit[7] needs to be strapped low when an on-board DVO device is present. The other pins should be left as NC.
Intel® 854 Graphics Memory Controller Hub (GMCH) 3.5.4 General Purpose Input/Output Signals Table 13. GPIO Signal Descriptions GPIO I/F Total RSTIN# Type I Comments Reset: Primary Reset, Connected to PCIRST# of ICH4-M. CMOS PWROK I Power OK: Indicates that power to GMCH is stable.
Signal Description 3.6 Voltage References, PLL Power Table 14. Voltage References, PLL Power Signal Name Type Description Host Processor HXRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. HYRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. HXSWING Analog Host Voltage Swing (RCOMP reference voltage): This signal provides a reference voltage used by the FSB RCOMP circuit.
Intel® 854 Graphics Memory Controller Hub (GMCH) Hub Interface HLRCOMP Analog Hub Interface RCOMP: This signal is connected to a reference resistor in order to calibrate the buffers. PSWING Analog RCOMP reference voltage: This is connected to the RCOMP buffer differential amplifier and is used to calibrate the buffers. HLVREF VCCHL Analog Ref Input buffer VREF: Input buffer differential amplifier to determine a high versus low input voltage.
Register Description 4.0 Register Description 4.1 Conceptual Overview of the Platform Configuration Structure The GMCH and ICH4-M are physically connected by a Hub interface. From a configuration standpoint, the Hub interface is logically PCI bus #0. As a result, all devices internal to the GMCH and ICH4-M appear to be on PCI bus #0.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.2 Nomenclature for Access Attributes Table 16 provides the nomenclature for the access attributes. Table 16. Nomenclature for Access Attributes RO Read Only. If a register is Read Only, Writes to this register have no effect. R/W Read/Write. A register with this attribute can be Read and Written. R/W/L Read/Write/Lock. A register with this attribute can be Read, Written, and Locked. R/WC Read/Write Clear.
Register Description 4.3 Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Specification defines two bus cycles to access the PCI Configuration Space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the CPU.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.4.2 Primary PCI and Downstream Configuration Mechanism If the Bus Number in the CONFIG_ADDRESS is non-zero, the GMCH will generate a Type 1 Hub interface Configuration Cycle. A[1:0] of the Hub interface request packet for the Type 1 configuration cycle will be “01”. This Hub interface configuration cycle will be sent over Hub interface.
Register Description system initialization software (usually BIOS) to properly determine the DDR SDRAM configurations, operating parameters, and optional system features that are applicable and to program the GMCH registers accordingly. 4.6 I/O Mapped Registers The GMCH contains two registers that reside in the CPU I/O Address Space: the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register.
Intel® 82854 Graphics Memory Controller Hub (GMCH) Bit 31 Descriptions Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI Configuration Space are enabled. If this bit is Reset to 0, accesses to PCI Configuration Space are disabled. 30:24 Reserved 23:16 Bus Number: When the Bus Number is programmed to 00h, the target of the Configuration Cycle is a Hub interface agent (GMCH, ICH4-M, and so on.).
Register Description 4.6.2 CONFIG_DATA – Configuration Data Register I/O Address: 0CFCh Default Value: 00000000h Access: Read/Write Size: 32 bits CONFIG_DATA is a 32-bit Read/Write window into Configuration Space. The portion of Configuration Space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Figure 3. Configuration Data Register 31 0 0 Bit Default Configuration Data Window Bit 31:0 D15343-003 Descriptions Configuration Data Window (CDW).
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.7 VGA I/O Mapped Registers If Native Graphics mode is strapped, and Device #2 is enabled, and Function #0 within Device #2 is enabled for VGA, and IO_EN is set within Function #0 then GMCH claims a set of I/O registers for legacy VGA function. Table 17 lists direct CPU Access registers and Table 18 lists registers that are Index – Data registers that are used to access Internal VGA registers. Table 17. VGA I/O Mapped Register List Name Table 18.
Register Description 4.8 Intel 854 GMCH Host-Hub Interface Bridge Device Registers (Device #0, Function #0) Table 5 summarizes the configuration space for Device #0, Function#0. Table 19.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 50 Aperture Translation Table Base ATTBASE B8 BB 00000000h RO, R/W Host Error Control/Status/ Obs HEM F0 F3 00000000h RO, R/W D15343-003
Register Description 4.8.1 VID – Vendor Identification Register Address Offset: 00-01h Default Value: 8086h Access: Read only Size: 16 bits The VID Register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register, uniquely identifies any PCI device. Writes to this register have no effect. 4.8.2 Bit Descriptions 15:0 Vendor Identification (VID): This register field contains the PCI standard identification for Intel.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.8.3 PCICMD – PCI Command Register Address Offset: 04-05h Default Value: 0006h Access: Read only, Read/Write Size: 16 bits Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented. Bit Descriptions 15:10 Reserved 9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast backto-back Write.
Register Description 4.8.4 PCI Status Register Address Offset: 06-07h Default Value: 0090h Access: Read only, Read/WriteClear Size: 16 bits PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.8.5 RID – Register Identification Address Offset: 08h Default Value: 02h Access: Read only Size: 8 bits This register contains the revision number of the GMCH Device #0. These bits are read only and writes to this register have no effect. 4.8.6 Bit Descriptions 7:0 Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH Device #0.
Register Description 4.8.7 BCC – Base Class Code Register Address Offset: 0Bh Default Value: 06h Access: Read only Size: 8 bits This register contains the Base Class code of the GMCH Device #0. This code is 06h indicating a Bridge device. 4.8.8 Bit Descriptions 7:0 Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the GMCH. This code has the value 06h, indicating a Bridge device.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.8.10 SID – Subsystem Identification Register Address Offset: 2E-2Fh Default Value: 0000h Access: Read/Write Once Size: 16 bits This value is used to identify a particular subsystem. 4.8.11 Bit Descriptions 15:0 Subsystem ID (SUBID): This field should be programmed during BIOS initialization. After it has been written once, it becomes Read Only.
Register Description 4.8.12 CAPID – Capabilities Identification Register (Device #0) Address Offset: 40-44h Default Value: chipset independent Access: Read Only Size: 40 bits The Capability Identification Register uniquely identifies chipset capabilities as defined in the table below. The bits in this register are intended to define a capability ceiling for each feature, not a capability select. The capability selection for each feature is implemented elsewhere.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.8.13 GMC – GMCH Miscellaneous Control Register (Device #0) Address Offset: 50-51h Default Value: 0000h Access: Read/Write Size: 16 bits Bit Descriptions 15:10 Reserved 9 Reserved 8 RRBAR Access Enable—R/W: 1: Enables the RRBAR space. 0: Disable 7:1 Reserved 0 MDA Present (MDAP)—R/W: This bit should not be set when the VGA Enable bit is not set.
Register Description 4.8.14 GGC – GMCH Graphics Control Register (Device #0) Address Offset: 52-53h Default Value: 0030h Access: Read/Write Size: 16 bits Bit Descriptions 15:7 Reserved 6:4 Graphics Mode Select (GMS): This field is used to select the amount of Main system memory that is pre-allocated to support the Internal Graphics Device in VGA (non-linear) and Native (linear) modes. The BIOS ensures that system memory is pre-allocated only when Internal Graphics is enabled.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.8.15 DAFC – Device and Function Control Register (Device #0) Address Offset: 54-55h Default Value: 0000h Access: Read/Write Size: 16 bits This 16-bit register controls the visibility of devices and functions within the GMCH to configuration software. Bit Description 15:8 Reserved 7 Device #2 Disable: 1: Disabled. 0: Enabled.
Register Description 4.8.17 PAM(6:0) – Programmable Attribute Map Register (Device #0) Address Offset: 59-5Fh Default Value: 00h Each Access: Read/Write Size: 4 bits/register, 14 registers The GMCH allows programmable DDR SDRAM attributes on 13 Legacy system memory segments of various sizes in the 640 kB -1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR registers in the P6 processor.
Intel® 82854 Graphics Memory Controller Hub (GMCH) As an example, consider a BIOS that is implemented on the Expansion bus. During the initialization process, the BIOS can be shadowed in main system memory to increase the system performance. When BIOS is shadowed in main system memory, it should be copied to the same address location. To shadow the BIOS, the attributes for that address range should be set to Write Only. The BIOS is shadowed by first doing a Read of that address.
Register Description Table 21.
Intel® 82854 Graphics Memory Controller Hub (GMCH) Extended System BIOS Area (E0000h-EFFFFh) This 64-kB area is divided into four 16-kB segments that can be assigned with different attributes via PAM Control register as defined in Figure 4 and Table 21. System BIOS Area (F0000h-FFFFFh) This area is a single 64-kB segment that can be assigned with different attributes via PAM Control register as defined in Figure 4 and Table 21. 4.8.
Register Description 4.8.19 ESMRAMC – Extended System Management RAM Control (Device #0) Address Offset: 61h Default Value: 38h Access: Read/Write/Lock Size: 8 bits The Extended SMRAM register controls the configuration of Extended SMRAM Space. The Extended SMRAM (E_SMRAM) Memory provides a Write-Back cacheable SMRAM Memory Space that is above 1 MB. Bit Description 7 H_SMRAM_EN (H_SMRAME): Controls the SMM Memory Space location (that is, above 1 MB or below 1 MB).
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.8.20 ERRSTS – Error Status Register (Device #0) Address Offset: 62-63h Default Value: 0000h Access: Read/Write Clear Size: 16 bits This register is used to report various error conditions via Hub Interface Special cycles. An SERR, SMI, or SCI Error Hub Interface Special cycle may be generated on a zero to one transition of any of these flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD registers respectively.
Register Description 4.8.21 ERRCMD – Error Command Register (Device #0) Address Offset: 64-65h Default Value: 0000h Access: Read/Write Clear Size: 16 bits This register enables various errors to generate a SERR Hub Interface Special cycle. Since the GMCH does not have a SERR# signal, SERR messages are passed from the GMCH to the ICH4-M over Hub interface. The actual generation of the SERR message is globally enabled for Device #0 via the PCI Command register.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 5 SERR on Receiving Unimplemented Special Cycle Hub Interface Completion Packet: 1: The GMCH generates an SERR Hub Interface Special cycle when a GMCH initiated Hub interface request is terminated with a Unimplemented Special cycle completion packet. 0: Reporting of this condition is disabled. 4:2 1 Reserved SERR on Multiple-bit ECC Error: 0: This system does not support ECC, this field must be set to 0.
Register Description 4.8.23 SCICMD – SCI Error Command Register (Device #0) Address Offset: 67h Default Value: 00h Access: Read/Write Size: 8 bits This register enables various errors to generate a SCI Hub Interface Special cycle. When an Error Flag is set in the ERRSTS register, it can generate a SERR, SMI, or SCI Hub Interface Special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively. Note: An error can generate one and only one Hub Interface Error Special cycle.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.8.24 SHIC – Secondary Host Interface Control Register (Device #0) Address Offset: 74-77h Default Value: 00006010h Access: Read Only, Read/Write Size: 32 bits Bit Descriptions 31 Reserved 30 BREQ0# Control of FSB Address and Control bus power management: 0: Disable FSB address and control bus power management. 1: Eisable FSB address and control bus power management. 29:28 Reserved 27 On Die Termination (ODT) Gating Disable: 0: Enable.
Register Description 4.8.25 D15343-003 HEM – Host Error Control, Status, and Observation (Device #0) Address Offset: F0-F3h Default Value: 00000000h Access: Read Only, Read/Write Size: 32 bits Bit Description 31 Detected HADSTB1# Glitch (ASTB1GL): This bit is set when the GMCH has detected a glitch on address strobe HADSTB1#. Software must write a 1 to clear this status bit. 30 Detected HADSTB0# Glitch (ASTB0GL): This bit is set when the GMCH has detected a glitch on address strobe HADSTB0#.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.9 Intel 854 GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function #1) The following table shows the GMCH Configuration Space for Device #0, Function #1. See “Nomenclature for Access Attributes” on page 42 for access nomenclature. Table 22.
Register Description 4.9.1 VID – Vendor Identification Register Address Offset: 00-01h Default Value: 8086h Access: Read Only Size: 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect. 4.9.2 Bit Descriptions 15:0 Vendor Identification (VID): This register field contains the PCI standard identification for Intel.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.9.3 PCICMD – PCI Command Register Address Offset: 04-05h Default Value: 0006h Access: Read Only, Read/Write Size: 16 bits Since Intel chipset Device #0 does not physically reside on PCI_A, many of the bits are not implemented. 74 Bit Descriptions 15:10 Reserved 9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast backto-back Write.
Register Description 4.9.4 PCISTS – PCI Status Register Address Offset: 06-07h Default Value: 0080h Access: Read Only, Read/Write Clear Size: 16 bits PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does not physically reside on PCI_A, many of the bits are not implemented.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.9.5 RID – Revision Identification Register Address Offset: 08h Default Value: 02h Access: Read Only Size: 8 bits This register contains the revision number of the Intel® 82854 GMCH Device #0. These bits are Read Only and Writes to this register have no effect. 4.9.6 Bit Descriptions 7:0 Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH Device #0.
Register Description 4.9.8 HDR – Header Type Register Address Offset: 0Eh Default Value: 80h Access: Read Only Size: 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. 4.9.9 Bit Descriptions 7:0 PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device. Reads and Writes to this location have no effect.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.9.11 CAPPTR – Capabilities Pointer Register Address Offset: 34h Default Value: 00h Access: Read Only Size: 8 bits The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. 4.9.
Register Description 4.9.13 DRA – DRAM Row Attribute Register (Device #0) Address Offset: 50-51h Default Value: 77h Access: Read/Write Size: 8 bits The DDR SDRAM Row Attribute Register defines the page sizes to be used when accessing different pairs of Rows. Each Nibble of information in the DRA registers describes the page size of a pair of Rows: Row 0, 1: 50h Row 2, 3: 51h 52h-5Fh: Reserved.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.9.14 DRT – DRAM Timing Register (Device #0) Address Offset: 60-63h Default Value: 18004425h Access: Read/Write Size: 32 bits This register controls the timing of the DDR SDRAM controller. Bit Description 31 DDR Internal Write to Read Command delay (tWTR): The tWTR is a std. DDR SDRAM timing parameter with a value of 1 CK for CL=2 and 2.5.
Register Description 27:26 Back To Back Read-Write commands spacing (DDR, same or different Rows/Bank): This field determines the RD-WR command spacing, in terms of common clocks based on the following formula: CL + 0.5xBL + TA (RD-WR) – DQSS DQSS: is time from Write command to data and is always 1 CK BL: is Burst Length which is set to 4 TA (RD-WR): is required DQ turn-around, can be set to 1, 2 or 3 CK CL: is CAS latency, can be set to 2 or 2.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 11 Activate to Precharge delay (tRAS), MAX: This bit controls the maximum number of clocks that a DDR SDRAM bank can remain open. After this time period, the system memory Controller will guarantee to pre-charge the bank. Note that this time period may or may not be set to overlap with time period that requires a refresh to happen. The DDR SDRAM Controller includes a separate tRAS-MAX counter for every supported bank.
Register Description 4.9.15 PWRMG – DRAM Controller Power Management Control Register (Device #0) Address Offset: 68-6Bh Default Value: 00000000h Access: Read/Write Size: 32 bits Bit Description 31:24 Reserved 23:20 Row State Control: This field determines the number of clocks the System Memory Controller will remain in the idle state before it begins pre-charging all pages or powering down rows.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 10 Reserved. 9:1 Reserved 0 Power State S1/S3 Refresh Control: 0 = Normal Operation, Pending refreshes are not completed before entering Self Refresh for S1/ S3. 1 = All Pending Refreshes plus one extra is performed before entering Self Refresh for S1/S3.
Register Description 4.9.16 DRC – DRAM Controller Mode Register (Device #0) Address Offset: 70-73h Default Value: 00000081h Access: RO, Read/Write Size: 32 bits Bit Description 31:30 Revision Number (REV): Reflects the revision number of the format used for DDR SDRAM register definition (Read Only). 29 Initialization Complete (IC): This bit is used for communication of software state between the Memory Controller and the BIOS.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 9:7 Refresh Mode Select (RMS): This field determines whether Refresh is enabled and, if so, at what rate Refreshes will be executed. 000: Refresh disabled 001: Refresh enabled. Refresh interval 15.6 µsec 010: Refresh enabled. Refresh interval 7.8 µsec 011: Reserved. 111: Refresh enabled. Refresh interval 64 clocks (fast refresh mode) Other: Reserved Any change in the programming of this field Resets the Refresh counter to zero.
Register Description 6:4 Mode Select (SMS). These bits select the special operational mode of the DDR SDRAM Interface. The special modes are intended for initialization at power up. 000: Post Reset State – When the GMCH exits Reset (power-up or otherwise), the mode select field is cleared to 000. Software is not expected to Write this value, however if this value is Written, there are no side effects (no Self Refresh or any other special DDR SDRAM cycle).
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.9.17 DTC – DRAM Throttling Control Register (Device #0) Address Offset: A0-A3h Default Value: 00000000h Access: Read/Write/Lock Size: 32 bits Throttling is independent for system memory banks, GMCH Writes, and Thermal Sensor Trips. Read and Write Bandwidth is measured independently for each bank.
Register Description Bit Description 31:28 DDR SDRAM Throttle Mode (TMODE): Four bits control which mechanisms for Throttling are enabled in an “OR” fashion. Counterbased Throttling is lower priority than Thermal Trips Throttling when both are enabled and Tripped. Counter-based trips point Throttling values and Thermal-based Trip Point Throttling values are specified in this register.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 27:24 Read Counter Based Power Throttle Control (RCTC): These bits select the Counter based Power Throttle Bandwidth Limits for Read operations to system memory. R/W, RO if Throttle Lock.
Register Description 15:12 Write Thermal Based Power Throttle Control (WTTC): These bits select the Thermal based Power Throttle Bandwidth Limits for Write operations to system memory. R/W, RO if Throttle Lock 0h = 85% 1h = 70% 2h = 65% 3h = 60% 4h = 55% 5h = 50% 6h = 45% 7h = 40% 8h = 35% 9h = 30% Ah = 20% B-Fh = Reserved 11 Counter Based Throttle Lock (CTLOCK): This bit secures RCTC and WCTC. This bit defaults to 0. Once a 1 is written to this bit, RCTC and WCTC (including CTLOCK) become Read-Only.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.10 Intel 854 GMCH Configuration Process Registers (Device #0, Function #3) See “Nomenclature for Access Attributes” on page 42 for access nomenclature. Table 23 summarizes all Device#0, Function #3 registers. Table 23.
Register Description 4.10.2 DID – Device Identification Register Address Offset: 02-03h Default Value: 358Ch Access: Read Only Size: 16 bits This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect. D15343-003 Bit Descriptions 15:0 Device Identification Number (DID): This is a 16-bit value assigned to the Intel 854 GMCH Host-HI Bridge Function #3 (358Ch).
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.10.3 PCICMD – PCI Command Register Address Offset: 04-05h Default Value: 0006h Access: Read Only, Read/Write Size: 16 bits Since the Intel® 82854 GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented. 94 Bit Descriptions 15:10 Reserved 9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast backto-back Write.
Register Description 4.10.4 PCISTS – PCI Status Register Address Offset: 06-07h Default Value: 0080h Access: Read Only, Read/Write Clear Size: 16 bits PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/Write clear. All other bits are Read Only. Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.10.5 RID – Revision Identification Register Address Offset: 08h Default Value: 02h Access: Read Only Size: 8 bits This register contains the revision number of the Intel® 82854 GMCH. These bits are Read Only and Writes to this register have no effect. 4.10.6 Bit Descriptions 7:0 Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH.
Register Description 4.10.8 HDR – Header Type Register Address Offset: 0Eh Default Value: 80h Access: Read Only Size: 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. 4.10.9 Bit Descriptions 7:0 PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.10.11 CAPPTR – Capabilities Pointer Register Address Offset: 34h Default Value: 00h Access: Read Only Size: 8 bits The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. 4.10.
Register Description Table 24.
Intel® 82854 Graphics Memory Controller Hub (GMCH) Intel® 82854 GMCH Integrated Graphics Device Registers (Device #2, Function #0) 4.11 This section contains the PCI configuration registers listed in order of ascending offset address. Device #2 incorporates Function #0. See “Nomenclature for Access Attributes” on page 42 for access nomenclature. Note: Table 25. C0F0 = Copy of Function #0 and U1F1 = Unique in Function #1.
Register Description 4.11.1 VID – Vendor Identification Register (Device #2) Address Offset: 00-01h Default Value: 8086h Access: Read Only Size: 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect. 4.11.2 Bit Description 15:0 Vendor Identification Number: This is a 16-bit value assigned to Intel.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.11.3 PCICMD – PCI Command Register (Device #2) Address Offset: 04-05h Default Value: 0000h Access: Read Only, Read/Write Size: 16 bits This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD register in the IGD disables the IGD PCI compliant master accesses to main system memory.
Register Description 4.11.4 PCISTS – PCI Status Register (Device #2) Address Offset: 06-07h Default Value: 0090h Access: Read Only Size: 16 bits PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD. 4.11.5 Bit Description 15 Detected Parity Error (DPE): Since the IGD does not detect parity, this bit is always set to 0.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.11.6 CC – Class Code Register (Device #2) Address Offset: 09-0Bh Default Value: 030000h Access: Read Only Size: 24 bits This register contains the device programming interface information related to the Sub-Class code and Base Class code definition for the IGD. This register also contains the Base Class code and the function sub-class in relation to the Base Class code.
Register Description 4.11.9 Bit Description 7:0 Master Latency Timer Count Value – RO HDR – Header Type Register (Device #2) Address Offset: 0Eh Default Value: 00h Access: Read Only Size: 8 bits This register contains the Header Type of the IGD. 4.11.10 Bit Description 7 Multi Function Status (MFunc): Indicates if the device is a multi-function device. 6:0 Header Code (H): This is a 7-bit value that indicates the Header code for the IGD.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.11.11 MMADR – Memory Mapped Range Address Register (Device #2) Address Offset: 14-17h Default Value: 00000000h Access: Read/Write, Read Only Size: 32 bits This register requests allocation for the IGD registers and instruction ports. The allocation is for 512-kB and the base address is defined by bits [31:19]. 4.11.12 Bit Description 31:19 Memory Base Address–R/W: Set by the OS, these bits correspond to address signals [31:19].
Register Description 4.11.13 4.11.14 4.11.15 SVID – Subsystem Vendor Identification Register (Device #2) Address Offset: 2C-2Dh Default Value: 0000h Access: Read/Write Once Size: 16 bits Bit Description 15:0 Subsystem Vendor ID: This value is used to identify the vendor of the subsystem. This register should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register can only be cleared by a reset.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.11.16 4.11.17 4.11.18 108 INTRLINE – Interrupt Line Register (Device #2) Address Offset: 3Ch Default Value: 00h Access: Read/Write Size: 8 bits Bit Description 7:0 Interrupt Connection: Used to communicate interrupt line routing information. POST software Writes the routing information into this register as it initializes and configures the system.
Register Description 4.11.19 4.11.20 D15343-003 MAXLAT – Maximum Latency Register (Device #2) Address Offset: 3Fh Default Value: 00h Access: Read Only Size: 8 bits Bit Description 7:0 Maximum Latency Value: Bits[7:0]=00h. The IGD has no specific requirements for how often it needs to access the PCI bus.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.11.21 PMCS – Power Management Control/Status Register (Device #2) Address Offset: D4-D5h Default Value: 0000h Access: Read/Write, Read Only Size: 16 bits Bit Description 15 PME_Status –RO: This bit is 0 to indicate that IGD does not support PME# generation from D3 (cold). 14:9 Reserved 8 PME_En–RO: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
Intel® 82854 GMCH System Address Map 5.0 Intel® 82854 GMCH System Address Map A system based on the GMCH supports 4 GB of addressable system memory space and 64 kB+3B of addressable I/O space. The I/O and system memory spaces are divided by system configuration software into regions. The system memory ranges are useful either as system memory or as specialized system memory, while the I/O regions are used solely to control the operation of devices in the system.
Intel® 82854 Graphics Memory Controller Hub (GMCH) Figure 6.
Intel® 82854 GMCH System Address Map Table 26.
Intel® 82854 Graphics Memory Controller Hub (GMCH) Monochrome Display Adapter (MDA) Range (0B0000h - 0B7FFFh) Monochrome Display Adapter ranges is accessible when the Intel® 854 Chipset is strapped into Native Graphics mode. Legacy support requires the ability to have a second graphics controller (monochrome) in the system. Accesses in the standard VGA range are forwarded to IGD and the Hub interface (depending on configuration bits).
Intel® 82854 GMCH System Address Map 5.4 Main System Memory Address Range (0010_0000h to Top of Main Memory) The address range from 1 MB to the top of main system memory is mapped to main DDR SDRAM address range controlled by the GMCH. The GMCH will forward all accesses to addresses within this range to the DDR SDRAM unless a hole in this range is created using the fixed hole as controlled by the FDHC register. Accesses within this hole are forwarded to Hub interface.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 5.4.2.1 Extended SMRAM Address Range (HSEG and TSEG) The HSEG and TSEG SMM transaction address spaces reside in this extended system memory area. 5.4.2.2 HSEG SMM mode CPU accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. Non-SMM mode CPU accesses to enabled HSEG are considered invalid are terminated immediately on the FSB.
Intel® 82854 GMCH System Address Map 5.4.2.5 PCI Memory Address Range (Top of Main System Memory to 4 GB) The address range from the top of main DDR SDRAM to 4-GB (top of physical system memory space supported by the GMCH) is normally mapped via the Hub interface to PCI. As an internal graphics configuration, there are two exceptions to this rule. 1. The first exception is addresses decoded to the graphics memory range. One per function in device #2. 2.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 5.4.3 System Management Mode (SMM) Memory Range The GMCH supports the use of main system memory as System Management RAM (SMM RAM) enabling the use of System Management mode. The GMCH supports three SMM options: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment (TSEG). System Management RAM space provides a system memory area that is available for the SMI handler's and code and data storage.
Intel® 82854 GMCH System Address Map Table 28. 5.4.4 SMM Space Transaction Handling SMM Space Enabled Transaction Address Space (Adr) DRAM Space (DRAM) Compatible (C) A0000h to BFFFFh A0000h to BFFFFh High (H) 0FEDA0000h to 0FEDBFFFFh A0000h to BFFFFh TSEG (T) (TOM-TSEG_SZ) to TOM (TOM-TSEG_SZ) to TOM System Memory Shadowing Any block of system memory that can be designated as Read-Only or Write-Only can be "shadowed" into GMCH DDR SDRAM.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 5.4.5.1 PCI I/O Address Mapping The GMCH can be programmed to direct non-memory (I/O) accesses to the PCI bus interface when CPU initiated I/O cycle addresses are within the I/O address range. This range is controlled via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in GMCH Device #1 configuration space. Address decoding for this range is based on the following concept.
Intel® 82854 GMCH System Address Map 5.4.7 Hub Interface Decode Rules The GMCH accepts accesses from Hub interface to the following address ranges: • All Memory Read and Write accesses to Main DDR SDRAM including PAM region (except SMM space) • Memory writes to VGA range (Native Graphics Mode only) All Memory Reads from the Hub interface A that are targeted > 4-GB system memory range will be terminated with Master Abort completion, and all Memory Writes (>4-GB) from the Hub interface will be ignored.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 5.4.7.2 Interface Decode Rules Cycles Initiated Using PCI Protocol The GMCH does not support any PCI access targeting Hub interface. The GMCH will claim PCI initiated memory read and write transactions decoded to the main DDR SDRAM range. All other memory read and write requests will be master-aborted by the PCI initiator as a consequence of GMCH not responding to a transaction.
Functional Description 6.0 Functional Description 6.1 Host Interface Overview The GMCH front side bus uses source synchronous transfer for the address and data signals. The address signals are double pumped and two addresses can be generated every bus clock. At 100-MHz bus frequency, the two address signals run at 200 MHz for a maximum address queue rate of 50-M addresses/sec. The data is quad pumped and an entire 64-B cache line can be transferred in two bus clocks.
Intel® 82854 Graphics Memory Controller Hub (GMCH) MSI is dependent on the address of the interrupt Memory Write. The GMCH forwards inbound Hub interface memory writes to address 0FEEx_xxxxh, to the system bus as Interrupt Message transactions. 6.2.2 Upstream Interrupt Messages The GMCH accepts message based interrupts from its Hub interface and forwards them to the system bus as Interrupt Message transactions.
Functional Description series of I/O cycles to the south bridge. The BIOS needs to determine the size and type of system memory used for each of the rows of system memory in order to properly configure the GMCH system memory interface. For SMBus Configuration and Access of the Serial Presence Detect Ports, refer to the Intel® 82801DBM I/O Controller Hub 4 (ICH4-M) Datasheet (252337) for more detail. 6.3.2.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 6.4 Integrated Graphics Overview The Intel® 82854 GMCH provides a highly integrated graphics accelerator and PCI set while allowing a flexible Integrated System Graphics solution. Figure 7. Intel® 82854 GMCH Graphics Block Diagram (Native Graphic Mode only) DDR/SDRAM Memory Control DAC Overlay 2D Engine 3D Engine Instr.
Functional Description 6.4.2 3D Engine The 3D engine of the GMCH has been designed with a deeply pipelined architecture, where performance is maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the same primitive.
Intel® 82854 Graphics Memory Controller Hub (GMCH) The scissor rectangle accelerates the clipping process by allowing the driver to clip to a bigger region than the hardware renders to. The scissor rectangle is pixel accurate, and independent of line and point width. The GMCH supports a single scissor box rectangle. 6.4.2.5 Backface Culling As part of the setup, the GMCH can discard polygons from further processing, if they are either facing away from or towards the user's viewpoint.
Functional Description 6.4.2.10 Texture Chromakey Chromakey is a method for removing a specific color or range of colors from a texture map before it is applied to an object. For nearest texture filter modes, removing a color simply makes those portions of the object transparent (the previous contents of the back buffer show through). For linear texture filtering modes, the texture filter is modified if only the non-nearest neighbor texels match the key (range).
Intel® 82854 Graphics Memory Controller Hub (GMCH) • Maps. Trilinear MIP Mapping is used minimize the visibility of LOD transitions across the polygon. Anisotropic MIP Nearest (Anisotropic filtering): This filter can be used when textured object pixels map back to significantly non-square regions of the texture (e.g., when the texture is scaled in one screen direction than the other screen direction). Both DirectX and OpenGL (Rev.1.1) allow support for all these filtering modes. 6.4.2.
Functional Description 6.4.3.1 Texture Map Blending Multiple textures can be blended together in an iterative process and applied to a primitive. The GMCH allows up to four distinct or shared texture coordinates and texture maps to be specified onto the same polygon. Also, the GMCH supports a texture coordinate set to access multiple texture maps. State variables in multiple textures are bound to texture coordinates, texture map or texture blending. 6.4.3.
Intel® 82854 Graphics Memory Controller Hub (GMCH) The GMCH supports both types of fog operations, vertex and per pixel. If fog is disabled, the incoming color intensities are passed unchanged to the destination blend unit. If fog is enabled, the incoming pixel color is blended with the fog color based on a fog coefficient on a per pixel basis. 6.4.3.6 Alpha Blending Alpha blending in the GMCH adds the material property of transparency or opacity to an object.
Functional Description reasonably accurate depth buffering within inches of the eye point. The selection of depth buffer size is relatively independent of the color buffer. A 16-bit Z/W or 24-bit Z/W buffer can be selected with a 16-bit color buffer. Z buffer is not supported in 8-bit mode. 6.4.3.9 Stencil Buffer The Raster engine provides 8-bit stencil buffer storage in 32-bit mode and the ability to perform stencil testing.
Intel® 82854 Graphics Memory Controller Hub (GMCH) Data is horizontally and vertically aligned at the destination. If the destination for the BLT overlaps with the source system memory location, the GMCH can specify which area in system memory to begin the BLT transfer. Hardware is included for all 256 raster operations (source, pattern, and destination) defined by Microsoft, including transparent BLT.
Functional Description 6.4.6.1 Cursor Color Formats Color data can be in an indexed format or a true color format. Indexed data uses the entries in the four-entry cursor palette to convert the two-bit index to a true color format before being passed to the blenders. The index can optionally specify that a cursor pixel be transparent or cause an inversion of the pixel value below it or one of two colors from the cursor palette.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 6.4.7.5 Color Control Color control provides a method of changing the color characteristics of the pixel data. It is applied to the data while in YUV format and uses input parameters such as brightness, saturation, hue (tint) and contrast. This feature is supplied for the overlay only and works in YUV formats only. 6.4.7.
Functional Description 6.4.8 Video Functionality The GMCH supports MPEG-2 decoding hardware, sub-picture support and DTV. 6.4.8.1 MPEG-2 Decoding The GMCH MPEG2 Decoding supports Hardware Motion Compensation (HWMC). The GMCH can accelerate video decoding for the following video coding standards: • • • • MPEG-2 support MPEG-1: Full feature support H.263 support MPEG-4: Only supports some features in the simple profile The HWMC interface supports Hardware Video Acceleration Compatible API’s (HVA). 6.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 6.5 Internal Graphic Display Interface The GMCH has three dedicated display ports: an Analog CRT port and two Digital display ports, DVOB and DVOC. When the GMCH is strapped to operate in Native Graphic Mode, the DVOB and DVOC can support down stream devices such as TV-out encoders, external DACs, LVDS transmitters, and TMDS transmitters.
Functional Description 6.5.1.1 ARIB Support Please refer to the ARIB TR-B15 Operational Guidelines for Digital Satellite Broadcasting (detailed Implementation guideline for receiver) for an exhaustive coverage of this topic (http://www.arib.or.jp/english/html/overview/ov/tr_b15.html). The Intel® 82854 GMCH supports the ARIB resolutions in Figure 8 except the Motion Picture (Movie) Plane and the Movie/Still picture selection plane. This device supports the remaining planes outlined in Figure 8. Figure 8.
Intel® 82854 Graphics Memory Controller Hub (GMCH) Figure 9.
Functional Description Following conditions should be met for the sync (HSYNC, VSYNC) and blank (HBLANK, VBLANK) signals: • Start of H(V)SYNC can not coincide with start of H(V)BLANK • H(V)SYNC should always start after H(V)BLANK starts.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 6.5.3.2 ARIB 960 X 540 support In order to support the conversion of a 960x540 or a 960x1080 Plane A buffer to 1920x1080i, the GMCH supports pixel doubling in the horizontal direction and field replication in the vertical direction. In order to activate this functionality, interlace mode bit 20 in the DVOC- Digital Display Port C Register must be programmed to a 1.
Functional Description 6.5.4 Interlace support for Video Overlay Window In interlace mode, support for Field1 and Field2 timing generation is supported by the Video Overlay. The Video Overlay makes use of the DPODPfieldID signal generated by the Pipe A timing generator to synchronize the field timing. This signal is used to indicate which field should be scanned out. The Video Overlay determines the correct lines to be used to assemble Field1 and Field2 during on the fly up and down scaling.
Intel® 82854 Graphics Memory Controller Hub (GMCH) Figure 11 shows how the timing registers switch while the buffer 0 and buffer 1 are scanned out. HSYNC_A HBLANK_A Timing Register Switching HTOTAL_A Figure 11.
Functional Description 6.5.5 Analog Display Port Characteristics The Analog display port provides an RGB signal output along with an HSYNC and VSYNC signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The intended target device is for a CRT based monitor with a VGA connector. 6.5.5.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 146 D15343-003
Power and Thermal Management 7.0 Power and Thermal Management The Intel® 82854 GMCH is intended to be compliant with the following specifications and technologies: • • • • • • • • • • • • • D15343-003 APM Rev 1.2 PCI Power Management Rev 1.0 PC'99, Rev 1.0, PC'99A, and PC'01, Rev 1.0 ACPI 1.0b and 2.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 7.1 General Description of Supported CPU States C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK is deasserted, and the processor core is active. The processor can service snoops and maintain cache coherency in this state. C1 (Auto Halt): The first level of power reduction occurs when the processor executes an AutoHalt instruction.
Power and Thermal Management 7.3 Internal Thermal Sensor This section describes the new on-die Thermal sensor capability. 7.3.1 Overview The Thermal sensor functions are provided below: Catastrophic Trip Point: This trip point is programmed through the BIOS during initialization. This trip point is set at the temperature at which the GMCH should be shut down immediately with minimal software support. The settings for this are lockable.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 7.4 External Thermal Sensor Input An External Thermal sensor with a serial interface may be placed next to DDR SDRAM DIMM (or any other appropriate platform location), or a remote Thermal Diode may be placed next to the DDR DIMM (or any other appropriate platform location) and connected to the External Thermal sensor. Intel advises that the External Thermal sensor contains some form of hysteresis, since none is provided by the GMCH hardware.
Intel® 82854 GMCH Strap Pins 8.0 Intel® 82854 GMCH Strap Pins 8.1 Strapping Configuration Table 33.
Intel® 82854 Graphics Memory Controller Hub (GMCH) Intel® 82854 GMCH Straps for Frequency/CPU Configuration Table 34. GST[2:0] LCLKCTLB CPU FSB Freq DDR Freq Gfx Freq Core Vcc 000 0 Intel Celeron M Processor Family, Genuine Intel Processor 400MHz 266MHz 200MHz 1.5V 111 0 Intel Celeron M Processor Family, Genuine Intel Processor 400MHz 333MHz 250MHz 1.
Ballout and Package Information 9.0 Ballout and Package Information Figure 12.
Intel® 82854 Graphics Memory Controller Hub (GMCH) 9.1 VCC/VSS Voltage Groups Table 35. Voltage Levels and Ball Out for Voltage Groups Name Voltage Level Ball out VCC 1.5 H14,J15,N14,N16,P13,P15,P17,R14,R16,T13,T15, T17,U14,U16,W21,AA15,AA17,AA19 VCCADAC 1.5 A9,B9 VCCDVO 1.5 E1,E4,E6,H7,J1,J4,J8,K9,L8,M4,M8,M9,N1,N8,P9,R8 VCCASM 1.5 AD1,AF1 VCC1_5 1.5 B14,B15,G13,J13 VCCGPIO 3.3 A3,A4 VCCHL 1.5 U6,U8,V1,V7,V9,W5,W8,Y1 VCCQSM 2.5 AJ6,AJ8 VCCSM 2.
Ballout and Package Information Table 36.
Intel® 82854 Graphics Memory Controller Hub (GMCH) Row Column Signal Name Row Column Signal Name Row Column Signal Name Y 25 HA[21]# F 25 HD[16]# B 23 HD[43]# AA 27 HA[22]# F 26 HD[17]# F 23 HD[44]# W 24 HA[23]# B 27 HD[18]# F 21 HD[45]# W 23 HA[24]# H 23 HD[19]# C 20 HD[46]# W 27 HA[25]# K 25 HD[2]# C 21 HD[47]# Y 27 HA[26]# E 27 HD[20]# G 18 HD[48]# AA 28 HA[27]# G 25 HD[21]# E 19 HD[49]# W 28 HA[28]# F 28 HD[22]# G 28 HD[5]#
Ballout and Package Information Row Column Signal Name Row Column Signal Name Row Column Signal Name K 27 HDSTBP[0]# H 10 HSYNC T 7 MDDCDATA D 26 HDSTBP[1]# M 25 HTRDY# N 7 MDVICLK E 21 HDSTBP[2]# B 20 HXRCOMP M 6 MDVIDATA E 18 HDSTBP[3]# B 18 HXSWING K 7 MI2CCLK K 21 HDVREF[0] H 28 HYRCOMP N 6 MI2CDATA J 21 HDVREF[1] K 28 HYSWING AJ 29 NC J 17 HDVREF[2] D 14 RSVD AH 29 NC N 27 HIT# E 13 RSVD B 29 NC N 28 HITM# E 10 RSVD
Intel® 82854 Graphics Memory Controller Hub (GMCH) Row Column Signal Name Row Column Signal Name Row Column Signal Name AD 28 RSTIN# AB 4 SCK[5]# AF 4 SDQ[2] F 12 RSVD AC 7 SCKE[0] AH 7 SDQ[20] D 12 RSVD AB 7 SCKE[1] AD 9 SDQ[21] B 12 RSVD AC 9 SCKE[2] AF 10 SDQ[22] AA 5 RSVD AC 10 SCKE[3] AE 11 SDQ[23] L 4 RSVD AD 23 SCS[0]# AH 10 SDQ[24] C 4 GST[0] AD 26 SCS[1]# AH 11 SDQ[25] F 3 RSVD AC 22 SCS[2]# AG 13 SDQ[26] D 3 RSVD
Ballout and Package Information Row Column Signal Name Row Column Signal Name Row Column Signal Name AG 22 SDQ[47] AG 2 SDQS[0] AC 21 SRAS# AE 23 SDQ[48] AH 5 SDQS[1] AD 25 SWE# AH 23 SDQ[49] AH 8 SDQS[2] W 21 VCC AE 2 SDQ[5] AE 12 SDQS[3] AA 19 VCC AE 24 SDQ[50] AH 17 SDQS[4] AA 17 VCC AH 25 SDQ[51] AE 21 SDQS[5] T 17 VCC AG 23 SDQ[52] AH 24 SDQS[6] P 17 VCC AF 23 SDQ[53] AH 27 SDQS[7] U 16 VCC AF 25 SDQ[54] AD 15 SDQS[8
Intel® 82854 Graphics Memory Controller Hub (GMCH) Row Column Signal Name Row Column Signal Name Row Column Signal Name B 14 VCC1_5 AJ 6 VCCQSM AB 6 VCCSM J 13 VCC1_5 AG 29 VCCSM AA 6 VCCSM G 13 VCC1_5 AF 29 VCCSM AJ 5 VCCSM P 9 VCCDVO AC 29 VCCSM Y 4 VCCSM M 9 VCCDVO AF 27 VCCSM AF 3 VCCSM K 9 VCCDVO AJ 25 VCCSM AB 3 VCCSM R 8 VCCDVO AF 24 VCCSM AG 1 VCCSM N 8 VCCDVO AB 22 VCCSM AC 1 VCCSM M 8 VCCDVO AJ 21 VCCSM A 12
Ballout and Package Information Row Column Signal Name Row Column Signal Name Row Column Signal Name AJ 26 VSS U 22 VSS AA 18 VSS AB 26 VSS R 22 VSS J 18 VSS W 26 VSS N 22 VSS F 18 VSS U 26 VSS L 22 VSS AC 17 VSS R 26 VSS J 22 VSS AB 17 VSS N 26 VSS F 22 VSS U 17 VSS L 26 VSS C 22 VSS R 17 VSS J 26 VSS AG 21 VSS N 17 VSS G 26 VSS AB 21 VSS H 17 VSS AE 25 VSS AA 21 VSS D 17 VSS AA 25 VSS Y 21 VSS A 17
Intel® 82854 Graphics Memory Controller Hub (GMCH) Row Column Signal Name Row Column Signal Name Row Column Signal Name AB 13 VSS L 9 VSS K 4 VSS U 13 VSS E 9 VSS G 4 VSS R 13 VSS AC 8 VSS D 4 VSS N 13 VSS Y 8 VSS AJ 3 VSS H 13 VSS V 8 VSS AG 3 VSS F 13 VSS T 8 VSS R 2 VSS D 13 VSS P 8 VSS AJ 1 VSS A 13 VSS K 8 VSS AE 1 VSS AJ 12 VSS H 8 VSS AA 1 VSS AG 12 VSS AJ 7 VSS U 1 VSS AA 12 VSS AE 7 VSS L 1 V
Ballout and Package Information Row D15343-003 Column Signal Name H 22 VTTLF U 21 VTTLF R 21 VTTLF N 21 VTTLF L 21 VTTLF H 20 VTTLF A 20 VTTLF J 19 VTTLF H 18 VTTLF A 18 VTTLF H 16 VTTLF G 15 VTTLF 163
Intel® 82854 Graphics Memory Controller Hub (GMCH) 9.2 Package Mechanical Information Figure 13 through Figure 15 provide detail on the package information and dimensions of the Intel® 82854 GMCH. The Intel® 82854 GMCH comes in a Micro-FCBGA package, which is similar to the mobile processors. The package consists of a silicon die mounted face down on an organic substrate populated with solder balls on the bottom side. Capacitors may be placed in the area surrounding the die.
Ballout and Package Information Figure 14.
Intel® 82854 Graphics Memory Controller Hub (GMCH) Figure 15.
