Audio Codec ‘97 Revision 2.3 Revision 1.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 NOTICES Intel Corporation assumes no responsibility for errors or omissions in the guide. Nor does Intel make any commitment to update the information contained herein. THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 TABLE OF CONTENTS 1. Introduction and Overview.................................................................................................................................9 1.1 AUDIO CODEC FEATURE LIST .........................................................................................................................9 1.2 MODEM CODEC FEATURE LIST ...................................................................................................
AC ‘97 Component Specification Revision 2.3 Rev 1.0 4.3.9 Slot 8: PCM R Surround DAC (or PCM R n+1) ................................................................................32 4.3.10 Slot 9: PCM LFE DAC .......................................................................................................................32 4.3.11 Slot 10: Modem Line 2 Output Channel (or PCM L n+1, or S/PDIF output) ....................................32 4.3.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 5.8 EXTENDED AUDIO REGISTER SET .................................................................................................................57 5.8.1 Extended Audio ID Register (Index 28h) .............................................................................................57 5.8.2 Extended Audio Status and Control Register (Index 2Ah)...................................................................58 5.8.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 6.7.1 ADC Loopback '001'............................................................................................................................86 6.7.2 Local analog Loopback '010'...............................................................................................................86 6.7.3 DAC Loopback '011'............................................................................................................................86 6.7.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 LIST OF FIGURES Figure 1. AC ‘97 Codec Block Diagram ...................................................................................................................10 Figure 2. AC ‘97 System Diagram ............................................................................................................................11 Figure 3. AC ‘97 48-pin package and pinout......................................................................................
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Table 16. Baseline Audio Register Map .....................................................................................................................47 Table 17. Baseline Audio Optional Feature IDs .........................................................................................................48 Table 18. 3D Stereo Enhancement Vendor IDs........................................................................................................
AC ‘97 Component Specification Revision 2.3 Rev 1.0 1. Introduction and Overview This specification defines the Audio Codec ‘97 (AC ‘97) Architecture and Digital Interface (AC-link) specifically designed for implementing audio and modem I/O functionality in mainstream PC systems.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 AC ‘97 2.x compliant modem indicates standardized modem functionality (extended modem feature set) Vendor specific package Optional second line modem and handset DACs and ADCs GPIO and interrupt capability Comprehensive power management capability 1.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 source, or a mix of sources. The optional third PCM ADC is dedicated to voice input, and also extends the range of acoustic echo cancellation (AEC) capabilities. For details, refer to Section 5. Consumer equipment (CE) compatible digital output is supported via optional SPDIF_OUT. Modem line 1, optional modem line 2, and optional handset ADC/DAC pairs shown in the figure describe integration of modem AFE functionality into the AC '97 architecture.
AC ‘97 Component Specification • • • • 1.5 Revision 2.3 Rev 1.0 Amplified analog stereo headphone output (HP_OUT) transmitted to headphones or headset via stereo mini-jack. Discrete analog 6-channel output (LINE_OUT plus 4CH_OUT) transmitted to Front and Surround amplified stereo PC speaker arrays via three stereo mini-jacks.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 2. Package, Pinout, and Signal Descriptions The 7mm x 7mm 48-pin QFP package originally selected for AC ‘97 audio-only Codecs has become prevalent throughout the industry. Vendors are recommended to follow the 48-pin package pinout assignments as closely as possible. Modem Codec (MC) and Combo Audio/Modem Codec (AMC) packaging and pinouts are entirely vendor specific. 2.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Key Dimension D 9.00 mm D1 7.00 mm E 9.00 mm E1 7.00 mm A (lead width) 0.20 mm e (pitch) 0.50 mm Z 1.00 mm Figure 4. AC ‘97 48-pin package dimensions 2.2 Pinout Table 1 gives the pinlist for the 48-pin QFP package.
AC ‘97 Component Specification 2.3 Revision 2.3 Rev 1.0 Signal Descriptions 2.3.1 Power and Ground It is recommended that the digital portion (logic and AC-link interface) of AC ‘97 Controllers and Codecs operate at 3.3V (see DC Characteristics in Section 9.1). The analog runs at AVdd = 5V or AVdd = 3.3V. Pin Signal Name Type Description 1 DVdd1 I Digital Vdd (3.3V recommended) 4 Dvss1 I Digital Gnd 7 Dvss2 I Digital Gnd 9 DVdd2 I Digital Vdd (3.
AC ‘97 Component Specification Type Revision 2.3 Rev 1.0 Pin Signal Name Description 43 GPIO0 IO Optional Vendor specific GPIO 44 GPIO1 IO Optional Vendor specific GPIO 45 ID0# I Codec ID strap pin (or Generic Cap) 46 ID1# I Codec ID strap pin (or Generic Cap) 47 EAPD O External Amplifier Power Control pin 48 SPDIF_OUT O S/PDIF output (or Vendor specific) Table 4. Digital I/O Signal Descriptions 2.3.3.1 S/PDIF transmitter pin assignment S/PDIF capable AC ‘97 2.
AC ‘97 Component Specification Pin 12 Signal Name Reserved / PC_BEEP Revision 2.3 Rev 1.
AC ‘97 Component Specification 2.3.5 Revision 2.3 Rev 1.0 Filter/References These signals are connected to resistors, capacitors, or specific voltages.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 3. Controller, Codec, and AC-link This section describes the physical and high-level functional aspects of the AC ‘97 Controller to Codec interface, referred to as AC-link. For a detailed description of AC-link protocols, slot and bit assignments, refer to Section 4. 3.1 AC-link Physical interface The AC ‘97 Codec communicates with its companion Digital Controller via the AC-link digital serial interface.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 AC'97 Clock Source Detection RESET# Signal Asserted BIT_CLK Toggling? Yes 12.288MHz signal on BIT_CLK is being generated externally; codec uses this signal as the clock. Yes 24.576MHz Crystal on XTL_IN and XTL_OUT used by codec to generate clock on BIT_CLK Yes 24.576 MHz signal on XTL_IN used by codec to generate 12.288MHz clock on BIT_CLK Yes 14.318 MHz signal on XTL_IN used by codec to generate 12.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 The beginning of all audio sample packets, or Audio Frames, transferred over AC-link is synchronized to the rising edge of the SYNC signal. SYNC is driven by the Controller. The Controller generates SYNC by dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This yields a 48 kHz SYNC signal whose period defines an audio frame.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Multiple Codec AC-link implementations must run off a common BIT_CLK. They can potentially save Controller pins by sharing SYNC, SDATA_OUT, and RESET# from the AC ‘97 Digital Controller. Each device requires its own SDATA_IN pin back to the Controller. This prevents contention of multiple devices on one serial input line. Support for multiple Codec operation necessitates a specially designed Controller.
AC ‘97 Component Specification 3.4 Revision 2.3 Rev 1.0 Clocking for Multiple Codec Implementations To keep the system synchronous, all Primary and Secondary Codec clocking must be derived from the same clock source, so they are operating on the same time base. In addition, all AC-link protocol timing must be based on the BIT_CLK signal, to ensure that everything on the AC-link will be synchronous. The following are potential 24.576 MHz clock options available to a Secondary Codec: 1.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 associated with being dependent on some other Codec’s clock being active. The AC ‘97 Digital Controller could be designed to manage power to the source of the high-speed clock. 3.5 AC-link Power Management 3.5.1 Powering down the AC-link The AC-link signals can be placed in a low power mode. When AC ‘97’s Powerdown Register (26h) is programmed to the appropriate value, both BIT_CLK and SDATA_IN are brought to and held at a logic low voltage level.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 3.5.2.2 Codec Initiates Wake-up A Codec (running off Vaux) can trigger a wake event (PME#) by transitioning SDATA_IN from low to high and holding it high until either a warm or cold reset is observed on the AC-link. This functionality is typically implemented in modem Codecs that detect ring, Caller ID, etc. For details, see Section 7.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 directional, fixed clock rate, serial digital stream. AC-link handles multiple input and output PCM audio streams, as well as control register accesses employing a time division multiplexed (TDM) scheme that divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution.
AC ‘97 Component Specification 4.2 Revision 2.3 Rev 1.0 AC-link Serial Interface Protocol The AC ‘97 Controller signals synchronization of all AC-link data transactions. The AC ‘97 Codec, Controller, or external clock source drives the serial bit clock onto AC-link, which the AC ‘97 Controller then qualifies with a synchronization signal to construct audio frames. SYNC, fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.
AC ‘97 Component Specification • • Revision 2.3 Rev 1.0 enables PCM DAC/ADC conversions at variable sample rates by write enabling Sample Rate Registers 2C34h.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 For Secondary Codec access, the AC ‘97 Digital Controller: 1. Sets the AC-link Frame valid bit (Slot 0, bit 15) 2. Invalidates the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13) 3. Places a non-zero value (01, 10, or 11) into the Codec ID field (Slot 0, bits 1 and 0) 4.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Figure 12. Start of an AC-link Output Frame SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions completed with 0’s by the AC ‘97 Controller. If there are less than 20 valid bits within an assigned and valid time slot, the AC ‘97 Controller always completes all trailing non-valid bit positions of the 20-bit slot with 0’s.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 The control interface architecture supports up to sixty-four (64) 16-bit read/write registers, addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are currently defined, odd register (01h, 03h, etc.) accesses are reserved for future expansion. Note that shadowing of the control register file on the AC ‘97 Controller is an option left open to the implementation of the AC ‘97 Controller.
AC ‘97 Component Specification 4.3.8 Revision 2.3 Rev 1.0 Slot 7: PCM L Surround DAC (or PCM L n+1) Slot 7 carries PCM L Surround data in 4- or 6-channel configurations (either single or multiple Codec implementations). This slot may also contain Double Rate Audio data for PCM L n+1 depending on the configuration of the DRSS bits in register 20h. 4.3.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Tag Phase 20.8 µs (48 kHz) Data Phase 12.288 MHz SYNC 81.4 ns BIT_CLK SDATA_IN End of previous Audio Frame Codec Ready slot(1) slot(2) slot(12) "0" "0" "0" 19 Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) 0 19 Slot 1 0 Slot 2 19 0 Slot 3 19 0 Slot 12 Figure 13. AC-link Input Frame A new AC-link input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK.
AC ‘97 Component Specification 4.4.1 Revision 2.3 Rev 1.0 Slot 0: TAG Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the AC ‘97 Codec is in the “Codec Ready” state or not. If the “Codec Ready” bit is a 0, this indicates that the AC ‘97 Codec is not ready for normal operation. This condition is normal following the deassertion of power on reset - for example, while the AC ‘97 Codec’s voltage references settle.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 during slot 0.) Status Address Port bit assignments: Bit(19) RESERVED (Stuffed with 0) Bit(18:12) Control Register Index (Echo of register index for which data is being returned) Bit(11:2) SLOTREQ bits See next section Bit(1,0) RESERVED (Stuffed with 0’s) The first bit (MSB) generated by AC ‘97 is always completed with a 0.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 out its 20-bit time slot. 4.4.6 Slot 5: Modem Line 1 ADC AC-link input frame slot 5 contains MSB justified, modem ADC output data (if the line Codec is supported). The optional modem ADC resolution is by default 16-bits. All trailing, non-valid bit positions will be completed with 0’s to fill out its 20-bit time slot. AC ‘97 Controller is then responsible for completing any non-valid trailing bit positions within this time slot with 0’s. 4.4.
AC ‘97 Component Specification Function AC ‘97 Digital Controller Primary Read Revision 2.3 Rev 1.0 Slot 0, bit 15 (Valid Frame) Slot 0, bit 14 (Valid Slot 1 Address) Slot 0, bit 13 (Valid Slot 2 Data) Slot 0, Bits 1-0 (Codec ID) 1 1 0 00 1 1 1 00 1 1 1 00 Frame N, SDATA_OUT AC ‘97 Digital Controller Primary Write Frame N, SDATA_OUT AC ‘97 Codec Status Frame N+1, SDATA_IN Table 11.
AC ‘97 Component Specification 4.5.4 Revision 2.3 Rev 1.0 The Codec-Ready Bit and Audio or Modem DAC/ADC Status Bits AC ‘97 compliance requires that Codec-Ready and audio or modem DAC/ADC status bits only change from “ready” to “not ready” in response to a PR state change issued by the Controller to the Powerdown Control/Status Registers 26h, 2Ah, or 3Eh.
AC ‘97 Component Specification • • • • 5.2 Revision 2.3 Rev 1.0 Amplified analog stereo headphone output (HP_OUT) transmitted to headphones or headset via stereo mini-jack. Discrete analog 4-channel output (LINE_OUT plus 4CH_OUT) transmitted to Front and Surround amplified stereo PC speaker arrays via dual stereo mini-jacks.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 audio sources, regardless of Controller architecture (host-based or hardware-accelerated Controllers). Double-rate audio. Support is also defined for optional 88.2 or 96 kHz DAC operation. Current PC-based DVD implementations recommend 96 (or 88.2) kHz audio to be down-sampled to 48 (or 44.1) kHz for high quality rendering.
AC ‘97 Component Specification • • • Revision 2.3 Rev 1.0 SRC mechanisms slot mapping configurations internal gains and phase inversions 5.4.2.1 Default Slot to DAC Mappings for Secondary Audio Codecs The AMAP bit, D9 in the Extended Audio ID Register (Register 28h), indicates whether or not the audio Codec supports AC ‘97 compliant default AC-link slot to audio DAC mappings.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 D13 control Powerdown for the Center, Surround, and LFE DACs respectively. When a 2-channel Secondary Codec is mapped as Surround L&R, Ready and Powerdown for Surround L&R are not implemented in Register 2Ah, and Register 26h must be used instead.
AC ‘97 Component Specification Revision 2.3 Rev 1.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 to support full resolution D/A conversions followed by analog attenuation as a means of achieving high SNR. 5.5.2 Analog Mixer Input The mixer input is a MUX design which offers the capability to record any of the audio sources or the outgoing mix of all sources.
AC ‘97 Component Specification • • • • • • 5.6 Revision 2.3 Rev 1.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 AC-link PCM Audio Data Format Bit Description 19-4 16-bit sample (MSB bit 19, LSB bit 4) 3-0 Optional: LSBs of 18 or 20-bit sample Table 14. Audio Slot Data Definitions AC-link Audio Interrupt Definition Bit Description 19-1 Reserved (Audio codec will return zeros in bits 19-1)10 0 Optional: Assertion = 1 will cause interrupt to be propagated to Audio controller system interrupt. See register 24h 11 definition for enabling mechanism.
AC ‘97 Component Specification Reg Name D15 D14 D13 D12 D11 Revision 2.3 Rev 1.
AC ‘97 Component Specification 5.7.1 Revision 2.3 Rev 1.0 Reset Register (Index 00h) Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 na Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement, if any.
AC ‘97 Component Specification SE4...SE0 3D Stereo Enhancement Technique 00000 (0) 00001 (1) 00010 (2) Revision 2.3 Rev 1.0 SE4...
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Mute Mx5...Mx0 Function Range 0 00 0000 0 dB Attenuation Req. 0 01 1111 46.5 dB Attenuation Req. 0 11 1111 94.5 dB Attenuation Optional 1 xx xxxx ∞ dB Attenuation Req. Table 19. Master, Aux Out, and Mono Volume 5.7.
AC ‘97 Component Specification 5.7.4 Revision 2.3 Rev 1.0 PC Beep Register (Index 0Ah) Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0Ah PC Beep Volume Mute X X F7 F6 F5 F4 F3 F2 F1 F0 PV3 PV2 PV1 PV0 X x000h This controls the level and frequency for the optional PC Beep. PV3-PV0 controls the volume of the input signal, if implemented, and the generated signal, if implemented. Each step corresponds to approximately 3 dB of attenuation.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 The default value for the mono registers is 8008h, which corresponds to 0 dB gain with mute on. The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on. Mute Gx4...Gx0 Function 0 00000 +12 dB gain 0 01000 0 dB gain 0 11111 -34.5 dB gain 1 xxxxx −∞ dB gain Table 22. Mixer Input Gain/Atten 5.7.
AC ‘97 Component Specification 5.7.7 Revision 2.3 Rev 1.0 Record Gain Registers (Index 1Ch and 1Eh) Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D0 Default 1Ch Record Gain Mute X X X GL3 GL2 GL1 GL0 X X X X GR3 GR2 GR1 D3 D2 D1 GR0 8000h 1Eh Record Gain Mic Mute X X X X X X X X X X X GM3 GM2 GM1 GM0 8000h 1Ch is for the stereo input and 1Eh is for the optional dedicated mic channel. Each step corresponds to 1.5 dB. 22.
AC ‘97 Component Specification 5.7.9 Reg Name 22h 3D Control Revision 2.3 Rev 1.0 3D Control Register (Index 22h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default X X X X CR3 CR2 CR1 CR0 X X X X DP3 DP2 DP1 DP0 0000h This optional register is used to control the center and/or depth of the 3D stereo enhancement function built into the AC ‘97 component.
AC ‘97 Component Specification Bit Default Function I4 0 Interrupt Status (R/W) Revision 2.3 Rev 1.0 0 - Interrupt is clear 1 - Interrupt was generated Interrupt event is cleared by writing a 1 to this bit. The interrupt bit will change regardless of condition of interrupt enable (I0) status. An interrupt in the GPI in slot 12 in the AC link will follow this bit change when interrupt enable (I0) is un-masked. If this bit is set, one or both of I3 or I2 must be set to indicate the interrupt cause.
AC ‘97 Component Specification 5.7.11 Revision 2.3 Rev 1.0 Powerdown Control/Status Register (Index 26h) Reg Name 26h Powerdown Ctrl/Stat D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC na This read/write register is used to program powerdown states and monitor subsystem readiness. The lower half of this register is read only status, with a 1 indicating that the subsection is “ready”.
AC ‘97 Component Specification 5.8 Revision 2.3 Rev 1.0 Extended Audio Register Set The extended audio registers support variable sample rate audio output and input, double-rate audio output, multichannel audio output, and S/PDIF output.
AC ‘97 Component Specification REV1, REV0 Revision 2.3 Rev 1.0 AC’97 Revision 00 Revision 2.1 or earlier 01 Revision 2.2 10 Revision 2.
AC ‘97 Component Specification • • • • SPSA[1,0] = 00 SPSA[1,0] = 01 SPSA[1,0] = 10 SPSA[1,0] = 11 Revision 2.3 Rev 1.0 S/PDIF source data assigned to AC-link slots 3&4 S/PDIF source data assigned to AC-link slots 7&8 [2-ch Primary Codec default] S/PDIF source data assigned to AC-link slots 6&9 [4-ch Primary Codec default] S/PDIF source data assigned to AC-link slots 10&11 [6-ch Primary Codec default] AMAP compliance is a requirement for AC ’97 2.2 Controllers and Codecs.
AC ‘97 Component Specification • • • Revision 2.3 Rev 1.0 should result in the “Validity” flag being set to “1”. In the case where the S/PDIF transmitter does is not receiving a sample or does not receive a valid sample from the AC’97 controller, (Left or Right), the S/PDIF transmitter should set the S/PDIF "Validity” flag to “0” and pad each of the S/PDIF “Audio Sample Word” in question with "0"s for the sub-frame in question.
AC ‘97 Component Specification 5.8.5 Revision 2.3 Rev 1.0 S/PDIF Control Register (Index 3Ah) Reg Name 3Ah S/PDIF Control D15 D14 V DRS D13 D12 SPSR1 SPSR0 D11 D10 D9 D8 D7 D6 D5 D4 D3 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE D2 D1 D0 COPY /AUDIO PRO Register 3Ah is a read/write register that controls S/PDIF functionality and manages bit fields propagated as channel status (or subframe in the V case).
AC ‘97 Component Specification 5.8.6 Revision 2.3 Rev 1.0 Vendor Reserved Registers (Index 5Ah - 5Fh, 70h - 7Ah) Reg Name 5Ah-5Fh, Vendor Reserved D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default X X X X X X X X X X X X X X X X X 70hh-7Ah These are reserved for vendor specific use. Driver writers should not access these registers unless the Vendor ID register has been checked first to ensure that the vendor of the AC ‘97 component has been identified.
AC ‘97 Component Specification 5.9 Revision 2.3 Rev 1.0 Extended Codec Registers Page ‘01’ The Extended Codec Registers Page ‘01’ implements an extended set of registers for identification and control of the codec. The Codec Class/Rev, PCI SVID, PCI SID registers provide extended information to identify the specific codec hardware and surrounding support hardware.
AC ‘97 Component Specification Bit Default RV[7:0] Revision 2.3 Rev 1.0 Function Revision ID: (RO) na This register specifies a device specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. This field should be viewed as a vendor defined extension to the codec ID. This number changes with new codec stepping of the same codec ID. CL[4:0] Codec Compatibility Class (RO) na This is a codec vendor specific field to define s/w compatibility for the codec.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 5.9.2.1 Function Select Register (Index 66h) Bit FC[3:0] Default 0h Function Function Code bits These bits specify the type of audio function described by this page. The codec must provide information in this register.
AC ‘97 Component Specification Bit Default Function G4 Codec default Gain Sign Bit Codec default Gain bits G[4:0] Revision 2.3 Rev 1.0 The codec updates this bit with the sign of the gain value present in G[3:0]. The BIOS updates this to take into consideration external amplifiers or other external logic when relevant. The codec updates these bits with the gain value (dB relative to level-out) in 1.5dBV increments.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 NOT provides sensing logic and this bit will be Read only. After a sense cycle is completed Indicates that no information is provided on the sensing method 1h – After codec Reset# de-assertion, it indicates the codec provides sensing logic for this I/O and this bit is Read/Write. After clearing this bit by writing “1”, when a sense cycle is completed the assertion of this bit indicates that there is valid information in the remaining descriptor bits.
AC ‘97 Component Specification Bit Default ST[2:0] Revision 2.3 Rev 1.0 Function Connector/Jack location bits This field describes the location of the jack in the system. 0h – Rear I/O Panel 1h – Front Panel 2h – Motherboard 3h – Dock/External 4h-6h - Reserved 7h – No Connection/unused I/O These bits are Read/Write. S[4:0] 1h Sensed bits relates to the I/O being sensed as either output or inputs. Sensed bits (outputs).
AC ‘97 Component Specification Revision 2.3 Rev 1.0 07h – SPDIF In (electrical) 08h – SPDIF In (TOS) 09h – Headset (mono speaker left channel and microphone. Read Functions 0 to 3 for matching DAC out) 0Ah – Other. Allows a vendor to report sensing other type of devices/peripherals. SR[5:0] together with OR[1:0] provide information regarding the type of device sensed. 0Bh-0Eh – Reserved 0Fh – Unknown (use fingerprint) 10-1Fh – Reserved This field is Read Only.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 A CODEC indicates that it does not support a given DAC or ADC by having a read only value of 0000b in the bits associated with the unsupported DAC or ADC. The MV bit is used to indicate that page 01 offsets 6Ch and 6Eh should be used to steer the slot to DAC/ADC mappings, rather than the DSA[1:0] bits in the Extended Audio ID register 28h.
AC ‘97 Component Specification • • • Revision 2.3 Rev 1.0 DA conversion rate may match the S/PDIF transmitter rate, or be independent SRC implementations differ Controller implementations differ Given the complexity, there needs to be agreement on minimum required concurrency support at 48 kHz, and a simple mechanism that enables the Driver to easily determine whether other S/PDIF configurations are supported (the SPCV bit is described above).
AC ‘97 Component Specification Revision 2.3 Rev 1.0 while transmitting 48 kHz independent S/PDIF source output, and are compatible with integrated multichannel audio Controllers. 5.10.1.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 thereby preserving 100% of the digital content. If supported, SPCV should indicate valid configuration when programmed as follows: • Register 2Ch controlling AC-link slots 3&4 DAC sample rates set to “xxxxh” (32, 44.1 or 48kHz) • Register 3Ah, field SPSR[1,0] controlling S/PDIF sample rate set to “xxh” (32, 44.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 performing a read operation over the link. Table 40 describes the GPIO output and input slot assignments. Input and Output Slot 12: GPIO Pin Status and Control Bit Description 19-4 GPIO Pin Status (see Table 41. Recommended Slot 12 GPIO Bit Definitions) 3-1 Vendor specific 0 GPIO_INT mask enabled input pin event interrupt (1=event) (input Slot 12 only) Table 40. Slot 12-Bit Definitions 6.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Interrupt •SDATA_IN (wake up) •GPIO_INT (slot 12, bit 0) Config (4Ch. n) (0=output) Other 15 bits... GPIO. n Output Wake (52h. n) Config (4Ch. n) GPIO. n Polarity (4Eh. n) •0=CMOS •1=Open Drain Sticky (50h. n) Config (4Ch. n) •0=Output •1=Input GPIO Status (54h. n) Q S Q R input buffer (non -inverting) Write ‘0’ to GPIO Status (54h. n) 1 1 0 Polarity (4Eh. n) •0=Low active •1=High active 0 Sticky (50h. n) . Figure 20.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 purpose. Recommended bit definitions are provided for maximum interoperability, and should be followed wherever possible. The suggested use for the International Bits 1-3 is to implement LINE12_AC, LINE12_DC, and LINE12_RS, which, when set to one, adjust the DAA AC impedance, DC impedance, and Ring Detect sensitivity to alternate values more suitable for some non-North American countries.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Current voice modem implementations migrate the controller functionality into the modem driver, eliminate the redundant voice Codec, and rely on low latency digital streaming between the modem and audio drivers. AMC designs may optionally implement the PHONE and MONO_OUT connections internally to save package pins. For certification reasons, care should be taken to limit the bandwidth of analog audio signals coupled to the modem Tx via MONO_OUT. 6.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 SYNC BIT_CLK SDATA_OUT SDATA_IN slot 12 prev. frame TAG slot 12 prev. frame TAG Write to 0x26 Data PR4 Figure 22. AC-link Low Power Mode In response to this command BIT_CLK and SDATA_IN Codec, and SDATA_OUT controller outputs go low and stay low.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 then low. PME# is cleared out in the AC ‘97 Digital Controller by system software, asynchronous to AC-link activity. The AC ‘97 Digital Controller must always monitor the Codec’s ready bit before sending data to it. 6.5.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 initialize. In the case of the combined Codec (AMC ‘97 ), the entire Codec, AC-link, and portions of the AC ‘97 Digital Controller are powered by Vaux which enables Caller ID decode and store to be done either by the controller or by the modem AFE Codec. However in the case of the split partitioned design, only the MC ‘97 SDATA_IN signal on the AC-link is powered while the remainder of the AC-link is un-powered.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 the newly-defined Extended AC ‘97 registers.
AC ‘97 Component Specification 6.6.3 Revision 2.3 Rev 1.
AC ‘97 Component Specification 6.6.4 Revision 2.3 Rev 1.
AC ‘97 Component Specification 6.6.8 Revision 2.3 Rev 1.0 GPIO Pin Wake-up Mask Register (Index 52h) Reg Name 52h GPIO Pin Wake-up (0 =no int, 1=yes int) D15 D14 D13 D12 D11 D10 D9 GW15 GW14 GW13 GW12 GW11 GW10 GW9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default GW8 GW7 GW6 GW5 GW4 GW3 GW2 GW1 GW0 0000h The GPIO Pin Wake-up is a read/write register that provides a mask for determining if an input GPIO change will generate a wake-up or GPIO_INT (0=No, 1=Yes).
AC ‘97 Component Specification Revision 2.3 Rev 1.0 is about to be placed in a low power mode with BIT_CLK stopped. In a typical AC + MC, or AMC configuration the audio Codec is deployed as the Primary Codec, and the modem Codec is deployed as the Secondary Codec. Setting the MLNK bit, given one of these common configurations is problematic.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Digital A B Analog Digital DAC C Analog DAC D E I/O Pad DAC output I/O Pad ADC input AC Link F G Digital ADC H Analog ADC I J Figure 26. Loopback points 6.7.1 ADC Loopback '001' The ADC Loopback takes the line input signal to the ADC and routes it back to the Line output. This loop includes the analog functions in the receive and transmit path.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 7. Power Management AC ‘97 Codecs can operate at reduced power when no activity is required, and need to be a fully static design, so that when the clock is stopped the registers will not lose their values. For 2-channel audio Codecs low power states are controlled by bits D8-D15 in the Powerdown Register, 26h (see Table 29 for full definitions).
AC ‘97 Component Specification Revision 2.3 Rev 1.0 follows the previous one, except that the analog mixer is not shut down. 7.1 Power Management “D State” Mappings for Audio Codecs The ACPI and PCI Bus Power Management Interface specifications define an accepted set of device power management states (D0 – D3). An audio device driver written to comprehend these power management specifications must map each supported system-side D state to an audio Codec-specific power savings mode using the PR bits.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 resume latency, etc., is available in the Microsoft Communications Device Class Power Management Reference Specification** located at: http://www.microsoft.com/hwdev/download/compmspc.rtf Table 45 details a lower-level mapping of the modem subsystem D states to the recommended MC ‘97 Codec power savings PR settings. +3.3 Vmai n +3.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 If the modem Codec has been enabled to wake the system, and a power management event occurs (such as the phone ringing), then the modem Codec complies with the behavior specified in Section 6.5.2. 7.3.2 Secondary MC’97 Codec and MLNK Setting the MLNK bit when transitioning a Secondary modem Codec to the D3hot state requires different behavior from the modem Codec than what is required from a Primary modem Codec.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 state of the Codec(s), and the power management state of the system. Table 46, Table 47, and Table 48 break down the AC-link behavior that must occur when resuming the AC-link as a function of audio Codec device state, modem Codec device state, and system state.
AC ‘97 Component Specification Audio Codec Modem Codec System State D-State D-State (ACPI: S0-S5) D0 D0 D0 Revision 2.3 Rev 1.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 modem Codec can use the low-to-high transition on RESET# as a reliable indication that power has been reestablished on the AC-link, and that an actual resume reset has occurred. An AC ‘97 2.3 Controller/Codec arrangement deployed as a PCI add-in card could have its AC-link RESET# signal follow the PCIRST# signal directly since PCIRST# will always be asserted whenever the system is sleeping in S3, S4 or S5. 7.5 Power Distribution The AC ‘97 Revision 1.
AC ‘97 Component Specification +3.3 Vmain Revision 2.3 Rev 1.0 +5 Vmain +12 Vmain +3.3 Vdual (3.3 Vaux) AC-link (Codec outputs) • BIT_CLK • SDATA_IN 9 9 AC-link (contrl. outputs) • SYNC • SDATA_OUT • RESET# 9 9 9 MC’97 digital logic 9 MC’97 analog circuitry 9 (note 1) Note 1: Modem codecs that do not support hardware capture of caller ID during ACPI S3 or S4 states may alternatively power their analog circuitry with either 3.3 Vmain or 5 Vmain. Table 49.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 that are shut off when the PC enters an ACPI sleep state of S3, S4 or S5. Additionally it enables the modem Codec to power its wake logic when in an S3, S4 or S5 ACPI sleep state. 7.5.3 AMC ‘97 (Primary) Implementations The AMC ‘97 combination Codec must implement the same power distribution strategy as for the split partitioned AC + MC Codec configuration.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 8. Testability 8.1 Activating the Test Modes SYNC SDATA_OUT Description 0 0 Normal AC ’97 operation 0 1 ATE Test Mode 1 0 Vendor Test Mode 1 1 Reserved Table 51. Test Mode Activation AC ‘97 has two test modes. One is for ATE in circuit test and the other is for vendor-specific tests. All AC-link signals are normally low through the trailing edge of RESET#.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 9. Digital DC and AC Characteristics 9.1 DC Characteristics Parameter Symbol Min Typ Max Units Digital Power Supply DVdd 3.135 3.3 3.465 V Input voltage range Vin -0.30 - DVdd + 0.30 V Low level input voltage Vil - - 0.35 x DVdd V High level input voltage Vih 0.65 x DVdd - - V High level output voltage Voh 0.90 x DVdd - - V Low level output voltage Vol - - 0.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Trst2clk Trst_low RESET# Ttri2actv BIT_CLK Ttri2actv SDATA_IN Figure 29. Cold Reset timing diagram when the codec is supplying the BIT_CLK signal RESET# Trst_low Tclk2rst BIT_CLK Ttri2actv SDATA_IN Figure 30 Cold Reset timing diagram when BIT_CLK is being provided by an external source. Parameter Symbol Min Typ Max Units RESET# active low pulse width Trst_low 1.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Parameter Symbol Min Typ Max Units SYNC active high pulse width Tsync_high 1.0 - - µs SYNC inactive to BIT_CLK startup delay Tsync2clk 162.8 - - ns Table 54. Warm Reset timing parameters Please note that this minimum SYNC pulse width pertains to warm reset only, during normal operation SYNC is asserted for the entire tag phase (16 BIT_CLK times). 9.2.2 AC-link Clocks Figure 32.
AC ‘97 Component Specification 9.2.3 Revision 2.3 Rev 1.0 Data Output and Input Times tco tsetup Vih Vil BIT_CLK SDATA_OUT SDATA_IN SYNC Voh Vol thold Figure 33. Data Output and Input Timing Diagram Parameter Symbol Min Typ Max Units Output Valid Delay from rising edge of BIT_CLK tco - - 15 ns Note: 47.5-75pF external load as per Table 62 Table 56.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Rise and Fall times, flight times, Output Valid Delay, Input Setup and Hold, and worst case capacitive loads (see Section 9.2.7) should be used together for modeling of the AC-link output pin drivers. For example, the following worst case scenario situates the Primary Codec along with a Secondary Codec on a riser 15 inches from the Controller. The AC-link BIT_CLK, SYNC, and SDATA_OUT signals are loaded with ~55 pF external capacitance.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 AC ‘97 2.3 maintains the original specified BIT_CLK, SYNC, SDATA_OUT, and SDATA_IN signal rise and fall times. These signals must also meet the Output Valid Delay time with respect to the rising edge of BIT_CLK specified in Table 56. Modeling of the AC-link output pin drivers should include rise and fall times, flight times, and external capacitive and inductive loads, which could be as large as 75 pF.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 Parameter Symbol Min Typ Max Units Setup to trailing edge of RESET# (also applies to SYNC) Tsetup2rst 15.0 - - ns Rising edge of RESET# to Hi-Z delay Toff - - 25.0 ns Table 61. ATE test mode timing parameters All AC-link signals are normally low through the trailing edge of RESET#. 1.
AC ‘97 Component Specification RESET, SYNC, & SDATA_OUT Revision 2.3 Rev 1.0 1 Codec 2 Codecs 3 Codecs 4 Codecs Controller Output Pin Capacitance 7.5pF 7.5pF 7.5pF 7.5pF Motherboard Trace Capacitance (Note 1) 30pF 30pF 30pF 30pF Codec Input Pin Capacitance (Note 2) 7.5pF 15pF 22.5pF 30pF Riser Connector Capacitance 2.5pF 2.5pF 2.5pF 2.5pF CNR Trace Capacitance (Notes 3 & 4) 0pF 7.5pF 12.5pF 15pF Total Capacitance driven by output pin 47.5pF 62.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 sine wave; Sample Frequency = 48 kHz; 0 dB = 1Vrms, 10KΩ/50pF load, Testbench Characterization BW: 20 Hz – 20 kHz, 0 dB attenuation; tone and 3D disabled) Parameter Min Typ Max Units Line Inputs - 1.0 - Vrms Mic Inputs1 - 0.1 - - - - Line Output - 1.0 - Headphone Output - - 1.41 90 - - - 85 - 20 - 20,000 Hz D/A 85 90 - dB A/D 75 80 - Line Output4 - - 0.02 Headphone Output5 - - 1.
AC ‘97 Component Specification Revision 2.3 Rev 1.0 (5) +3 dB output into 32 Ω load (6) ±0.25 dB limits (7) Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. (8) The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth of 28.8 to 100 kHz, with respect to a 1VRMS DAC output. (9) Gain step size 1.5 dB is true for all attenuators except for PC_BEEP, which has 3.0 dB step size. Appendix A.
AC ‘97 Component Specification Reg Name D15 D14 D13 D12 D11 Revision 2.3 Rev 1.
AC ‘97 Component Specification D15 Reg Name 28h Extended Audio ID ID1 ID0 x x 2Ah Ext’d Audio Stat/Ctrl VCFG PRL PRK PRJ PRI 2Ch PCM Front DAC Rate SR15 SR14 SR13 SR12 SR11 2Eh PCM Surr DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 30h PCM LFE DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 32h PCM L/R ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 34h MIC ADC Rate SR15 SR14 SR
