Accelerated Graphics Port Interface Specification

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Revision: 0.8.1

Original Date: December 1999

Revision: 1.0

Original Date: September 2002

AGP V3.0

Interface Specification

Summary of content (143 pages)

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AGP V3.0 Interface Specification Revision: 0.8.1 Original Date: December 1999 Revision: 1.
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AGP3.0 Interface Specification Rev. 1.0 This Page is intentionally left blank.
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AGP3.0 Interface Specification Rev. 1.0 Revision History Revision # V0.9 V0.91 Date Nov. 2000 Dec. 2000 V0.91R Apr. 2001 V0.95 May 2001 V1.0 August 2002 Description First public release of the draft specification Several corrections made after initial review. Major items listed below: • FW made optional for both target and master – Sections: 2.7.4, 2.7.5, 5.8.4, 5.8.5 • SBA requests may start on any SB_STBx edge – Section: 2.1.2 • Clarification on “sticky” Type requests on SBA – Section: 2.3.
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AGP3.0 Interface Specification Rev. 1.0 This specification is provided “AS IS” with no warranties whatsoever including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted or intended hereby.
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AGP3.0 Interface Specification Rev. 1.0 Table of Contents 1 INTRODUCTION AND OVERVIEW .......................................................................11 1.1 Organization of This Document..................................................................................................11 1.2 Reference Documents ...............................................................................................................12 1.3 Need for AGP3.0 ..........................................................
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AGP3.0 Interface Specification Rev. 1.0 3.4.1 AGP3.0 Signaling Details .....................................................................................................63 3.4.2 Signaling Details for Non-AGP3.0 Signals ...........................................................................65 3.5 System Topologies and Specifications ......................................................................................66 3.5.1 Universal AGP3.0 Topologies ...............................................
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AGP3.0 Interface Specification Rev. 1.0 5.3.1 AGP Aperture Page Size....................................................................................................117 5.3.2 AGP Graphics Aperture Requirements..............................................................................117 5.3.3 GART Overview .................................................................................................................118 5.3.4 GART Requirements.........................................................
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AGP3.0 Interface Specification Rev. 1.0 List of Figures Figure 2-1: 8X SBA Addressing Showing Three Consecutive SBA Requests........................................19 Figure 2-2: 8X Data Transfers on AD Interface .......................................................................................19 Figure 2-3: Minimum TRDY and AD_STB Timing Relationship ..............................................................21 Figure 2-4: AGP3.0 Calibration Cycle ..................................................
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AGP3.0 Interface Specification Rev. 1.0 List of Tables Table 1: AGP Specification Releases ......................................................................................................11 Table 2: V2.0- Compatibility .....................................................................................................................13 Table 3: Changes to AGP2.0 in Core Specs ...........................................................................................14 Table 4: Changes to AGP2.
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AGP3.0 Interface Specification Rev. 1.0 Table 50: AGP3.0 Interconnect Requests .............................................................................................102 Table 51: Isochronous Status ID Codes ................................................................................................104 Table 52: The Synchronization Sequence of Data from Processor to AGP .........................................110 Table 53: The Synchronization Sequence of Data from AGP to the Processor ..........
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AGP3.0 Interface Specification Rev. 1.0 1 Introduction and Overview The AGP V3.0 Interface Specification (or AGP3.0) describes enhancements to the Accelerated Graphics Port (AGP) Interface. AGP3.0 offers a significant increase in performance along with feature enhancements to AGP2.0. This interface represents the natural evolution from the existing AGP to meet the ever-increasing demands placed on the graphic interfaces within the workstation and desktop environments. While AGP3.
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AGP3.0 Interface Specification Rev. 1.0 Finally, Appendix C contains a glossary of terms used throughout this document. 1.2 Reference Documents The following documents should be used as supporting reference material: 1. 2. 3. Accelerated Graphics Port Interface Specification, V2.0 AGP System Design Guide, V1.5 PCI Local Bus Specification, V2.2 1.3 Need for AGP3.0 In the past, AGP bandwidth has been scaled up at regular intervals. AGP1X and 2X were introduced simultaneously, and AGP2.
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AGP3.0 Interface Specification Rev. 1.0 Table 2: V2.0 Compatibility AGP3.0 Feature Impact Uses the same connector and signal pins as AGP4x with a few additional signals to support the new signaling. Uses the same AGP 1.5 V and Universal AGP connectors as AGP2.0. Common Clock remains at 66 MHz. Same flow control and PCI speeds. Buffering needs for Source Synchronous transfers double relative to AGP4X. Same protocol and flow control as AGP. Maintains interface level backward compatibility.
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AGP3.0 Interface Specification Rev. 1.0 1.5.1 Changes to AGP The tables that follow describe the changes to AGP2.0. Descriptions of these changes are in the chapters and appendices that follow. Table 3: Changes to AGP2.0 in Core Specs Change Section Classification Core-logic Impact Graphics Card Impact 8X (533MT/s) transfer rate for Data and Side-band Address (SBA) 2.1.2 Performance Required Required 2.
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AGP3.0 Interface Specification Rev. 1.0 Table 4: Changes to AGP2.0 in Appendices A and B Core-logic Impact Graphics Card Impact Support for Isochronous Transactions. Change 4.1 Feature Addition Optional Optional Hardware enforced coherency inside GART region selectable on Page basis. 5.4 Feature Enhancement Optional Optional Flow Control Change on Fast Writes. 4.2.2 Feature Enhancement No Impact Required Multiple AGP Ports support. 5.2.
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AGP3.0 Interface Specification Rev. 1.0 2 Description of New Features This chapter describes the AGP3.0 features that differ from AGP2.0 and covers the following areas: 1. 2. 3. 4. Signal Interface Differences Transaction and Protocol Differences Platform Dependencies Programming Changes The electrical specification that describes the signaling scheme is in Chapter 3. All other changes that apply to the core specification are included in this chapter.
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AGP3.0 Interface Specification Rev. 1.0 Table 5: Signal List AGP2.0 Signal AGP3.0 Signal Signaling Scheme in AGP3.0 Max Signaling Rate in AGP3.0 Assertion Level in AGP3.0 SBA SBA#1 AGP3.0 signaling 533MT/s/Source Synch 1=Low; 0=High SB_STB, SB_STB# SB_STBF, SB_STBS AGP3.0 Signaling 266MHz 1=High; 0=Low AD AD AGP3.0 Signaling 533MT/s/Source Synch 1=High; 0=Low AD_STB[1:0], AD_STB#[1:0] AD_STBF[1:0], AD_STBS[1:0] AGP3.0 Signaling 266 MHz 1=High, 0=Low AGP3.
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AGP3.0 Interface Specification Rev. 1.0 Table 6: AGP3.0 New Signals Name Type of Change Type Description AGP_Vrefcg Redefined Static This pin is used by the motherboard (or core-logic) to supply AGP Vref or AGP3.0 Vref to the graphics card based on the configuration detected. AGP_Vrefgc Redefined Static This pin is used by the Graphics Card to supply AGP or AGP3.0 Vref to the motherboard based on the configuration detected.
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AGP3.0 Interface Specification Rev. 1.0 may start at any rising SB_STBF edge within a common clock cycle at the AGP3.0 Master. The Master must insert NOPs into any unused request slots. 3. The two strobes SB_STBF and SB_STBS alternately use the L->H edge to latch the SBA data. The illustration in Figure 2-1 shows the one strobe as the inverse of the other. However, the specification does not require this.
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AGP3.0 Interface Specification Rev. 1.0 The major change from AGP2.0 is that the number of source synchronous AD transfers that happen within a common clock period has doubled. The timing parameters, t1, t2, and t3, have values different from AGP2.0 to account for AGP3.0 signaling technology. The relationship between TRDY and the 8X data transfer remains the same as the relationship between TRDY and the 4X data transfer that is in AGP2.0.
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AGP3.0 Interface Specification Rev. 1.0 Last th) Data Latched in her First Data in receiver 1 2 CL A 1 2 3 4 5 t3max 3 Data Master’ Commo Cloc Domai In Cycle 3 . 6 7 AD_STB AD_STB TRD t1min t2 min Figure 2-3: Minimum TRDY and AD_STB Timing Relationship Figure 2-3 shows the minimum delay between common clock and AD_STB (and the corresponding data). The delay t1min represents the earliest the first data is latched into the receiver using the strobe.
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AGP3.0 Interface Specification Rev. 1.0 dynamic calibration approaches can be utilized. In a static approach, the design accommodates, up front, the worst-case changes within the three variables. A dynamic calibration approach will adjust the parameters as changes in the variables occur. Process variations need only be adjusted once. Voltage and temperature, however, will change during operation and any buffer characteristic change beyond specification must be adjusted dynamically.
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AGP3.0 Interface Specification Rev. 1.0 transactions, designs are strongly encouraged to not delay the assertion of IRDY or TRDY by more than 8 clock cycles, i.e. beyond T10. 6. Once the Core-logic asserts IRDY it must keep it asserted until it samples TRDY asserted. It will then de-assert IRDY to end the calibration cycle. 7. Similarly, once the Graphics chip asserts TRDY, it must continue to assert it until it samples IRDY asserted upon which it will de-assert TRDY and end the calibration cycle. 8.
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AGP3.0 Interface Specification Rev. 1.0 Earliest that IRDY or TRDY can be asserted T1 T2 T3 T4 T5 AGP CLK ST[2:0] 11 000 Next GNT IRDY Delayed 1 TRDY AD[31:0] C#/BE[3:0] Figure 2-4: AGP3.0 Calibration Cycle 2.1.4.1 SBA Group Calibration The SBA interface calibration is initiated by the AGP3.0 Master (Graphics Chip) and is triggered by the calibration cycle. Soon after the calibration cycle is completed (IRDY and TRDY have been asserted), the AGP3.
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AGP3.0 Interface Specification Rev. 1.0 Minimum 8 Cycles 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T1 2 Cycles A.G.P. CLK SB_STBF Master must not glitch Strobes for 6 cycles Com Update 8X transfers resum e Min 16 16-bit NOP Commands SBA[7:0]# * ^ sync cycle * Since SBA has inverted polarity in AGP3.0, the logical value of Sync = FEh while the electrical value is LLLL LLLH.
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AGP3.0 Interface Specification Rev. 1.0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T19 T20 T21 T22 AGP CLK ST[2:0] 110 000 GNT IRDY TRDY SBA[7:0]# 5 clocks SBA Sync Allowed AD Calibration Cycle 4 clocks minimum (5 in this example) 4 clocks 12 clocks No SBA Sync Allowed during this period Target tests for SBA activity Master & Target may calibrate SBA (SB_STBx may glitch) Figure 2-6: SBA Calibration When SBA Strobes are Stopped 2.1.4.
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AGP3.0 Interface Specification Rev. 1.0 mode is enabled. The Master can initiate FRAME based cycles as soon as its BME bit is set in its command register. The reset condition sets the default value of PCAL_CYCLE to ‘0’, which translates to a 4ms period. Once the initial calibration period is over, the normal operation is started by the core-logic. Calibration Cycles can only start after the initial calibration period is completed. Calibration will precede setting the AGP_Enable bit.
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AGP3.0 Interface Specification Rev. 1.0 Table 8: DBI Implementation Requirements Signaling Mode Transfer Speed Transmitter DBI Receiver DBI AGP V3.0 8X Required Required AGP V3.0 4X Optional Required AGP V3.0 Frame Based PCI Optional Required AGP 1.0 or 2.
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AGP3.0 Interface Specification Rev. 1.0 2.1.5.1 AGP Connector Pins for DBI On the AGP connector, DBI_LO is assigned the pin B14 (reserved in AGP2.0 specification), and DBI_HI is assigned the pin A12 (used for PIPE# in AGP2.0 specification). The implication of using A12 for DBI_HI is that in designs that are “universal” and can operate in AGP2.0 or AGP3.0 modes, both the Master and Target must multiplex PIPE# and DBI_HI on the same wire. However, for a given mode of operation (AGP2.0 or AGP3.
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AGP3.0 Interface Specification Rev. 1.0 Table 10: Summary of PCI Signals Based on Function and Agent Device Graphics Interface PCI Target AGENT FRAME IRDY TRDY STOP DEVSEL IDSEL PERR SERR REQ GNT RST# AD[31::00] C#/BE[3::0] DBI_HI, DBI_LO PAR LOCK INTA# INTB# CLK PME# R R R R R R1 R O Master R R R R R R R R R R NS O O R O Core-logic AGP3.
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AGP3.0 Interface Specification Rev. 1.0 Legend: R = Required O = Optional I = Internal signal NS = Not supported A shaded cell indicates that the signal is not applicable to the function. / NOTE 1. The AGP Master does not require RBF if it can always accept the return of Read data. 2. The AGP Master does not require WBF if it always can accept the first block of FW data. 3. ST signals are only optional to the PCI master if no AGP support is implemented. 2.2.
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AGP3.0 Interface Specification Rev. 1.0 2.3.2 Removal of Transaction Types AGP3.0 removes the use of certain AGP2.0 transactions, which are now classified as reserved events. The core-logic response to these reserved transactions is implementation specific and beyond the scope of this specification. 2.3.2.1 High Priority Transactions AGP3.0 does not support the AGP High Priority Read and Write transactions.
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AGP3.0 Interface Specification Rev. 1.0 The “CCCC” field contains the Bus operation or request as itemized in Table 12. Table 12: AGP3.0/AGP2.0 Bus Requests CCCC AGP2.0 AGP3.
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AGP3.0 Interface Specification Rev. 1.0 any padding that is necessary. This is the same as AGP2.0 except that the amount of required padding could be 8, 16, or 24 bytes. 2.3.3 Flow Control The maximum AGP3.0 data rate (AGP8X) is twice that of AGP2.0. However, the signals that are used for flow-control by the AGP3.0 Master and Target, as well as the timing relationships, remain the same as AGP2.0.
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AGP3.0 Interface Specification Rev. 1.0 have at least 128 bytes of buffering. This is double that of AGP2.0 which requires a minimum of 64 bytes. Subsequent transfers may be stalled on a block-by-block basis with the suppression of TRDY at the predefined throttle point. 1 2 3 4 5 6 7 8 9 CLK FRAME AD C/BE 1s t Block (128B) 2nd Block (64B) ADD WAIT CMD WAIT AD_STBF IRDY TRDY STOP WBF DEVSEL Throttle Point Figure 2-8: Fast-Write Showing Wait State Insertion 2.3.3.
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AGP3.0 Interface Specification Rev. 1.0 1 2 3 4 5 6 7 8 9 CLK 8-29 AD RD1 32B | RD2 64B | STALL |RD3 32B | RD4 32B |RD5 32B |RD6 AD_STBF AD_STBS RBF TRDY GNT ST[2::0] xx 000 000 xxx xxx 000 000 000 000 00 Figure 2-9: Use of RBF in Read Transaction Control In Figure 2-9, RBF is not able to stop the two pipelined GNTs from completing their transactions. (These are labeled RD1 and RD2 in the diagram.
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AGP3.0 Interface Specification Rev. 1.0 AGP3.0 write transactions in the same order as the issued requests from the AGP3.0 Master. This implies that a sequence of writes, AGP_write_memA/AGP_write_memB, may complete in nonsequential order, such as memB being updated before memA. An exception to this rule occurs when a sequence of writes target the same memory location. The Target must ensure that a sequence of writes to the same memory location is completed in the same order as issued by the master.
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AGP3.0 Interface Specification Rev. 1.0 2.4 Platform Architecture Differences This section deals with changes to AGP that have platform level dependencies. These include support for hardware- enforced coherency, peer-to-peer access models, and system configuration issues. 2.4.1 Hardware Enforced Cache Coherency The AGP Master performs AGP or PCI transactions that are directed at system memory, with a single address space being associated with all these transactions.
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AGP3.0 Interface Specification Rev. 1.0 2.4.2 AGP3.0/AGP2.0 Compatibility AGP3.0 and AGP2.0 use the same connector and signal interface with a few additions. This means that in addition to the configurations allowed in the AGP specification, several new ones are created. The following tables define the various motherboard and card types that will be considered in this section. Table 15: Motherboard Options Connector Type Description AGP 3.3 V Motherboard Motherboard Types 3.
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AGP3.0 Interface Specification Rev. 1.0 The AGP3.0 Specification does not preclude a universal motherboard or add-in card from supporting 3.3V. Refer to sections 4.3.4 - 4.3.6 and 4.3.8 of the AGP Specification, revision 2.0 for further details on a Universal Motherboard implementation. Refer to the AGP2.0 Add-in Card ECN #53 for further details on Universal Add-in card implementation. Table 16: Graphics Card Options Graphics Card Types Connector Type AGP 3.3 V Card Description Supports only AGP 3.
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AGP3.0 Interface Specification Rev. 1.0 Table 17: Selecting Platform Mode of Operation Motherboard Graphics Card MB_DET pin on motherboard GC_DET pin on Graphics Card TYPEDET pin on Graphics Card Mode Speed of Operation AGP3.3V/UAGP/ UAGP3.0 AGP3.3V AGP3.3V Don’t Care Open Open AGP3.3V 1x, 2x UAGP/UAGP3.0/ AGP3.3V AGP1.5V/UAGP AGP3.0 Only UAGP3.0 AGP1.5V/UAGP AGP1.5V/UAGP Don’t Care Open AGP3.
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AGP3.0 Interface Specification Rev. 1.0 The core-logic or graphics card that supports “universal” AGP3.0 must dynamically change the meaning of AGPSTAT [2:0] based on the setting of AGPSTAT [3]. The selection of the speed of operation is done by software, which looks at the supported speeds in the core-logic and graphics card to pick one that is common to both.
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AGP3.0 Interface Specification Rev. 1.0 2.5 AGP3.0 Programming The configuration of registers in the AGP port, for the core-logic and graphics card is described below. This has not changed from AGP2.0. However, there are changes to some of the fields in the NCAPID, AGPSTAT and AGPCMD registers. These are described in this section. Additional changes to support certain workstation specific optional features are described in Appendix B.
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AGP3.0 Interface Specification Rev. 1.0 2.
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AGP3.0 Interface Specification Rev. 1.0 2.7 Required Master and Target Registers 2.7.1 PCISTS: PCI STATUS REGISTER Offset: 06h Size: 2 bytes Table 23: PCI Register Bits 15:5 4 Access R-IW Field Description See the PCI Local Bus Specification. If the CAP_LIST bit is set, the device’s configuration space implements a list of capabilities. The capability pointer is located at 34h. See the PCI Local Bus Specification. CAP_LIST 3:0 2.7.
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AGP3.0 Interface Specification Rev. 1.0 2.7.3 NCAPID: AGP IDENTIFIER REGISTER Offset: CAPPTR Size: 4 bytes MAJOR AND MINOR REVISION ID NUMBER Table 25: Major/Minor Revisions Bits Access Field 31:24 23:20 RZ-IW R-IWD’0011 Reserved MAJOR 19:16 R-IWD’0000 MINOR 15:8 R-IW-Dx NEXT_PTR 7:0 R-IWD’CAPID Value CAP_ID Description Always returns 0 on read; write operations have no effect. Major revision number of AGP3.0 interface specification this device conforms to.
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AGP3.0 Interface Specification Rev. 1.0 2.7.4 AGPSTAT: AGP STATUS REGISTER Offset: CAPPTR + 04h Size: 4 bytes Table 27: AGP Register Bits Access Field Description 31:24 MST: R1-IW TGT: R-IW-Dx RQ 23:16 15:13 RZ-IW MST: RZ-IW TGT: R-IW-D’x Reserved ARQSZ 12:10 R-IW-Dx CAL_Cycle 9 R1-IW Reserved (SBA) 8 7 6 RZ-IW RZ-IW Reserved Reserved Always returns 0 when read; write operations have no effect. Always returns 0 when read; write operations have no effect.
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AGP3.0 Interface Specification Rev. 1.0 Bits 2:0 Access R-IW Field Description AGP3.0_MODE = 0, the RATE field (AGPSTAT[2:0]) and DRATE field (AGPCMD[2:0]) in both the master and target must function as defined by the AGP Interface Specification V2.0 for compatibility with existing software. Data Rate Support (RATE) - RATE AGPSTAT[3] 0 1 1 1 1 Code xxx 001 010 011 All other codes Speed Supported See AGP2.0 Specs 4x 8x 4, and 8x Reserved 2.7.
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AGP3.0 Interface Specification Rev. 1.0 Bits Access Field Description 9 R-W-D’0 SBA_ENABLE This must be a read/write bit for software compatibility with AGP interface specification V2.0. AGP3.0 devices are required to support side band addressing. This bit must be set to 1’b when AGPSTAT[3] = 1. 8 R-W-D’0 AGP_ENABLE Master: Setting the AGP_ENABLE bit allows the master to initiate AGP3.0 operations. When cleared, the master cannot initiate AGP3.0 operations.
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AGP3.0 Interface Specification Rev. 1.0 2.8 AGP3.0 Connector Pin-outs Both Universal AGP3.0 and AGP3.0 motherboards use the same AGP connectors as AGP2.0. A few additional signals have been defined to take the place of previously reserved pins. Furthermore, the polarity of certain signals is different from AGP. Table 29 contains the updated pin assignments. Table 29: AGP3.0 Motherboard Connector Pinout Pin# B A Pin# B A Pin# B A 1 OVRCNT# 12V 23 GND GND 45 KEY KEY 2 5.
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AGP3.0 Interface Specification Rev. 1.0 3 AGP3.0 Physical Layer Specification The AGP3.0 Physical Layer Specification defines a set of signaling levels, timing relationships and topologies that support the enhanced performance capabilities of AGP3.0. The physical layer specification provides for full backward compatibility with 1.5 V AGP2.0.
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AGP3.0 Interface Specification Rev. 1.0 Both GC_DET#, and MB_DET# are of the asynchronous signal type. The GC_DET# signal is a static signal supplied from the graphics card to indicate to the motherboard and/or core-logic that the AGP3.0 signaling and protocol are supported. Likewise, the MB_DET# signal is a static signal supplied from the motherboard or core-logic to indicate to the graphics card and/or AGP3.0 Master that the AGP3.0 signaling and protocol are supported.
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AGP3.0 Interface Specification Rev. 1.0 relationship from that of AGP2.0 (e.g. the SBA bits are now SBA#, indicating that a logic 1 is signaled as a low voltage on the interconnect). Table 30: AGP3.
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AGP3.0 Interface Specification Rev. 1.0 Collectively these signals are referred to as AGP3.0 signals because they share this same signaling scheme. The remainder of this chapter is concerned primarily with this set of signals. / NOTE In many cases, AGP3.0 signals have been defined as logically inverted from those of the AGP2.0 Interface specification. This has been done to minimize power consumption, especially in the quiescent state of the interconnect. This is more fully described in Section 2.1.
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AGP3.0 Interface Specification Rev. 1.0 3.2.1 AGP3.0 Common Clock Transfer Mode Operation All timings for common clock signals are referenced to a single 66 MHz clock. This clock is required to be common between the two agents at each end of the AGP3.0 channel. This clock may or may not be synchronous to some other clock in the system (e.g. the FSB clock). If there is more than one AGP3.0 segment within the system, it must be assumed that different base clocks have been used by each of the segments.
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AGP3.0 Interface Specification Rev. 1.0 Inner Loop Receiver Transmitter data timing Outer Loop Data Timing data timing Control 66 MHz Clock Figure 3-3: Source Synchronous Mode Time Domain As previously indicated, the outer loops of both devices operate from a common clock, with all outer loop controls specified relative to this clock. The inner loop timings use additional source synchronous strobe timing signals employed to realize the high data transfer rates.
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AGP3.0 Interface Specification Rev. 1.0 defined in this specification -- logically inverted from that of AGP2.0 with different VOH and VOL characteristics, etc. 3.2.2.2 Transmit to Receive Inner Loop Transfer of source synchronous data between transmit and receive inner loop circuits is accomplished using a strobe pair (AD_STBF/AD_STBS) that is sent from the transmitter to the receiver. For AGP3.
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AGP3.0 Interface Specification Rev. 1.0 Common Clk (66 MHz) tRX_SU tRX_SU tRS8su Receive AD_STBS Receive AD_STBF Receive Data Data0 Data1 tRX_H Data2 Data3 Data4 Data5 Data6 Data7 tRX_H Figure 3-5: Receive Strobe/Data Timings for 8X Source Synchronous Timing 3.2.2.3 Receive Inner to Outer Loop: The most complex set of timings are those that address the receiver inner to outer loop relationships.
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AGP3.0 Interface Specification Rev. 1.0 Due to this uncertainty window as to when the first edge of AD_STBF will be sent, the earliest safe receiver transfer point from the inner to the outer loops occurs at the end of T2. The minimum specification scenario implies that a second set of AD_STBF/AD_STBS strobes occurs in T2, when a second set of eight DWords of data is being transferred.
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AGP3.0 Interface Specification Rev. 1.
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AGP3.0 Interface Specification Rev. 1.0 where TCYC is a single common clock period and TVAL, TFLT, TSU, and TSKEW are as defined in Table 31 below.
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AGP3.0 Interface Specification Rev. 1.0 • • • • • • • • ISI17 due to imperfect impedance matching resulting from tolerances on package, board trace, connector, driver and receiver impedances Rising/falling edge delay matching Vref uncertainty Core circuitry noise effects (i.e.
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AGP3.0 Interface Specification Rev. 1.0 The AGP3.0 Design Guide provides an example distribution of first and second order timing budget effects impacting signal skew. The previous discussion is directed at inner loop timings. Timing specifications between the inner and outer loops must also be closely managed. Specifically, the system must be designed to ensure that data sent in conjunction with T1 is available for capture, in the common (base) clock domain, at the end of T2.
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AGP3.0 Interface Specification Rev. 1.0 pull-up device against a standard load device of 50 Ω. The method of setting the driver pull-up to the proper resistance value is implementation specific and is not covered in this specification. VDDQ Vref R ON_P = Zpd (VDD/V OH - 1) V OH = 0.80V VOL = V SS = 0.00V T-line impedance = Z0 R ON_N = Zp d R TT = Z pd VSS Driving Device VSS Receiving Device Figure 3-9: Determination of Device RON Values 3.4.1.2 Vref Generation As opposed to AGP2.0, Vref for AGP3.
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AGP3.0 Interface Specification Rev. 1.0 VDDQ Vref R ON_P = Zpd (VDD/V OH - 1) V OH = 0.80V T-line impedance = Z0 R TT = Z pd VSS Driving Device Receiving Device Figure 3-10: Driving the Interface High 3.4.1.4 Driving the Interface to a Low Level The AGP3.0 interface has the same make-up in its default (or quiescent) state as when the driver is driving the interface low. In this case the pull-down of the driver is enabled while its pull-up is disabled (see Figure 3-11). Vref VOL = V SS = 0.
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AGP3.0 Interface Specification Rev. 1.0 Care must be taken to avoid coupling to any high frequency signals that might cause EMI radiation problems when a cable is attached. Associated power lines should be properly bypassed to decouple noise. INTA#, INTB#, and PME# are all 3.3 V open drain signals driven by the AGP Master, referenced to the VCC3.3 power supply. These interrupt and power management signals subsequently may be interfaced to +5 V PCI devices on the motherboard.
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AGP3.0 Interface Specification Rev. 1.0 3.5.2 Other Topologies It is possible to design a system with master and target devices both “down” on the motherboard, without an intervening connector. Also, custom systems with a connector other than the standard AGP connector can be built. Both of these cases can benefit from these specifications, however this specification is not meant to cover or constrain either of these configurations. 3.5.3 System Level Definitions 3.5.3.
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AGP3.0 Interface Specification Rev. 1.0 reference plane 1 Stripline Interconnect H’ trace S trace H Ground reference plane trace H S trace Microstrip Interconnect Ground reference plane Figure 3-12: Spacing to Height Definitions for Stripline and Microstrip Implementations 3.5.3.2 System (Common) Clock Skew The maximum allowable, total common clock skew is 1.0 ns.
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AGP3.0 Interface Specification Rev. 1.0 V_ih CLK (@Device #1) Vtest V_il T_skew T_skew T_skew V_ih CLK (@Device #2) V_il Vtest Figure 3-13: Clock Skew Diagram / NOTE For systems that employ SSC (spread spectrum clocking), the additional clock skew from the different tracking speeds of the component’s PLL must be accounted for in skew calculations. 3.5.3.3 External Pull-ups/Pull-downs AGP3.
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AGP3.0 Interface Specification Rev. 1.0 Table 33 Motherboard Interconnect Requirements1 Parameter AGP3.0-DT Min AGP3.0-WS Max Min Max 2.0 7.0 Units Notes inches 2 inches 2 Source Synchronous Signals Interconnect Length - Stripline Interconnect Length - Microstrip Interconnect Mismatch – strobe-tostrobe Interconnect Mismatch – strobe-todata Trace Characteristic Impedance (Stripline) Trace Characteristic Impedance (Microstrip) Trace Effective Impedance 2.0 6.
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AGP3.0 Interface Specification Rev. 1.0 6. Propagation delay must account for all contributors up to the connector pins. 7. Effective impedance incorporates all coupling effects including crosstalk as it is explained in section 3.5.3.1. 8. This represents the contribution to skew on the motherboard and includes all causes, not just interconnect. 9. Package information is added here for simple reference. Flip-chip packaging is highly recommended. For further details, consult section 3.
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AGP3.0 Interface Specification Rev. 1.0 / NOTES 1. All interconnects must be ground referenced. 2. Worst-case interconnect skews listed in this table are based on simulations that take into account realizable layout topologies and a wide range of interconnect. Trace lengths include pin-to-trace breakout and trace-to-connector fan-in/-out. 3. Add-in-Card may use stripline or microstrip routing. The routing must be strongly ground referenced. 4.
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AGP3.0 Interface Specification Rev. 1.0 3.5.6 Motherboard / Add-in Card Interoperability Interoperability is required by AGP3.0 implementations. A box with a ü symbol means the configuration is legal while a grayed out box indicates an illegal configuration and must be excluded either by electrical or mechanical means. Table 35 shows the matrix of compatible motherboard and add-in cards and their operating and signaling voltage. Table 35: Motherboard / Add-in Card Interoperability AGP2.
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AGP3.0 Interface Specification Rev. 1.0 buffer drive characteristics, input signal clamping, and board layout requirements. Note that VDDQ is fixed at 1.5 V for AGP2.0, Universal AGP3.0, and AGP3.0-Only topologies. In general, the higher transfer rate electrical interface and board requirements are backward compatible to the lower rates for a particular signaling level. The AGP3.
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AGP3.0 Interface Specification Rev. 1.0 Table 36: AGP Target Signal State During and After RESET Signal Name AGP3.0 AGP3.0 Signaling During Reset After Reset1 Signal Name AGP2.0 AGP 2.
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AGP3.0 Interface Specification Rev. 1.0 Table 37: AGP Master Signal State During and After RESET Signal Name AGP3.0 AGP3.0 Signaling During Reset After Reset Signal Name 1 AGP2.0 AGP 2.
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AGP3.0 Interface Specification Rev. 1.0 3.6 Component Level Electrical Specifications This section provides details of the electrical characteristics for the AGP3.0 interface. I/O buffer design technology to meet these requirements will not be addressed as it is beyond the scope of this specification. 3.6.1 DC Specs The parameters below list the DC requirements for the common clock and source synchronous modes of AGP3.0. Table 38: DC Specifications for AGP3.
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AGP3.0 Interface Specification Rev. 1.0 specified nominal value across the entire range between Vss and VOH (Refer to Table 45 for complete details). 5. The driver pull-up impedance must be adjusted to obtain an output swing within the VOH specification. More information on driver characteristics can be found in section 3.6.6.1. 3.6.2 AC Measurement and Test Conditions Because of the high-speed nature of the AGP3.
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AGP3.0 Interface Specification Rev. 1.0 Table 39: Measurement and Test Condition Parameters Symbol Measure Point Units Notes Vclk VREF V 1 Vtesti VREF V Test level for inputs Vtesto 0.5VOH V Test level for outputs Vth VREF + 0.200 V 2 Vtl VREF - 0.200 V 2 slew rate max 3.5 V/ns 3 slew rate min 2.0 V/ns 3 / NOTE 1. Vclk is a strobe signal in this example. 2. The input timing measurement test is done with at least 0.1 Volts of overdrive greater than Vil and Vih . 3.
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AGP3.0 Interface Specification Rev. 1.0 3.6.3 AC Timings AGP3.0 timings are specified through two sets of parameters, one set that defines the AGP3.0 common clock operation (for the outer loop control signals), and the second set that defines source synchronous operation. Table 40 and Table 41 provide a summary of the interface timings for 66 MHz and 533 MT/s AGP3.0 operation.
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AGP3.0 Interface Specification Rev. 1.0 Table 41: AGP3.0 AC Source-Synchronous Timing Parameters 8X Speed Symbol Parameter Min 4X Speed Max Min Max Units Notes / Comments Source Synchronous Transmitter1: TBIT_TIME/2 One half bit time 937.5 1875 ps TDvb Data valid before strobe 527.5 950 ps At the transmitter pads TDva Data valid after strobe 477.5 1150 ps At the transmitter pads TINTC_SUS Strobe-to-data skew on setup time caused by interconnect effects 0 442.
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AGP3.0 Interface Specification Rev. 1.0 / NOTE 1. Measured at pad into standard 50 Ω load to Vss. 2. Input waveform example for min/max slew rate at receiver pad.
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AGP3.0 Interface Specification Rev. 1.0 3.6.4 Signal Integrity Requirement for AGP3.0 The overshoot requirements are meant to protect the device from electrical overstress (EOS) and to minimize the effects from ISI on timing. The ringback limits are intended to prevent false signal detection and false strobes, and to insure sufficient input drive levels to guarantee proper input timing. On-die clamping and ESD diode effects are included.
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AGP3.0 Interface Specification Rev. 1.0 Figure 3-17: Signal Integrity Requirements VOH (steady) Keep Out Region VIH (min) VRB VIL (max) VRB VOL TDRIVE VREF (steady) 3.6.4.2.1 SPECIAL STROBE SI REQUIREMENTS As soon as a strobe transition crosses the DC VIL or VIH limits, the transition must continue monotonically through the VREF switch point to VRB overdrive beyond VREF, outside the shaded keep-out region of Figure 3-17. The strobe must remain outside the keep-out region for time TDRIVE.
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AGP3.0 Interface Specification Rev. 1.0 3.6.4.2.2 SPECIAL GAD SI REQUIREMENTS There are two cases for GAD signals: full transitions and glitches. In the first case, as soon as an Address or Data signal transitions across the DC VIL or VIH limits, the transition must continue monotonically through the VREF switch point to VRB overdrive beyond VREF, outside the shaded keep-out region of Figure 3-17. The GAD signals must remain outside the keep-out region for time TDRIVE.
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AGP3.0 Interface Specification Rev. 1.0 Table 42: Input/Output Signal Integrity Requirements Symbol VOSH_P VOSH_N VRB TDRIVE 1. 2. 3. 4. 5. 6. 7. 8. Parameter Output Slew Rate Input Slew Rate Positive overshoot above steady level Negative overshoot below steady level Ringback margin to Vref Input overdrive time Min 2 1 150 0.6 Max 3.5 3.5 350 -300 Units V/ns V/ns mV mV mV ns Notes 1,2,3 7 1,4,8 1,4,8 1,5 6 Output buffer measurements are made with a standard 50 Ω load to ground (see Table 39).
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AGP3.0 Interface Specification Rev. 1.0 6 nS (min) voltage test point V1 RSRC V I/O Buffer Evaluation Setup tRF V2 RTT 15nS (66 MHz) Figure 3-20: Open-circuit Voltage Table 43: Parameters for Maximum AC AGP3.0 Signaling Waveforms Symbol Parameter VIH Signaling Min RSRC tester source resistance V1 Positive-Going Overshoot V2 Negative-Going Overshoot -0.3 tRF Rise fall time 0.5 Units Max Ω 45 1.575 V V 1.
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AGP3.0 Interface Specification Rev. 1.0 3.6.6 Driver and Receiver Characteristics 3.6.6.1 AGP3.0 Driver Characteristics AGP3.0 is designed for point-to-point communication. The output driver must be able to deliver a voltage swing of 0.8 V (nominal) to the terminated receiver (through the interconnect), with known characteristic impedance Z0.
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AGP3.0 Interface Specification Rev. 1.0 / NOTE 1. The min current limit is relaxed above Vswing to accommodate a standard CMOS transistor saturation characteristic. Termination impedance tolerance above Vswing becomes less important for signal integrity purposes. 2. Equations A and B reflect a ± 10% tolerance over the entire set of pull-down and termination impedance, across the range from 0 Volts to Vswing.
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AGP3.0 Interface Specification Rev. 1.0 Pull-u p - V Swing Z Term Z Term IOUT V Swing Example Pull-up V-I Characteristic 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 V OUT (Volts) Figure 3-22: V/I Curve for AGP3.0 Transmitter Pull-up Table 45: Specifications for AGP3.
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AGP3.0 Interface Specification Rev. 1.0 3.6.6.2 Signal swing (V OH) Accuracy Signal timing characteristics and quality are highly dependent on the signal swing values observed at the receiver. In general, VOH represents the voltage attained at the receiver input as the signal settles. Designs are expected to maintain VOH at least above 750 mV at VDDQ = 1.5 volts, and preferably near the Vswing target value of 800 mV but below 850mV.
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AGP3.0 Interface Specification Rev. 1.0 3.6.6.5 Calibration of Driver Pull-up and Pull-down and Receiver Load To maintain proper receiver load impedance and the proper signal swing (VOH), the driver and receiver will need to be occasionally adjusted to account for changes in operating point. To support this activity, a calibration mechanism has been developed for the AGP3.0 interface. The framework to support this calibration mechanism (boot time requirements, calibration cycles, etc.
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AGP3.0 Interface Specification Rev. 1.0 Simulations have shown that a wirebond suffers from potential power delivery resonance effects. The cause for this is the LC circuit formed by the VDDQ/VSS bond wires and the on-die capacitance of the driver. A certain amount of on-die capacitance is necessary since it decreases signal timing push-out caused by simultaneous switching outputs (SSO).
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AGP3.0 Interface Specification Rev. 1.0 3.7.2 Pin-out/Ball-out Requirements All AGP3.0 signal pins must be located to facilitate meeting the card connector with a minimum of package/board vias or trace crossovers to minimize overall trace lengths, crosstalk, mismatched number of layer changes, and trace length mismatches within a given signal group.
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AGP3.0 Interface Specification Rev. 1.0 Table 47: Add-in Card Power Supply Limits Symbol Vddq1.5 VCC3.3 3.3VAUX VCC5 VCC12 Parameter I/O Supply Voltage 3.3 V Power Supply 3.3 V Auxiliary Supply 5 V Power Supply 12 V Power Supply Condition IMAX = 2.0 A IMAX = 6.0 A IMAX = 0.375 A IMAX = 2.0 A IMAX = 1.0 A Min 1.425 3.15 3.15 4.75 11.4 Max 1.575 3.45 3.45 5.25 12.6 Units V V V V V Notes 1, 2 / NOTE 1. AGP3.0 requires no more than 1.0 amp average VDDQ current through the connector.
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AGP3.0 Interface Specification Rev. 1.0 4 Appendix A: Workstation Enhancements The following workstation specific changes and enhancements are described in this Appendix. The remaining workstation specific changes are described in Appendix B. 1. Isochronous Operation 2. Fast Write Flow Control Change 3. Synchronization Schemes 4. Fan-Out Bridge Requirements 4.1 Isochronous Mode Operation Traditional AGP devices can demand up to the maximum bandwidth available over the AGP ports.
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AGP3.0 Interface Specification Rev. 1.0 4.1.1 4x Speed and Isochronous Support Isochronous operation is not supported when the 4x speed of operation is selected even when operating in AGP3.0 signaling mode. The core-logic hardware must ensure that the isochronous operation is disabled when this speed is selected and the Isoch_Support bit in AGPSTAT [17] is cleared. 4.1.2 Contract Parameters Isochronous parameters are defined in this part of the AGP3.0 specification.
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AGP3.0 Interface Specification Rev. 1.0 Table 48: Transaction Size Vs Payload Size Type Read Read Read Read Write Write Write Write Payload Size (ISOCH_Y) 32Bytes 64Bytes 128Bytes 256Bytes 32Bytes 64Bytes 128Bytes 256Bytes Transaction Size 32Bytes 64Bytes 128Bytes 256Bytes 32Bytes 64Bytes 64Bytes 64Bytes # of Consecutive Requests/Payload 1 1 1 1 1 1 2 4 4.1.2.
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AGP3.0 Interface Specification Rev. 1.0 Chipsets may guarantee any value for the maximum latency between zero and five isochronous periods (Lmax = 5 microseconds). The specific value supported by the core-logic is indicated in a PCI configuration register (NISTAT.isoch_L). Figure 4-1 shows how data transfers may occur in a system where the core-logic latency is Lcore-logic = 2.
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AGP3.0 Interface Specification Rev. 1.0 The number of isochronous streams which can be simultaneously serviced is a function of the core logic implementation and therefore not specified here. Designers must refer to the targeted core logic documentation for any implementation specific restrictions that must be observed. 4.1.3 Transaction Ordering There is no ordering between the completion of isochronous memory transactions and the completion of any other memory traffic in the system.
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AGP3.0 Interface Specification Rev. 1.0 data, then write an isochronous synchronization flag in system memory using a fenced write transaction. Once the flag becomes visible, the data is guaranteed to be visible. Isochronous data may be written with fenced or unfenced write transactions; however, completion flags must be written with a fenced write transaction. Synchronizing the processor with an AGP3.0 Isoch. Write could proceed as follows: AGP3.
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AGP3.0 Interface Specification Rev. 1.0 4.1.6 Isochronous Request/Status Encoding The AGP3.0 specification includes four new isochronous transaction codes in addition to those required by the AGP Interface Specification V2.0. The AGP3.0 Master device must place one of these four new codes on the “CCCC” wires to initiate an isochronous transaction. The new isochronous transaction codes are shown in Table 50. Highlighting implies a change from AGP. Table 50: AGP3.0 Interconnect Requests CCCC AGP3.
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AGP3.0 Interface Specification Rev. 1.0 1010 Flush 1011 Reserved 1100 Fence (For both read and writes) 1101 Reserved (used for PCI Frame based Dual Address Cycle) 1110 ISOCH Align 1111 Reserved Similar to a Read. This request drives all low priority write accesses ahead of it to the point that all the results are fully visible to all other system agents, and then returns a single Quad-word of random data as an indication of its completion.
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AGP3.0 Interface Specification Rev. 1.0 4.1.7 Identifying Isochronous Data The AGP3.0 core-logic specifies the type of isochronous data to be transmitted over the AGP3.0 Port using the two status codes that were previously reserved. The new status codes are shown below. Highlighting implies a change from AGP2.0.
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AGP3.0 Interface Specification Rev. 1.0 Target AGP8X port AGP8X fanout Bridge AGP/AGP8X port Device AGP/AGP8X port Device Figure 4-3: AGP3.0 Fanout Bridge Connections 4.1.10 Setting T, L, Y, N for AGP3.0 Core-logic and AGP3.0 Devices Several isochronous parameters must be set to compatible values on the AGP3.0 core-logic (target) and the AGP3.
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AGP3.0 Interface Specification Rev. 1.0 An AGP3.0 Master’s request queue depth must be sufficient to cover the AGP3.0 core-logic’s isochronous pipeline latency (L). Plus, any additional isochronous latency contributed by an optional Fan-out Bridge, according to the following expression: Qisoch = BW * L Y Where BW/Y = N which is the number of transactions (read and write) per time period T (1 microsecond) of payload size Y. Request queue size for an AGP3.
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AGP3.0 Interface Specification Rev. 1.0 4.1.11 Time Keeping An AGP3.0 device must be aware of the isochronous time period (T) to ensure that it does not exceed the agreed-upon maximum number of isochronous transaction requests. AGP3.0 bridges must also be aware of the isochronous period for the same reason. Timekeeping is optional for AGP3.0 core-logics. AGP3.0 Master devices must synchronize their isochronous periods to that of the bridge or core-logic by issuing a time alignment transaction.
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AGP3.0 Interface Specification Rev. 1.0 4.1.11.1 Isoch Align Transaction An Isoch Align transaction is similar to a Isoch Read transaction except that it has a special meaning to the Core-Logic. If the Core-Logic supports time-keeping, it will return an offset value to allow the isoch device to align its isochronous period to that of the core-logic. The value of this offset is returned in the lower 8 bits of a 32 bit word. The remaining bits in the word should be ignored.
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AGP3.0 Interface Specification Rev. 1.0 Master is allowed to disconnect a stalled transaction with or without accepting any data. The target is required to resume where the disconnected transaction left off. Disconnecting a stalled Fast Write ensures that a pending isochronous transfer can complete in a timely manner. 4.3 Synchronization Models This section presents a discussion of the synchronization models used for interchange of data between different agents in the platform.
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AGP3.0 Interface Specification Rev. 1.0 Since the second phase is eventually completed, the completion of the first phase (which decides on the data to be returned) is more important. 4.3.3 Write Completion Since “Writes” from any agent (processor, or AGP3.0 for example) device may be posted, this data could potentially sit in write queues indefinitely. This is especially true if there are dependencies on subsequent events (such as more writes) to flush these queues. The AGP3.
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AGP3.0 Interface Specification Rev. 1.0 4.3.5 Synchronization Scheme: Case 2 AGP Data to Processor The following scheme ensures correct operation. Table 53: The Synchronization Sequence of Data from AGP to the Processor AGP3.0 Device Actions Core-logic Actions Processor Actions Writes to memory (Could be low priority Async. or Isoch). Executes a Fence for Asynchronous Writes (skip step for Isoch Writes). Writes flag in system memory to indicate completion.
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AGP3.0 Interface Specification Rev. 1.0 Since the Fan-out Bridge is transparent, it implies that the AGP Devices are logically on the primary segment and are indistinguishable to software from multiple devices on a traditional multi-drop bus. • • • The Fan-out Bridge cannot have an impact on the AGP flow control protocol. This implies that it must supply adequate buffering to manage the flow control on each side of the bridge independently.
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AGP3.0 Interface Specification Rev. 1.0 5 Appendix B: Workstation Programming Model 5.
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AGP3.0 Interface Specification Rev. 1.0 5.2 Port and Device Definitions 1. AGP3.0 Port: The AGP3.0 Port is the target of requests from the AGP3.0 (Master) devices. It is provided by the core-logic implementation. AGP3.0 provides for multiple AGP3.0 Ports with multiple devices on each port. 2. Processor Port: The processor port is not required when supporting an AGP3.0 interface, but is typically supported by a Host Bus Bridge.
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AGP3.0 Interface Specification Rev. 1.0 5.2.2 AGP3.0 Port Requirements 1. The core-logic locates all AGP3.0 configuration registers within a single function of the AGP3.0 Port device; this allows System Software to easily support AGP3.0. The core-logic ensures that the configuration of all AGP3.0 Port resources, AGP3.0 aperture, and GART reside within this single function space. The registers are described in more detail later in this section. 2. The location of AGP3.
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AGP3.0 Interface Specification Rev. 1.0 5.3 AGP Graphics Aperture In an AGP3.0 system, driver software and an AGP3.0 device can share large amounts of data through buffers placed in system RAM. A large buffer requires many host processor virtual pages; although host system software ensures that these pages appear contiguous to host software (virtually contiguous). It is often difficult for system software to map these virtual pages to contiguous physical pages in system memory (physically contiguous).
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AGP3.0 Interface Specification Rev. 1.0 An AGP3.0 target (core-logic) may implement a number of Graphics Translation Look-aside Buffers (GTLB) to speed-up translation of AGP3.0 aperture page addresses to system memory locations. 5.3.1 AGP Aperture Page Size The core-logic implementation is configured by system software to support one, common AGP aperture page size for all pages in the AGP aperture. The core-logic includes a mechanism that allows system software to select that common AGP3.
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AGP3.0 Interface Specification Rev. 1.0 uses the GART for translation. 10. The operation of the AGP Port and AGP Master accesses to system memory function correctly regardless of whether host translation is present in the core-logic. 11. It is implementation-dependent whether the core-logic translates accesses directed to the AGP aperture by any system component NOT on the AGP Port – including PCI devices on other Buses. Software should not rely on this capability. 12.
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AGP3.0 Interface Specification Rev. 1.0 Table 55: Bit Positions Bit Position Field Definition 0 Valid When 1, the GART entry is a valid translation. When 0, the GART entry is invalid and accessing the entry for translation causes an implementation specific error condition.. 1 Coh This bit in combination with AGPSTAT.ITA_COH controls coherency support for accesses that use this GART entry. See section 5.4 for details. 3:2 Rsv Reserved for future use by the AGP3.0 specification.
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AGP3.0 Interface Specification Rev. 1.0 a) It sets an implementation specific error bit and optionally records the invalid GART entry address in an implementation specific register. These remain latched until explicitly cleared by software or on Power-On-Reset. b) Core-logic causes a processor-specific action that is platform dependent. c) If the transaction is a read of the AGP aperture, core-logic may either cancel the request or complete the request by returning UNDEFINED data.
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AGP3.0 Interface Specification Rev. 1.0 5.4 Coherency Requirements When the AGP target makes an access from an AGP Master coherent, the target ensures that: • • A read request receives the most current value of the datum from among all host processor caches, memory, and other coherent caching agents in the system; A write request’s value becomes the most current value of the datum in the system and is made visible to all host processor caches, memory, and other coherent caching agents in the system.
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AGP3.0 Interface Specification Rev. 1.0 5.4.1 Coherency of Host Processor Accesses The coherency mechanisms described in the AGP3.0 specification do not control nor influence the coherency of any host processor access to any region of physical memory, including the Graphics AGP aperture. Thus, the coherency of a host processor access to a graphics AGP aperture page would ignore the value of the page’s gart_entry.coh bit, and all other such mechanisms described above.
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AGP3.0 Interface Specification Rev. 1.0 Capabilities mechanism as described in the PCI Local Bus Specification. The New Capabilities structure is implemented as a linked list of registers containing information for each function supported by the device. AGP status and Command registers are included in the linked list. The structure for the AGP specific ID and structure is illustrated in Figure 5-3.
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AGP3.0 Interface Specification Rev. 1.0 These registers are located in AGP configuration space of the core-logic (also called AGP target) and AGP Device (also called AGP Master). For the core-logic, the AGP configuration space could be entirely in a Host-to-PCI Bridge function and/or a PCI-to-PCI Bridge function.
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AGP3.0 Interface Specification Rev. 1.0 The Major and Minor Revision IDs in the NCAPID register are used to inform software of the register set being implemented. Table 58 shows this relationship. Table 58: Major/Minor Revisions Major Revision 2h 3h or greater 3h or greater 3h or greater Minor Revision Don’t Care 0h-4h 5h-9h Ah-Fh Register Set Support AGP2.0 Register Support AGP3.0 Core Specification Register Support AGP3.0 Appendix Specification Register Support Reserved for future use 5.
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AGP3.0 Interface Specification Rev. 1.0 D’xxxx -- Power-on-Default is xxxx Hardwired-Value doesn’t need Power-on-default 5.8 Required Master and Target Registers 5.8.1 PCISTS: PCI STATUS REGISTER Offset: 06h Size: 2 bytes Table 61: Status Register Bits Access Field Description 15:5 4 See the PCI Local Bus Specification. R-IW CAP_LIST If the CAP_LIST bit is set, the device’s configuration space implements a list of capabilities The capability pointer is located at 34h.
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AGP3.0 Interface Specification Rev. 1.0 5.8.3 NCAPID: AGP IDENTIFIER REGISTER Offset: CAPPTR Size: 4 bytes Table 63: Identifier Table Bits Access Field Description 31:24 RZ-IW Reserved Always returns 0 on read; write operations have no effect. 23:20 R-IWD’0011 MAJOR Major revision number of AGP3.0 specification this device conforms to. A Value of 3 or greater Indicates AGP3.0. 19:16 R-IWD’0101 MINOR Minor revision number of AGP3.0 interface specification to which this device conforms.
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AGP3.0 Interface Specification Rev. 1.0 5.8.4 AGPSTAT: AGP STATUS REGISTER Offset: CAPPTR + 04h Size: 4 bytes Table 64: Status Register Bits Access Field Description 31:24 MST: R1-IW TGT: R-IW-Dx RQ TARGET ONLY: The RQ field contains the maximum number of AGP3.0 command requests (both asynchronous and isochronous) that can be enqueued to the target. “0” means a depth of 1 entry, while 0xFF means a depth of 256 entries.
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AGP3.0 Interface Specification Rev. 1.0 Bits Access Field Description 6 MST: RZ-IW TGT: R-IW-Dx htrans# TARGET ONLY: When ‘0’, Core-logic can translate host processor accesses through the AGP aperture. NOTE: Core-logic translation of host processor accesses is a platform specific feature and is solely used for the purpose of supporting legacy OS. Drivers written to use this feature may not port to platforms that do not have legacy support requirements.
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AGP3.0 Interface Specification Rev. 1.0 5.8.5 AGPCMD: AGP COMMAND REGISTER Offset: CAPPTR + 08h Size: 4 bytes Table 65: Command Register Bits Access 31:24 MST: R-W-D’0 TGT: RZ-IW Field PRQ Description Master: The PRQ field must be programmed with the maximum number of AGP command requests (both asynchronous and isochronous) that the master i s allowed to “enqueue” in the target. “0” means a depth of one entry, while FFh means a depth of 256 entries.
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AGP3.0 Interface Specification Rev. 1.0 Bits Access Field Description initiate AGP operations. When cleared, the master cannot initiate AGP operations. Target: Setting the AGP_ENABLE bit allows the target to accept AGP operations. When cleared, the target ignores incoming AGP operations. Notes: 1. The target must be completely configured and enabled before the master is programmed. 2.
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AGP3.0 Interface Specification Rev. 1.0 Bits 2:0 Access R-W-D’000 Field DRATE Description Data Rate Enable (DRATE) - The setting of these bits determines the data transfer rate. One (and only one) bit in this field must be set to indicate the desired data transfer rate. The same bit must be set on both master and target. The encoding below assumes AGP3.
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AGP3.0 Interface Specification Rev. 1.0 5.8.6 NISTAT: AGP ISOCHRONOUS STATUS REGISTER This register is accessible in the Target only if the Target’s AGPSTAT.isoch_support bit is set. Similarly, the register is accessible in the Master only if the Master’s AGPSTAT.isoch_support bit is set. When the isoch_support bit is not set, reads to this register will return undefined data and writes will have no effect.
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AGP3.0 Interface Specification Rev. 1.0 Bits Access Field Description 3124 RZ-IW Reserved Reserved. Reads return zeros; writes are ignored 5:3 MST: RWD101’b TGT: R-IWDx ISOCH_L Target: Maximum isochronous data transfer latency in units of isochronous periods (1 us). Allowable values are 1 to 5.
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AGP3.0 Interface Specification Rev. 1.0 5.8.7 NICMD: AGP ISOCHRONOUS COMMAND REGISTER This register is accessible in the Target only if the Target’s AGPSTAT.isoch_support bit is set. Similarly, the register is accessible in the Master only if the Master’s AGPSTAT.isoch_support bit is set. When the isoch_support bit is not set, reads to this register will return undefined data and writes will have no effect.
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AGP3.0 Interface Specification Rev. 1.0 Bits 5:0 Access RZ-IW Field Reserved Description Reserved The calculation of NICMD.PISOCH_Y, NICMD.PISOCH_N, and NICMD.PRQ are very dependent upon fields in AGPSTAT and NISTAT. Refer to Section 4.1.10 for possible methods in calculating these fields.
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AGP3.0 Interface Specification Rev. 1.0 5.9 Required Target Registers 5.9.1 APBASELO: AGP APERTURE BASE LOW ADDRESS REGISTER Offset: 10h Size: 4 bytes Table 68: Aperture Base Low Address Register Bits 31:22 Access R-W-D’0 Field AddressLo Description Address[31:22] of the AGP3.0 Aperture Address. Writes to APBASELOW will be dictated by the programmed value in Apsize. APSIZE[11:8] controls APBASELOW[31:28] while APSIZE[5:0] controls APBASELOW[27:22].
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AGP3.0 Interface Specification Rev. 1.0 Bits 0 Access RZ-IW Field Description Memory Hardwired to zero to indicate that the Graphics AGP3.0 aperture must reside in “Memory” space – as defined by the PCI Local Bus Specification. 5.9.2 APBASEHI: AGP APERTURE BASE ADDRESS HIGH REGISTER This register is only available when AGPSTAT.over4G bit is set. . When the AGPSTAT.over4G bit is not set, reads to this register will return undefined data and writes will have no effect.
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AGP3.0 Interface Specification Rev. 1.0 5.9.3 AGPCTRL: AGP CONTROL REGISTER Offset: CAPPTR + 10h Size: 4 bytes Table 70: Control Register Bits Access Field Description 31:24 RZ-MW Reserved Reserved For Future AGP3.0 Architectural Core-logic Features 23:16 R-MW-Dx Reserved Reserved For Implementation-Specific Core-logic Features 15:10 RZ-MW Reserved Reserved For Future AGP3.
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AGP3.0 Interface Specification Rev. 1.0 5.9.
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AGP3.0 Interface Specification Rev. 1.0 Bits Access Field Description “1s” for the APSIZE encoding for its maximum aperture size. For e.g. if core logic supports 256MB max, it must hardwire APSIZE[11:8] to ‘1’. Writes to these bits will have no effect. • Min Aperture Size: If this is different from the table above, the core logic must hardwire the “0s” in the encoding for its min aperture size. For e.g. if min supported size is 16MB, APSIZE[1,0] must be hardwired to ‘0. Write will have no effect.
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AGP3.0 Interface Specification Rev. 1.0 5.9.6 GARTLO: AGP GART POINTER Offset: CAPPTR + 18h Size: 4 bytes Table 73: GART Pointer Bits Access Field Description 31:12 RW-D’0 baselo Bits[31:12] of the start of the Graphics AGP aperture Remapping Table (GART). As a minimum the GART must be aligned on a 4KB boundary 11:4 RZ-IW Reserved Reserved 3:0 RZ-IW Reserved Reserved 5.9.
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AGP3.0 Interface Specification Rev. 1.0 6 Appendix C: Glossary of Terms Term Common Clock Transfer Definition A transfer across an interface between two agents that is synchronized to a clock that is common to both and is matched in phase and frequency. Core-logic The core-logic that has the host platform’s AGP3.0 bridge. Motherboard This is a general term referring to the PC board that includes the components of the Corelogic and the AGP connector.