Intel® E7520 Memory Controller Hub (MCH) Specification Update July 2009 Notice: The Intel® E7520 MCH may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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Contents Revision History ................................................................................................................. 4 Preface ............................................................................................................................... 5 Summary Table of Changes ............................................................................................... 6 Identification Information ..................................................................................
Revision History Revision History Version -001 -002 Description Date • Initial publication. June 2004 • Added C4 Stepping information. November 2004 • Added errata 30-32. 4 -003 • Added Specification Clarification 1.
Preface This document is an update to the memory interface specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and document errata and specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the this update document and are no longer published in other documents.
Summary Table of Changes Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the E7520 MCH. Intel may fix some errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations: Codes Used in Summary Table X: Errata exists in the stepping indicated.
Summary Table of Changes Errata Stepping No.
Summary Table of Changes Specification Changes Number SPECIFICATION CHANGES None for this revision of the Specification Update Specification Clarifications Number 1 SPECIFICATION CLARIFICATIONS Clarification to Section 4.4.
Identification Information Identification Information Component Identification via Programming Interface The Intel® E7520 MCH can be identified by the following register contents: MCH Version Stepping Vendor ID1 Device ID2 Revision Number3 E7520 C-1 8086h 3590h 09h E7520 C-2 8086h 3590h 0Ah E7520 C-4 8086h 3590h 0Ch NOTES: 1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00 - 01h in the PCI bus 0, device 0, function 0 configuration space. 2.
Errata Errata 1. DMA channel source address checking error Problem: In the DMA controller memory mapped registers, bit 6 of the DCRs (Descriptor Control Registers Memory Mapped I/O Address Offset 2Ch-2Fh, 6Ch-6Fh, 0ACh-A7h, 0ECh-EFh) for channels 0-3 should be RO, but is implemented as RW. Implication: The DMA controller does not implement error checking for this case if this bit is set to “1”. Workaround: Do not write a ‘1’ to bit 6 of the DCRx for channels 0-3.
Errata 5. PCI Express* add-in card presence detect state misreported Problem: PCI Express ports that are configured as non-hot plug capable incorrectly assert the add-in card Presence Detect State in the PCI Express Slot Status Register (EXP_SLTSTS Device 2-7, Function 0, Offset 7E-7Fh bit 6) regardless of the presence of an add-in card. Implication: Software may interpret the presence of an add-in card when none exists.
Errata 9. PCI Express link training failures on hot reset Problem: When issuing a hot reset via the bridge control register (BCTRL, Bus 0, Device 2-7, Function 0, Offset 3Eh bit 6, 1b) secondary bus reset bit to a PCI Express slot, the link may fall back degraded to a lower link width. Implication: The link may degrade in width or fail to train all together after a hot reset. Workaround: Implement a software algorithm that issues a Secondary Bus Reset upon a link training failure for 2 ms.
Errata Workaround: Upon initial training and after each retrain or secondary bus reset, clear the correctable error detected bit of the PCI Express Device Status register (EXP_DEVSTS, Device 2-7, Function 0, Offset 6E-6Fh bit 0, 1b) and the receiver error status bit of the PCI Express Correctable Error Status register (EXP_CORERRSTS, Device 2-7, Function 0, Offset 110-113h bit 0, 1b).
Errata 17. HiLoCS bit not readable in memory error address registers In memory mirror mode, the Error Address registers utilize bit 0 to signal if the error occurred on the primary or mirror copy. In the MCH, these bits are not accessible via software and will always return 0b if read.
Errata 20. SEC errors may be reported on opposite channel’s error registers in memory mirroring mode Problem: In memory mirroring mode the MCH may report SEC errors on opposite channels depending on the state of SA15 and the DDRCSR FSM Mirror State Transition Qualifier (Device 0, Function 0, Offset 9A-9Bh bits 11:10). Channel A SEC errors may be reported in Channel B error registers and vice versa.
Errata 23.
Errata Workaround: Intel recommends an algorithm that will issue an Secondary Bus Reset upon a link training failure for 2ms. The algorithm should support at least three iterations of Secondary Bus Resets. Status: For the steppings effected, see the Summary Table of Changes. 26. SKP ordered set may not be sent within required interval Problem: During Link Recovery on a PCI Express port, the MCH may fail to transmit a SKP ordered set within the required time interval as defined in the PCI Express 1.
Errata 29. Transposed interrupt messages across Hub Interface Problem: In cases where virtual wire interrupt messages (Assert/Deassert-INT[A, B, C, D]) received on PCI Express are spuriously short (the deassert message is received before the assert message can be forwarded by the MCH to the ICH), the MCH may infrequently transpose the interrupt assert and deassert messages across the Hub Interface.
Errata Workaround: A mux can be incorporated into the SMBus to disconnect the MCH when the platform goes into the S5 state. Status: For the steppings effected, see the Summary Table of Changes. 32.
Errata 34. Possible loss of Hot-swap Power Fault Event in dual PCI Express Hot-swap port configurations Problem: During boot, as part of normal PCI enumeration, the external hot-swap expander device on the PCI Express hot-swap ports must be configured. This PCI enumeration proceeds on a per device basis, during which an expander input change on the second port might get lost.
Specification Changes Specification Changes There are no Specification Changes in this revision of the Specification Update.
Specification Clarifications Specification Clarifications 1. Clarification to Section 4.4.1, “Memory Remapping”, in the EDS Section 4.4.1 currently reads as follows: 4.4.1 Memory Remapping An incoming address (referred to as a logical address) is checked to see if it falls in the memory remap window. The bottom of the remap window is defined by the value in the REMAPBASE register. The top of the remap window is defined by the value in the REMAPLIMIT register.
Documentation Changes Documentation Changes There are no Documentation Changes in this revision of the Specification Update. 1. Interupt Redirection The bit definition for the hardware interrupt redirection has been added. The following changes will be reflected in the next release of the Datasheet.
