Intel® Xeon® Processor E7-8800/ 4800/2800 Product Families Specification Update November 2014 Reference Number: 325122-021
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Contents Revision History................................................................................................................................. 5 Preface............................................................................................................................................... 6 Summary Tables of Changes ............................................................................................................. 8 Identification Information......................................
November 2014 Intel® Xeon® Processor E7-8800/4800/2800 Product Families Specifiication Update
Revision History Revision Description Date -001 Public Release April 2011 -002 Added BP33 errata April 2011 -003 Added BP34, BP35 errata May 2011 -004 Added erratum BP36 July 2011 -005 Added erratum BP37 August 2011 -006 Added erratum BP38 September 2011 -007 Added erratum BP39 October 2011 -008 Added erratum AS2.
Preface This document is an update to the specifications contained in the “Affected Documents” table below. This document is a compilation of device and documentation errata, specification clarifications, and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in “Nomenclature” are consolidated into the specification update and are no longer published in other documents.
Nomenclature Errata are design defects or errors. These may cause the Intel® Xeon® Processor E7-8800/4800/2800 Product Families behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, for example, core speed, L2 cache size, package type, etc.
Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel® Xeon® Processor E7-8800/4800/2800 Product Families. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.
Table 1. Errata Table (Sheet 1 of 2) Stepping Number Status Description A-2 BP1. X No Fix Intel® Interconnect BIST (Intel® IBIST) Does Not Work in Intel® QuickPath Interconnect (Intel® QPI) in Slow Mode BP2. X No Fix Retraining Parameter Negotiation is Not Implemented for Intel® QPI BP3. X No Fix Intel® IBIST Slave Ignores Loop Count Values Sent by Master on Intel® QPI BP4. X No Fix System Hangs when Skipping Stop Req2 and Start Req1 Messages in Quiesce/Lock Sequence BP5.
Table 1. Errata Table (Sheet 2 of 2) Stepping Number Status Description A-2 BP33. X No Fix Package C3/C6 with Memory Self-refresh Enabled May Cause False Error Logging BP34. X No Fix Performance Monitor WOKEN Event May Under Count BP35. X No Fix PECI Command Average Temperature Read does not report correct Temperature BP36. X No Fix Intel® QPI Initialization May Cause a CATERR During Power-on Reset BP37.
Specification Clarifications Number SC1. SPECIFICATION CLARIFICATIONS Package C3/C6 Memory Self-Refresh Error Handling Document Changes Number DC1.
Identification Information Component Identification via Programming Interface The Intel® Xeon® Processor E7-8800/4800/2800 Product Families stepping can be identified by the following register contents: Reserved Extended Family1 Extended Model2 Reserved Processor Type3 Family Code4 Model Number5 Stepping ID6 31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0 00000000b 0010b 00b 0110 1111b 0000b Notes: 1.
Component Marking Information Intel® Xeon® Processor E7-8800/4800/2800 Product Families can be identified by the following component markings: Figure 1. Processor Top-Side Marking (Example) Legend: GRP1LINE1: GRP1LINE2: GRP1LINE3: GRP1LINE4: GRP1LINE5: Mark Text (Production Mark): INTEL{M}{C}'YY PROC# Intel® Xeon® SSPEC XXXXX SPEED/CACHE/INTC {FPO} {e4} YY = Year PROC# = Processor Number xxxxx = Country of Origin INTC = Interconnect Speed (Intel® QPI) Factory Information Table 2.
Mixing Processor Within MP Platforms Intel supports multiprocessor (MP) configurations consisting of processors: 1. From the same power optimization segment. 2. That support the same maximum Intel® QuickPath Interconnect (Intel® QPI) and DDR3 memory speeds. 3. That share symmetry across physical packages with respect to the number of logical processors per package, number of cores per package, number of Intel® QPI interfaces, and cache topology. 4.
Intel® Trusted Execution Technology Authenticated Control Modules Platforms supporting Intel® Trusted Execution Technology (Intel® TXT) must ship with authenticated control modules, software binaries used to establish a root of trust. BIOS launches the BIOS ACM (authenticated control module) to establish a static root of trust at power-on. The measured launch environment launches the SINIT ACM to establish a dynamic root of trust at MLE (Measured Launch Event) launch. Table 3. Table 4.
Intel® Xeon® Processor E7-8800/ 4800/2800 Product Families BIOS ACM Errata Summary Table 5. Intel® Xeon® Processor E7-8800/4800/2800 Product Families BIOS ACM Errata Table Release Number Status 1.0 AC1 16 November 2014 X Description 1.
Intel® Xeon® Processor E7-8800/ 4800/2800 Product Families SINIT ACM Errata Summary Table 6. Intel Xeon Processor E7-8800/4800/2800 Product Families SINIT ACM Errata Table Release Number Status 1.0 1.1 AS1 X X AS2 X Description No Fix TXT.ERRORCODE TPM Command Return Code And Launch Control Policy List Index And Minor Code Are Not Reported Correctly.
Errata BP1. Intel® Interconnect BIST (Intel® IBIST) Does Not Work in Intel® QuickPath Interconnect (Intel® QPI) in Slow Mode Problem: The Intel IBIST (Interconnect Built-in Self Test) does not work in the Intel® QuickPath Interconnect (Intel® QPI) slow mode and only works at operational speed. Implication: The Intel IBIST does not work in Intel® QPI slow mode. Workaround: Do not run the Intel IBIST in slow mode. Status: For the steppings affected, see the Summary Tables of Changes. BP2.
BP5. Integrated Memory Controller Signals Spurious CMCI when Home Agent Failover Count Saturation Occurs Problem: When home agent failover count saturation occurs, the memory controller signals a spurious CMCI (Corrected Machine Check Interrupt) without logging an error. Failover count saturation is not an error and a CMCI should not be issued. Implication: Due to this erratum, software receives a CMCI with no error logged. Workaround: None identified.
BP9. Memory Controller Patrol Scrub Ceases to Function with CRC Errors and the IMT31 Reclaim Feature Enabled Problem: The processor does not fully implement the protocol in the Memory Controller-Home Agent for sharing the IMT31 (In-flight Memory Table) entry resulting in a patrol scrub deadlock. This issue can occur whenever the Error Flow State is invoked in response to CRC errors or hardware injected periodic ZQCAL (ZQ Calibration).
Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. BP14. Mirror Slave May Deliver Incorrect Data when a Read to the Mirror Master Completes Before the Write-back from the IOH Problem: A read from the mirror master may complete before the write-back from the IOH completes.
Implication: Due to this erratum, an unexpected Page Fault may occur during stress testing when the processor core transitions from C6 to C0. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. BP18.
rollover. When generated, the error signal is sent to the system configuration controller where it is processed into a system management interrupt (SMI). Under specific conditions, a RAS recoverable error signal is generated and logged in a physical layer port, but the interrupt is not generated. More specifically, the error signal is lost on the way from the port to the system configuration controller. The problem arises when the error signal passes through a port that has been disabled.
BP26. Task Switch to a TSS With an Inaccessible LDTR Descriptor May Cause Unexpected Faults Problem: A task switch may load the LDTR (Local Descriptor Table Register) with an incorrect segment descriptor if the LDT (Local Descriptor Table) segment selector in the new TSS specifies an inaccessible location in the GDT (Global Descriptor Table). Implication: Future accesses to the LDT may result in unpredictable system behavior.
which BIOS code runs on, may have one thread take the power event and the other thread not take the power event, resulting in a system hang. Implication: As a result of this erratum, the system may hang after BIOS initiates a system quiesce flow. Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. BP31.
Implication: Performance Monitoring Event WOKEN will under count the number of cores woken up from core C-states due to Trusted Execution Technology transaction. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BP35.
BP39. An Unexpected Page Fault or EPT Violation May Occur After Another Logical Processor Creates a Valid Translation for a Page Problem: An unexpected page fault (#PF) or EPT violation may occur for a page under the following conditions: • The paging structures initially specify no valid translation for the page. • Software on one logical processor modifies the paging structures so that there is a valid translation for the page (e.g.
restart an I/O instruction if the platform has not been configured to generate a synchronous SMI for the recorded I/O port address. Status: For the steppings affected, see the Summary Tables of Changes. BP42. Writing an Illegal Vector to the IA32_X2APIC_SELF_IPI MSR Will Hang the Processor Problem: Writing an illegal vector (0 to 15) to the IA32_X2APIC_SELF_IPI MSR while the local APIC is in x2APIC mode will cause the processor to hang. Implication: When this erratum occurs, the processor will hang.
Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BP46. A Combination of Data Accesses That Are Split Across Cacheline Boundaries May Lead to a Processor Hang Problem: Under certain complex micro-architectural conditions, closely spaced data accesses that are split across cacheline boundaries may lead to a processor hang. Implication: Due to this erratum, the processor may hang.
BP51. CR0.CD Is Ignored in VMX Operation Problem: If CR0.CD=1, the MTRRs and PAT should be ignored and the UC memory type should be used for all memory accesses. Due to this erratum, a logical processor in VMX operation will operate as if CR0.CD=0 even if that bit is set to 1. Implication: Algorithms that rely on cache disabling may not function properly in VMX operation. Workaround: Algorithms that rely on cache disabling should not be executed in VMX root operation.
Workaround: Software that has executed in 64-bit mode should reload CR3 with a 32-bit value before returning to 32-bit paging. Status: For the steppings affected, see the Summary Tables of Changes. BP55.
Implication: Software in VMX root operation may execute with the “execute disable” feature enabled despite the fact that the feature should be disabled by the IA32_MISC_ENABLE MSR. Intel has not observed this erratum with any commercially available software. Workaround: A virtual-machine monitor should not allow guest software to write to the IA32_MISC_ENABLE MSR. Status: For the steppings affected, see the Summary Tables of Changes. BP59. Performance Monitor Counter MEM_INST_RETIRED.
Intel® Xeon® Processor E7-8800/ 4800/2800 Product Families BIOS ACM Errata AC1. BIOS ACM Exit INIT (LockConfig) Call May Fail on Certain IOH Bus Configurations Problem: With certain IOH bus configurations, the BIOS ACM Exit Init (LockConfig) call may be unable to lock the IOHs and the call will fail. Implication: When this erratum occurs, the TXT.HEAP.BASE and TXT.HEAP.SIZE registers will be locked, and BIOS will be unable to setup TXT heap memory for MLE (Measured Launch Environment) boot.
Intel® Xeon® Processor E7-8800/ 4800/2800 Product Families SINIT ACM Errata AS1. TXT.ERRORCODE TPM Command Return Code And Launch Control Policy List Index And Minor Code Are Not Reported Correctly. Problem: On affected SINIT ACM releases, the TXT.ERRORCODE register TPM command return code (bits 24:16), Launch Control Policy List Index (bits 24:22) and Launch Control Policy Minor Code (bits 21:16) are not reported correctly. Implication: Software depending upon TXT.
Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Xeon® Processor E7-8800/4800/2800 Product Families Datasheet, Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: Instruction Set Reference Manual N-Z
Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: • Intel® Xeon® Processor E7-8800/4800/2800 Product Families Datasheet, Volumes 1 and 2. • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture. • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M.
Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture. • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M. • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: Instruction Set Reference Manual N-Z.
November 2014 Intel® Xeon® Processor E7-8800/4800/2800 Product Families Specification Update
