Dual-Core Intel® Xeon® Processor 7000 Series Datasheet Revision 2.
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Contents 1 Introduction....................................................................................................................... 11 1.1 Terminology......................................................................................................... 12 1.2 Reference Documents......................................................................................... 14 1.3 State of Data .......................................................................................................
6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 On-Demand Mode.................................................................................. 71 PROCHOT# Signal Pin .......................................................................... 71 FORCEPR# Signal Pin .......................................................................... 72 THERMTRIP# Signal Pin ....................................................................... 72 Tcontrol and Fan Speed Reduction .................................................
Figures 2-1 2-2 2-3 8-2 8-3 8-4 8-5 8-6 8-7 On-Die Front Side Bus Termination .................................................................... 15 Phase Lock Loop (PLL) Filter Requirements ...................................................... 17 Dual-Core Intel® Xeon® Processor 7000 SeriesLoad Current vs. Time.................................................................................................. 26 VCC Static and Transient Tolerance...........................................................
2-16 2-17 3-1 3-2 3-3 4-1 4-2 5-1 6-1 6-2 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 6 GTL+ Asynchronous and AGTL+ Asynchronous Signal Group DC Specifications ................................................................................................ 31 SMBus Signal Group DC Specifications ............................................................. 31 Processor Loading Specifications ..........................................................
Revision History Document Number Revision Number Description Date 309626 -001 • Initial release of this document November 2005 309626 -002 • Changed product name to Dual-Core Intel® Xeon® Processor 7000 Series September 2006 • Updated Section 1.
Dual-Core Intel® Xeon® Processor 7000 Series Datasheet
Features Available at 2.66 or 3.
Dual-Core Intel® Xeon® Processor 7000 Series Datasheet
1 Introduction The Dual-Core Intel® Xeon® processor 7000 series is Intel’s first dual core product for multi-processor servers, utilizing two physical Intel NetBurst® microarchitecture cores in one package. It maintains the tradition of compatibility with IA-32 software and includes features found in the Intel® Xeon® processor such as hyper pipelined technology, a Rapid Execution Engine, and an Execution Trace Cache.
Introduction which are accessed through an SMBus interface and contain information relevant to the particular processor and system in which it is installed. Thermal management and further thermal redundancy can be achieved with the use of the Thermal Monitor feature. Table 1-1.
Introduction transactions as well as interrupt messages pass between the processor and chipset over the FSB. • Functional Operation — Refers to the normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical, and thermal, are satisfied.
Introduction 1.
2 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Dual-Core Intel Xeon processor 7000 series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. The termination voltage level for the Dual-Core Intel Xeon processor 7000 series AGTL+ signals is VTT. Termination resistors are provided on the processor silicon and are terminated to VTT.
Electrical Specifications The BCLK[1:0] inputs directly control the operating speed for the FSB interface. The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. If lower speeds are desired, the appropriate ratio can be configured by setting bits [15:8] of the IA32_FLEX_BRVID_SEL_MSR.
Electrical Specifications 2.1.3 Phase Lock Loop (PLL) Power and Filter VCCA, VCCIOPLL are power sources required by the PLL clock generators on the Dual-Core Intel Xeon processor 7000 series. These are analog PLLs and they require low noise power supplies for minimum jitter. These supplies must be low pass filtered from VTT. The AC low-pass requirements, with input at VTT, are as follows: • • • • < 0.2 dB gain in pass band < 0.
Electrical Specifications processor. A minimum VCC voltage is provided in Table 2-7 and changes with frequency. This allows processors running at a higher frequency to have a relaxed minimum VCC voltage specification. The specifications have been set such that one voltage regulator can work with all supported frequencies. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings.
Electrical Specifications Table 2-3. Voltage Identification (VID) Definition VID5 VID4 VID3 VID2 VID1 VID0 VID (V) VID5 VID4 VID3 VID2 VID1 VID0 VID (V) 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.
Electrical Specifications 2.3 Reserved, Unused, and TESTHI Pins All RESERVED pins must be left unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section 5 for a pin listing for the processor and the location of all RESERVED pins. For reliable operation, always terminate unused inputs or bidirectional signals to their respective deasserted states.
Electrical Specifications 2.5 Front Side Bus Signal Groups The FSB signals are grouped by buffer type as listed in Table 2-4. The buffer type indicates which AC and DC specifications apply to the signals. AGTL+ input signals have differential input buffers that use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving.
Electrical Specifications Table 2-5. Signal Description Table Signals with RTT1 A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOT_SELECT2, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#, HITM#, LOCK#, MCERR#, ODTEN3, REQ[4:0]#, RS[2:0]#, TEST_BUS, RSP#, TCK4, TDI4, TMS4, TRDY#, TRST#4 Signals with RL BINIT#, BNR#, HIT#, HITM#, MCERR# NOTES: 1. Signals not included in the “Signals with RTT” list require termination on the baseboard.
Electrical Specifications 2.7 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the TAP logic, Intel recommends that the Dual-Core Intel Xeon processor 7000 series be first in the TAP chain, followed by any other components within the system. Use of a translation buffer to connect to the rest of the chain is recommended unless one of the other components is capable of accepting an input of the appropriate voltage.
Electrical Specifications 2.9 Processor DC Specifications The following notes apply: • The processor DC specifications in this section are defined at the processor core silicon and not at the package pins unless noted otherwise. • The notes associated with each parameter are part of the specification for that parameter. • Unless otherwise noted, all specifications in the tables apply to all frequencies and cache sizes. See Section 5 for the pin signal definitions.
Electrical Specifications Table 2-8. Voltage and Current Specifications (Sheet 2 of 2) Symbol ICC_TDC Parameter Min ICC for Dual-Core Intel Xeon processor 7000 series Thermal Design Current 2.8 - FMB GHz Typ Max 130 Unit A Notes1 7, 20, 13 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on silicon characterization, however they may be updated as further data becomes available. 2.
Electrical Specifications Figure 2-3. Dual-Core Intel® Xeon® Processor 7000 SeriesLoad Current vs. Time 155 Sustained Current (A) 150 145 140 135 130 125 0.01 0.1 1 10 100 1000 Time Duration (s) NOTES: 1. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization.
Electrical Specifications Table 2-9. VCC Static and Transient Tolerance Icc Vcc_max Vcc_typical Vcc_min Notes 0 VID-0.000 VID-0.020 VID-0.040 1,2,3 5 VID-0.006 VID-0.026 VID-0.046 1,2,3 10 VID-0.013 VID-0.033 VID-0.052 1,2,3 15 VID-0.019 VID-0.039 VID-0.059 1,2,3 20 VID-0.025 VID-0.045 VID-0.065 1,2,3 25 VID-0.031 VID-0.051 VID-0.071 1,2,3 30 VID-0.038 VID-0.058 VID-0.077 1,2,3 35 VID-0.044 VID-0.064 VID-0.084 1,2,3 40 VID-0.050 VID-0.070 VID-0.
Electrical Specifications Figure 2-4. VCC Static and Transient Tolerance Ic c [ A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 V ID - 0 .0 0 0 V ID - 0 .0 2 0 V CC M a x im u m V ID - 0 .0 4 0 V ID - 0 .0 6 0 V ID - 0 .0 8 0 Vcc [V] V ID - 0 .1 0 0 V ID - 0 .1 2 0 V CC T y p ic a l V ID - 0 .1 4 0 V ID - 0 .1 6 0 V CC M in im u m V ID - 0 .1 8 0 V ID - 0 .2 0 0 V ID - 0 .2 2 0 V ID - 0 .2 4 0 NOTES: 1. 2. 3. 4.
Electrical Specifications Figure 2-5. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. Table 2-11. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit VL Input Low Voltage -0.150 VH Input High Voltage 0.
Electrical Specifications Table 2-12. BSEL[1:0], VID[5:0], and DC Specifications Symbol Parameter Max Unit Notes 1 RON Buffer On Resistance 60 Ω IOL Max Pin Current 8 mA ILO Output Leakage Current 200 µA 2 VTOL Voltage Tolerance 3.3 + 5% V 3 NOTES: 1. These parameters are not tested and are based on design simulations. 2. Leakage to VSS with pin held at 2.5 V. 3. Represents the maximum allowable termination voltage. Table 2-13.
Electrical Specifications Table 2-15. PWRGOOD Input and TAP Signal Group DC Specifications (Sheet 2 of 2) Symbol Parameter IOL Output Leakage Current RON Buffer On Resistance Min Max Unit N/A ±200 µA 4 8 Ω Notes NOTES: 1. All outputs are open drain. 2. The VTT represented in these specifications refers to instantaneous VTT. 3. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 4.
Electrical Specifications 32 Dual-Core Intel® Xeon® Processor 7000 Series Datasheet
3 Mechanical Specifications The Dual-Core Intel Xeon processor 7000 series is packaged in a FC-mPGA4 package that interfaces with the motherboard via a mPGA604 socket. The package consists of a processor core mounted on a substrate pin-carrier. An IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor package components and how they are assembled together.
Mechanical Specifications Figure 3-2.
Mechanical Specifications Figure 3-3.
Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout zones. 3.
Mechanical Specifications 3.4 Package Handling Guidelines Table 3-2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 3-2. Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N [80 lbf] 1, 2 Tensile 156 N [35 lbf] 3, 2 Torque 8 N-m [70 lbf-in] 4, 2 NOTES: 1.
Mechanical Specifications 3.8 Processor Markings Figure 3-4 shows the topside markings and Figure 3-5 shows the bottom-side markings on the processor. These diagrams are to aid in the identification of the Dual-Core Intel Xeon processor 7000 series. Please note that the figures in this section are not to scale. Figure 3-4.
Mechanical Specifications 3.9 Processor Pin-Out Coordinates Figure 3-6 shows the top view of the processor pin coordinates. The coordinates are referred to throughout the document to identify processor pins. Figure 3-6.
Mechanical Specifications Figure 3-7.
4 Pin Listing 4.1 Dual-Core Intel Xeon Processor 7000 Series Pin Assignments Section 2.5 contains the front side bus signal groups for the Dual-Core Intel Xeon processor 7000 series (see Table 2-4). This section provides a sorted pin list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor pins ordered alphabetically by pin name. Table 4-2 is a listing of all processor pins ordered by pin number. 4.1.1 Pin Listing by Pin Name Table 4-1. Pin Listing by Pin Name (Cont’d) Table 4-1.
Pin Listing Table 4-1. Pin Listing by Pin Name (Cont’d) Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No. Signal Buffer Type Direction Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Cont’d) Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No. Signal Buffer Type Direction DBI1# AD22 Source Sync Input/Output Don’t Care N1 DBI2# AE12 Source Sync Input/Output Don’t Care N3 DBI3# AB9 Source Sync Input/Output Don’t Care N5 DBSY# F18 Common Clk Input/Output Don’t Care N7 DEFER# C23 Common Clk Input Don’t Care N9 Pin Name Pin Name Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Cont’d) Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No. Signal Buffer Type VCC D18 Power/Other VCC D24 VCC D31 VCC Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No. Signal Buffer Type VCC T30 Power/Other Pin Name Direction Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No. Signal Buffer Type VSS E9 Power/Other VSS E15 VSS E17 VSS Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Cont’d) Pin Name VSS Pin No. Signal Buffer Type P7 Power/Other Direction Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No. Signal Buffer Type VSS AD17 Power/Other VSS AD23 Vss AE6 VSS AE11 VSS Table 4-1. Pin Listing by Pin Name (Cont’d) Pin No.
Pin Listing 4.1.2 Pin Listing by Pin Number Table 4-2. Pin Listing by Pin Number Pin No. A1 50 Pin Name VID5 A2 Don’t Care A3 SKTOCC# Signal Buffer Type Power/Other Power/Other Direction Output Output Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No. C17 Pin Name A8# Signal Buffer Type Direction Source Sync Input/Output Input/Output Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No. 52 Pin Name F6 BPM0# F7 F8 Signal Buffer Type Direction Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No. K3 Pin Name Signal Buffer Type Direction Don’t Care K4 VSS K5 Don’t Care K6 VSS K7 Don’t Care Power/Other Power/Other Power/Other Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No. 54 Pin Name Signal Buffer Type Direction Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No. Pin Name Signal Buffer Type Direction Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No. AB7 Pin Name PWRGOOD Signal Buffer Type Async GTL+ Direction Input Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Cont’d) Pin No. AD27 Pin Name Signal Buffer Type Table 4-2. Pin Listing by Pin Number (Cont’d) Direction Pin No.
Pin Listing 58 Dual-Core Intel® Xeon® Processor 7000 Series Datasheet
5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (Sheet 1 of 7) Name A[39:3]# Type Description I/O A[39:3]# (Address) define a 240-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Dual-Core Intel Xeon processor 7000 series FSB.
Signal Definitions Table 5-1. Signal Definitions (Sheet 2 of 7) Name BNR# Type Description I/O BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal which must connect the appropriate pins of all processor system bus agents.
Signal Definitions Table 5-1. Signal Definitions (Sheet 3 of 7) Name D[63:0]# Type Description I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period.
Signal Definitions Table 5-1. Signal Definitions (Sheet 4 of 7) Name Type Description HIT# I/O HITM# I/O HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together, every other common clock.
Signal Definitions Table 5-1. Signal Definitions (Sheet 5 of 7) Name Type Description ODTEN I ODTEN (On-die termination enable) should be connected to VTT through a resistor to enable on-die termination for end bus agents. For middle bus agents, pull this signal down via a resistor to ground to disable on-die termination. Whenever ODTEN is high, on-die termination will be active, regardless of other states of the bus.
Signal Definitions Table 5-1. Signal Definitions (Sheet 6 of 7) Name Type SM_EP_A[2:0] I Description The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors. To set an SM_EP_A line high, a pull-up resistor should be used that is no larger than 1 kΩ. The processor includes a 10 kΩ pull-down resistor to VSS for each of these signals.
Signal Definitions Table 5-1. Signal Definitions (Sheet 7 of 7) Name Type Description VCCA I VCCA provides isolated power for the analog portion of the internal PLL’s. Use a discrete RLC filter to provide clean power. Refer to the appropriate platform design guide for complete implementation details. VCCIOPLL I VCCIOPLL provides isolated power for digital portion of the internal PLL’s.
Signal Definitions 66 Dual-Core Intel® Xeon® Processor 7000 Series Datasheet
6 Thermal Specifications 6.1 Package Thermal Specifications The Dual-Core Intel Xeon processor 7000 series requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Thermal Specifications The upper point of the thermal profile consists of the Thermal Design Power (TDP) defined in Table 6-1 and the associated TCASE value. The lower point of the thermal profile consists of x = PCONTROL_BASE and y = TCASE_MAX @ PCONTROL_BASE. Pcontrol is defined as the processor power at which TCASE, calculated from the thermal profile, corresponds to the lowest possible value of Tcontrol. This point is associated with the Tcontrol value (see Section 6.2.
Thermal Specifications Figure 6-1. Dual-Core Intel® Xeon® Processor 7000 Series Thermal Profile A 0.184 NOTE: Refer to the Dual-Core Intel® Xeon® Processor 7000 Sequence Thermal/Mechanical Design Guidelines for system and environmental implementation details. Table 6-2. Dual-Core Intel® Xeon® Processor 7000 Series Thermal Profile A Thermal Profile A Ψ ca = 0.
Thermal Specifications 6.1.2 Thermal Metrology The maximum and minimum case temperatures (TCASE) specified in Table 6-1 are measured at the geometric top center of the processor IHS. Figure 6-2 illustrates the location where TCASE temperature measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Dual-Core Intel® Xeon® Processor 7000 Sequence Thermal/Mechanical Design Guidelines. Figure 6-2.
Thermal Specifications operating temperature. Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. With a thermal solution designed to meet the thermal profile, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications.
Thermal Specifications 6.2.4 FORCEPR# Signal Pin The FORCEPR# (force power reduction) input can be used by the platform to force the Dual-Core Intel Xeon processor 7000 series processor to activate the TCC. If the Thermal Monitor is enabled, the TCC will be activated upon the assertion of the FORCEPR# signal. The TCC will remain active until the system deasserts FORCEPR#. FORCEPR# is an asynchronous input. FORCEPR# can be used to thermally protect other system components.
7 Features 7.1 Power-On Configuration Options Several configuration options can be set by hardware. The Dual-Core Intel Xeon processor 7000 series samples its hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 7-1. The sampled information configures the processor for subsequent operation. These configuration options can only be changed by another reset. All resets configure the processor.
Features 7.2.2 HALT Power Down State HALT is a low power state entered when the processor executes the HALT instruction. The processor transitions to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the FSB. RESET# causes the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state.
Features BINIT# is not serviced while the processor is in Stop-Grant state. The event is latched and can be serviced by software upon exit from the Stop-Grant state. RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state occurs with the deassertion of the STPCLK# signal. A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the FSB (see Section 7.2.4).
Features Enhanced Intel SpeedStep® Technology 7.3 Enhanced Intel SpeedStep Technology enables the processor to switch between multiple frequency and voltage points, which may result in platform power savings. In order to support this technology, the system must support dynamic VID transitions. Switching between voltage/frequency states is software controlled. For more configuration details also refer to the Prescott, Nocona and Potomac Processor BIOS Writer’s Guide (BWG).
Features The processor SMBus implementation uses the clock and data signals of the System Management Bus (SMBus) Specification. It does not implement the SMBSUS# signal. Layout and routing guidelines are available in the appropriate platform design guide document. For platforms which do not implement any of the SMBus features found on the processor, all of the SMBus connections, except SM_VCC, to the socket pins may be left unconnected (SM_ALERT#, SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0], SM_WP).
Features Table 7-2.
Features Table 7-2. Processor Information ROM Format (Sheet 2 of 3) # of Bits Offset/Section Function Notes Cache Data: 25 - 26h 16 Reserved Reserved for future use 27 - 28h 16 L2 Cache Size per core 16-bit hexadecimal number (in KB) 29 - 2Ah 16 L3 Cache Size 16-bit hexadecimal number (in KB). 16 Processor Cache VID 16-bit hexadecimal Vcache value requested by CVID output (in mV). 16 Cache Voltage, Minimum 16-bit hexadecimal Vcache value Minimum Processor DC Cache Voltage in (in mV).
Features Table 7-2. Processor Information ROM Format (Sheet 3 of 3) # of Bits Offset/Section Function Notes 8 Additional Processor Feature Flags 16 Thermal Adjustment Factors [15:8] Measurement Correction Factor (Pending) [7:0] Temperature Target 7Ah 7B-7Ch 7.4.
Features Table 7-4. Write Byte SMBus Packet 7.4.4 S Slave Address Write A Command Code A Data A P 1 7-bits 1 1 8-bits 1 8-bits 1 1 SMBus Thermal Sensor The processor’s SMBus thermal sensor provides a means of acquiring thermal data from the processor. The thermal sensor is composed of control logic, SMBus interface logic, precision analog-to-digital converters, and precision current sources.
Features Table 7-6. Read Byte SMBus Packet S Slave Address Write Ack Command Code Ack S 1 7-bits 0 1 8-bits 1 1 Slave Read Address 7-bits 1 Ack Data /// P 1 8-bits 1 1 Table 7-7. Send Byte SMBus Packet S Slave Address Write Ack Command Code Ack P 1 7-bits 0 1 8-bits 1 1 Table 7-8. Receive Byte SMBus Packet S Slave Address Read Ack Data /// P 1 7-bits 1 1 8-bits 1 1 /// P 1 1 Table 7-9.
Features Table 7-10. SMBus Thermal Sensor Command Byte Assignments Register Command R/W Reset State RESERVED2 00h N/A RESERVED Ch. 1 Temp. Value1 01h R 0000 0000 Status Register 1 02h R Undefined Configuration Register 03h R 0000 0000 Conversion Rate Register 04h R 0000 0111 RESERVED2 05h - 06h N/A RESERVED Ch. 1 Temp. High Limit1 07h R 0101 0101 Limit1 08h R 0000 0000 Ch. 1 Temp.
Features Note: Writing to a read-command register or reading from a write-command register will produce invalid results. The default command after reset is to a reserved value (00h). After reset, Receive Byte SMBus packets will return invalid data until another command is sent to the thermal sensor. 7.4.6 SMBus Thermal Sensor Registers 7.4.6.
Features alarm condition persists). If the SM_ALERT# signal is enabled via the Thermal Sensor Configuration Register and a thermal diode threshold is exceeded, an alert will be sent to the platform via the SM_ALERT# signal. Table 7-12. SMBus Thermal Sensor Status Register 1 Bit Name Reset State Function 7 (MSB) BUSY N/A 6 RESERVED RESERVED Reserved for future use. 5 RESERVED RESERVED Reserved for future use.
Features Table 7-14. SMBus Thermal Sensor Configuration Register (Sheet 2 of 2) 7.4.6.5 Bit Name Reset State Function 6 RUN/STOP 0 Stand-by mode control bit. If set the device immediately stops converting, and enters stand-by mode. It will perform new temperature measurements when a one-shot is performed. If cleared the device automatically updates on a timed basis. 5 AL/TH 0 This bit selects the function of pin 13. Default = 0 = ALERT. Always set this bit to 0.
Features Table 7-15. SMBus Thermal Sensor Conversion Rate Register (Sheet 2 of 2) Bit Name Reset State 5:4 Channel Selector 00 Function These bits are used to select the temperature measurement channels. 00 = Round robin 01 = Local Temperature 10 = Remote 1 Temperature 11 = Remote 2 Temperature Default = 00. Always set these bits to 00 3:0 Conversion Rates 1000 These bits determine how often the temperature sensor measures each temperature channel. Bit encoding = Conversions / sec 0000 = 0.
Features 7.4.8 SMBus Device Addressing Of the addresses broadcast across the SMBus, the memory component claims those of the form “1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors on the system baseboard. These address pins are pulled down weakly (10 kΩ) on the processor substrate to ensure that the memory components are in a known state in systems which do not support the SMBus (or only support a partial implementation).
Features Table 7-17. Memory Device SMBus Addressing Address (Hex) Upper Address1 Device Select R/W bits 7-4 SM_EP_A2 bit 3 SM_EP_A1 bit 2 SM_EP_A0 bit 1 bit 0 A0h/A1h 1010 0 0 0 X A2h/A3h 1010 0 0 1 X A4h/A5h 1010 0 1 0 X A6h/A7h 1010 0 1 1 X A8h/A9h 1010 1 0 0 X AAh/ABh 1010 1 0 1 X ACh/ADh 1010 1 1 0 X AEh/AFh 1010 1 1 1 X NOTE: 1. This addressing scheme will support up to 8 processors on a single SMBus. 7.4.
Features The Header also includes the data format revision at offset 0h and the EEPROM size (formatted in hex bytes) at offset 01-02h. The data format revision is used whenever fields within the PIROM are redefined. Normally the revision would begin at a value of 1. If a field, or bit assignment within a field, is changed such that software needs to discern between the old and new definition, then the data format revision field should be incremented.
Features 7.4.9.3.2 Front Side Bus Frequency Offset 1A - 1Bh provides FSB frequency information. Systems may need to read this offset to decide if all installed processors support the same FSB speed. Because the Intel NetBurst® microarchitecture bus is described as a 4x data bus, the frequency given in this field is currently 667 MHz. The data provided is the speed, rounded to a whole number, and reflected in hex. Example: The Dual-Core Intel Xeon processor 7000 series supports a 667 MHz FSB.
Features 7.4.9.4 Cache Data This section contains cache-related data. 7.4.9.4.1 L2 Cache Size Offset 27 - 28h is the L2 cache size field. The field reflects the size of the level two cache for each core in kilobytes. Example: The Dual-Core Intel Xeon processor 7000 series may have a 2 MB (2048 KB) L2 cache per core. Thus, offset 27 - 28h will contain 800h. 7.4.9.4.2 L3 Cache Size Offset 29 - 2Ah is the L3 cache size field. The field reflects the size of the level three cache in kilobytes.
Features 7.4.9.6.1 Processor Part Number Offset 38 - 3Eh contains seven ASCII characters reflecting the Intel part number for the processor. This information is typically marked on the outside of the processor. If the part number is less than 7 characters, a leading space is inserted into the value. The part number should match the information found in the marking specification found in Section 3. Example: The Intel Xeon processor with 512 KB L2 cache (533 MHz FSB) has a part number of 80532KE.
Features Table 7-19. Offset 79h Definitions (Sheet 2 of 2) Bits Definition 3:2 Number of cores 1:0 Number of threads per core Example: The Dual-Core Intel Xeon processor 7000 series has two cores and two threads per core. Therefore, this register will have a value of 0Ah 7.4.9.7.4 Additional Processor Feature Flags Offset 7Ah provides additional feature information for the processor. This field is defined as follows: Table 7-20.
Features Table 7-22. 128 Byte ROM Checksum Values Section Checksum Address Header 0Dh Processor Data 15h Processor Core Data 24h Cache Data 31h Package Data 37h Part Number Data 6Fh Thermal Reference Data 73h Feature Data 7Fh Other Data None Defined Checksums are automatically calculated and programmed by Intel. The first step in calculating the checksum is to add each byte from the field to the next subsequent byte. This result is then negated to provide the checksum.
Features 96 Dual-Core Intel® Xeon® Processor 7000 Series Datasheet
8 Boxed Processor Specifications 8.1 Introduction The Dual-Core Intel Xeon processor 7000 series will be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The boxed thermal solution is under development and is subject to change. This section is meant to provide some insight into the current direction of the thermal solution.
Boxed Processor Specifications NOTE: 1. The heatsink in this image is for reference only. 2. This drawing shows the retention scheme for the boxed processor. 8.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor passive heatsink. 8.2.1 Boxed Processor Heatsink Dimensions The boxed processor is shipped with an unattached passive heatsink. Clearance is required around the heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 8-2.
Boxed Processor Specifications Figure 8-3.
Boxed Processor Specifications Figure 8-4.
Boxed Processor Specifications Figure 8-5.
Boxed Processor Specifications Figure 8-6.
Boxed Processor Specifications Figure 8-7. Recommended Processor Layout and Pitch 8.2.2 Boxed Processor Heatsink Weight The boxed processor heatsink weight is approximately 530 grams. See Section 3 of this document for details on the processor weight. 8.2.3 Boxed Processor Retention Mechanism and Heatsink Supports Baseboards and chassis’s designed for use by system integrators should include holes that are in proper alignment with each other to support the boxed processor.
Boxed Processor Specifications solution limitations by using a load path attached to the chassis pan. The hat spring on the under side of the baseboard provides the necessary compressive load for the thermal interface material. The baseboard is intended to be isolated such that the dynamic loads from the heatsink are transferred to the chassis pan via the heatsink screws and heatsink standoffs. This reduces the risk of package pullout and solder joint failures in a shock and vibe situation.
Boxed Processor Specifications 106 Dual-Core Intel® Xeon® Processor 7000 Series Datasheet
9 Debug Tools Specifications Please refer to the ITP700 Debug Port Design Guide, eXtended Debug Port: Debug Port Design Guide for Twin Castle Chipset Platforms, eXtended Debug Port: Debug Port Design Guide for MP Platforms, and the appropriate platform design guide for more detailed information regarding debug tools specifications. 9.
Debug Tools Specifications 108 Dual-Core Intel® Xeon® Processor 7000 Series Datasheet
