Intel® E7320 Memory Controller Hub (MCH) Specification Update June 2005 Notice: The Intel® E7320 MCH may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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Contents Revision History ................................................................................................................. 4 Preface ............................................................................................................................... 5 Summary Table of Changes ............................................................................................... 6 Identification Information ..................................................................................
Revision History Revision History Version -001 -002 Description Date • Initial publication. August 2004 • Added C4 Stepping information. November 2004 • Added errata 24 -26. -003 4 • Added Specification Clarification 1.
Preface This document is an update to the memory interface specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and document errata and specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the this update document and are no longer published in other documents.
Summary Table of Changes Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the E7320 MCH. Intel may fix some errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations: Codes Used in Summary Table X: Errata exists in the stepping indicated.
Summary Table of Changes Errata Stepping No.
Summary Table of Changes Specification Changes Number SPECIFICATION CHANGES None for this revision of the Specification Update Specification Clarifications Number 1 SPECIFICATION CLARIFICATIONS Clarification to Section 4.4.
Identification Information Identification Information Component Identification via Programming Interface The Intel® E7320 MCH can be identified by the following register contents: MCH Version Stepping Vendor ID1 Device ID2 Revision Number3 E7320 C-1 8086h 3592h 09h E7320 C-2 8086h 3592h 0Ah E7320 C-4 8086h 3592h 0Ch NOTES: 1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00 - 01h in the PCI bus 0, device 0, function 0 configuration space. 2.
Errata Errata 1. Data corruption after an illegal front side bus configuration Write Problem: When an illegal FSB configuration write occurs (bits [30:24] of the Configuration Address Register (CONFIG_ADDRESS, I/O address 0CF8h) are non-zero) PCI configuration accesses following this write may be corrupted. Implication: This is a mishandled error case and causes corruption of transactions after this transaction. This is an illegal case.
Errata 5. Incorrect PCI Express Link/Lane numbers driven in degraded link Problem: If a failure of receiver detect or bit/symbol lock occurs on lane 0 (lane 7 in the case of physical lane reversal) while other lanes successfully achieve bit/symbol lock in the early stages of Polling.Active, the MCH will exhibit anomalous lane numbering during the ensuing failed training sequence.
Errata Implication: A spurious error is flagged, and accesses between 4 GB and 32 GB will not succeed in the 32 GB (maximum) memory configuration, which can result in a system hang. Workaround: Refer to your Intel representative for details the Intel® E7520, E7320, and E7525 Memory Controller Hub (MCH) Components BIOS Specification for details. Status: For the steppings effected, see the Summary Table of Changes. 10.
Errata Register Device:Function:Offset DRAM_SCRB_ADD D0:F1:A8-ABh DRAM_RETR_ADD D0:F1:AC-AFh DRAM_SEC2_ADD D0:F1:C8-CBh Implication: Software cannot rely on these bits. Workaround: Refer to your Intel Representative for workaround details. Status: For the steppings effected, see the Summary Table of Changes. 14. MCH transitions from Polling.Active prematurely Problem: During a standard link training sequence, the MCH should remain in Polling.
Errata Express specification requires that the link attempt to train as a x1 on lane 0 - the MCH will not train in this scenario. Failures are anticipated to occur because of a broken transmitter/receiver path, or a silent transmitter. None of those failure modes will cause the MCH to fail to train, since either the receiver termination will be missing, or the transmitted signals will not be seen at the MCH.
Errata should also ensure that the Completion Timeout Error Mask is set in MCH root ports associated with inactive PCI Express links (unpopulated slots or disabled devices) -- refer to erratum 15 for detail. Status: For the steppings effected, see the Summary Table of Changes. 19. PCI Express x4, x8 links may train down to lower width Problem: It has been observed that x4, x8 links may fail to train to their full link widths. This behavior occurs infrequently.
Errata Under normal operation, a transition into S3-S5 will have the following processor bus signature: 1. ICH asserts STPCLK# to the processor. 2. Processor issues a Stop Grant Acknowledge transaction on the processor bus. 3. ICH asserts SLP# to the processor. In the failing case steps 1 and 2 are observed, but step 3 is not. Implication: System may hang during a power management transition. Workaround: Refer to your Intel Representative for workaround details.
Errata Workaround: Limit the uninterrupted duration (total data payload size) for transfers between peer PCI Express ports, such that no one continuous transfer will exceed a duration of 16.7 ms. For reference, each x4 PCI Express port is capable of transferring well over 12 MB of data in 16.7 ms, thus an uninterrupted blockage of such duration is not expected to occur unless extreme circumstances are contrived. Status: For the steppings effected, see the Summary Table of Changes. 25.
Errata Custom operating systems or future operating systems that independently manage the power state of PCI Express devices outside the scope of system power state transitions would be similarly exposed to link-down errors via the same mechanism. In cases where the destination power state on the attached device is between D0 and D3, any such link-down event constitutes a real error from which software may only recover by fully reconfiguring the devices below the affected link.
Specification Changes Specification Changes There are no Specification Changes in this revision of the Specification Update.
Specification Clarifications Specification Clarifications 1. Clarification to Section 4.4.1, “Memory Remapping”, in the EDS Section 4.4.1 currently reads as follows: 4.4.1 Memory Remapping An incoming address (referred to as a logical address) is checked to see if it falls in the memory remap window. The bottom of the remap window is defined by the value in the REMAPBASE register. The top of the remap window is defined by the value in the REMAPLIMIT register.
Documentation Changes Documentation Changes There are no Documentation Changes in this revision of the Specification Update. 1. Interupt Redirection The bit definition for the hardware interrupt redirection has been added. The following changes will be reflected in the next release of the Datasheet.
Documentation Changes 22 Intel® E7320 Memory Controller Hub (MCH) Specification Update
