Intel® Core™ i5-600, i3-500 Desktop Processor Series, Intel® Pentium® Desktop Processor 6000 Series Datasheet – Volume 1 This is volume 1 of 2 January 2011 Document Number: 322909-006
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Contents 1 Introduction .............................................................................................................. 9 1.1 Processor Feature Details ................................................................................... 11 1.1.1 Supported Technologies .......................................................................... 11 1.2 Interfaces ........................................................................................................ 11 1.2.
2.5 2.6 2.4.2.1 Display Planes ..........................................................................31 2.4.2.2 Display Pipes ............................................................................32 2.4.2.3 Display Ports ............................................................................32 2.4.3 Intel® Flexible Display Interface ...............................................................32 Platform Environment Control Interface (PECI) .................................................
6 Signal Description ................................................................................................... 53 6.1 System Memory Interface .................................................................................. 54 6.2 Memory Reference and Compensation .................................................................. 56 6.3 Reset and Miscellaneous Signals.......................................................................... 56 6.4 PCI Express* Based Interface Signals............
8-2 Socket Pinmap (Top View, Upper-Right Quadrant) ........................................................86 8-3 Socket Pinmap (Top View, Lower-Left Quadrant) ..........................................................87 8-4 Socket Pinmap (Top View, Lower-Right Quadrant) ........................................................
Revision History Revision Number Description Date 001 • Initial release January 2010 002 • Added workstation information January 2010 003 • Added Intel® Core™ i5-680 processor April 2010 004 • Added Intel® Core™ i5-655K processor and Intel® Core™ i3-550 processor June 2010 005 • Added Intel® Core™ i3-560 processor August 2010 006 • Added the series designation “Intel® Pentium® desktop processor 6000 series”. • Added the Intel ® Pentium® processor G6960.
Datasheet, Volume 1
Introduction 1 Introduction The Intel® Core™ i5-600, i3-500 desktop processor series and Intel® Pentium® desktop processor 6000 series are the next generation of 64-bit, multi-core processors built on 32-nanometer process technology. Based on the low-power/high-performance Intel microarchitecture, the processor is designed for a two-chip platform, instead of the traditional three-chip platforms (processor, (G)MCH, and ICH).
Introduction Figure 1-1. Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Platform Diagram Discrete Graphics (PEG) PCI Express* 1x16 Processor DDR3 DIMMs 2 Channels (2 UDIMM/Channel) OR PCI Express* 2x 8 DDR3 DIMMs Note: Supported PCI Express configurations vary by processor and SKU. Intel® Flexible Display Interface DMI PECI Serial ATA Intel® Management Engine USB 2.0 Intel® 5 Series Chipset Intel® HD Audio SMBUS 2.
Introduction 1.1 Processor Feature Details • Two cores • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data second-level cache (L2) for each core • Up to 4-MB shared instruction/data third-level cache (L3), shared among all cores 1.1.
Introduction • 1-Gb and 2-Gb DDR3 DRAM technologies are supported.
Introduction • 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros). • 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.
Introduction 1.2.4 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between processor and a PECI master, usually the PCH. 1.2.
Introduction 1.3 Power Management Support 1.3.1 Processor Core • Full support of ACPI C-states as implemented by the following processor C-states: — C0, C1, C1E, C3, C6 • Enhanced Intel SpeedStep® Technology 1.3.2 System • Desktop Intel 5 Series Chipset platforms support: S0, S1, S3, S4, S5 • Workstation Intel 3400 Series Chipset platforms support: S0, S1, S3, S4, and S5 1.3.3 Memory Controller • Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM)) • Dynamic power-down 1.3.
Introduction Term DMA Direct Memory Access DMI Direct Media Interface DTS Digital Thermal Sensor ECC Error Correction Code Enhanced Intel SpeedStep® Technology Technology that provides power management capabilities. Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory, the processor raises an error to the operating system.
Introduction Term Description Processor Core The term “processor core” refers to Si die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the L3 cache. Rank A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a DIMM. SCI System Control Interrupt. Used in ACPI protocol.
Introduction 1.7 Related Documents Refer to the following documents for additional information. Table 1-1. Related Documents Document Document Number/ Location Voltage Regulator-Down (VRD) 11.1 Design Guidelines http://download.intel.com/design /processor/designex/322172.pdf Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet, Volume 2 http://download.intel.com/design /processor/datashts/322910.
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. 2.1 System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels each accessing one or two DIMMs.
Interfaces Table 2-1.
Interfaces 2.1.3 System Memory Organization Modes The IMC supports two memory organization modes, single-channel and dual-channel. Depending upon how the DIMM Modules are populated in each memory channel, a number of different configurations can exist. 2.1.3.1 Single-Channel Mode In this mode, all memory cycles are directed to a single-channel. Single-channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order, but not both. 2.1.3.
Interfaces When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory, IMC operates completely in Dual-Channel Symmetric mode. Note: The DRAM device technology and width may vary from one channel to the other. 2.1.3.2.2 Dual-Channel Asymmetric Mode This mode trades performance for system design flexibility.
Interfaces 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.1 Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next.
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express. The number of PCI Express controllers available is dependent on the platform: • Processor with desktop Intel 5 Series Chipset: 1 x 16 PCI Express Graphics is supported. • Processor with Intel 5 Series Chipset P55 and P57 SKUs: 2 x 8 PCI Express Graphics is supported.
Interfaces PCI Express uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers.
Interfaces 2.2.2 PCI Express* Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-5.
Interfaces 2.3 Direct Media Interface (DMI) DMI connects the processor and the PCH chip-to-chip. The DMI is similar to a four-lane PCI Express supporting up to 1 GB/s of bandwidth in each direction. Note: Only DMI x4 configuration is supported. 2.3.1 DMI Error Flow DMI can only generate SERR in response to errors—never SCI, SMI, MSI, PCI INT, or GPE. Any DMI related SERR activity is associated with Device 0. 2.3.
Interfaces Figure 2-6. Processor Graphic Processing Unit Block Diagram Plane A Video Engine Sprite A Pipe A 2D Engine Cursor A Memory 3D Engine Vertex Fetch/Vertex Shader VGA Alpha Blend/ Gamma/ Panel Fitter M U X Intel® FDI Plane B Geometry Shader Pipe B Sprite B Clipper Strip & Fan/Setup Cursor B Windower/IZ 2.4.
Interfaces 2.4.1.2.3 Geometry Shader (GS) Stage The GS stage receives inputs from the VS stage. Compiled application-provided GS programs, specifying an algorithm to convert the vertices of an input object into some output primitives. For example, a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line.
Interfaces 2.4.1.4.2 Logical 128-Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The 128-bit, integrated graphics BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations.
Interfaces 2.4.2 Integrated Graphics Display The Graphics Processing Unit’s display pipe can be broken down into three components: • Display Planes • Display Pipes • DisplayPort and Intel FDI Figure 2-7. Processor Display Block Diagram Plane A Sprite A Cursor A VGA Plane B Sprite B Alpha Blend/ Gamma/ Panel Fitter Pipe A M U X Intel® FDI Pipe B Cursor B 2.4.2.1 Display Planes A display plane is a single displayed surface in memory and contains one image (desktop, cursor, overlay).
Interfaces 2.4.2.1.3 Cursors A and B Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration, and are associated with Planes A and B respectively. These planes support resolutions up to 256 x 256 each. 2.4.2.1.4 VGA VGA is used for boot, safe mode, legacy games, and so forth This mode can be changed by an application without OS/driver notification, due to legacy requirements. 2.4.2.
Interfaces 2.5 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between processor and a PECI master, usually the PCH. The processor implements a PECI interface to: • Allow communication of processor thermal and other information to the PECI master. • Read averaged Digital Thermal Sensor (DTS) values for fan speed control. 2.6 Interface Clocking 2.6.1 Internal Clocking Requirements Table 2-4.
Interfaces 34 Datasheet, Volume 1
Technologies 3 Technologies 3.1 Intel® Virtualization Technology Intel Virtualization Technology (Intel VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets.
Technologies • Guest Preemption Timer — Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM.
Technologies 3.1.5 Intel® VT-d Features Not Supported The following features are not supported by the processor with Intel VT-d: • No support for PCISIG endpoint caching (ATS) • No support for interrupt remapping • No support for queue-based invalidation interface • No support for Intel VT-d read prefetching/snarfing; that is, translations within a cacheline are not stored in an internal buffer for reuse for subsequent translations.
Technologies 3.3 Intel® Hyper-Threading Technology The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology) that allows an execution core to function as two logical processors. While some execution resources such as caches, execution units, and buses are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers. This feature must be enabled using the BIOS and requires operating system support.
Power Management 4 Power Management This chapter provides information on the following power management topics: • ACPI States • Processor Core • IMC • PCI Express* • Integrated Graphics 4.1 ACPI States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States State Description G0/S0 Full On G1/S3-Cold Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor). G1/S4 Suspend-to-Disk (STD).
Power Management 4.1.4 PCI Express* Link States State 4.1.5 Description L0 Full on – Active transfer state. L0s First Active Power Management low power state – Low exit latency. L1 Lowest Active Power Management - Longer exit latency. L3 Lowest power state (power-off) – Longest exit latency. Integrated Graphics States State Description D0 Full on, display active D3 Cold power-off 4.1.6 Interface State Combinations Table 4-2. G, S, and C State Combinations Table 4-3.
Power Management 4.2 Processor Core Power Management While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power Cstates have longer entry and exit latencies. 4.2.
Power Management Figure 4-1. Idle Power Management Breakdown of the Processor Cores Thread 0 Thread 1 Core 0 State Thread 0 Thread 1 Core 1 State Processor Package State Entry and exit of the C-States at the thread and core level are shown in Figure 4-2. Figure 4-2.
Power Management Table 4-4. Coordination of Thread Power States at the Core Level Processor Core C-State Thread 1 C0 C1 C3 C6 C0 C0 C0 C0 C0 C1 C0 C11 C11 C11 C3 C0 C11 C3 C3 C6 C0 C11 C3 C6 Thread 0 Note: 1. If enabled, the core C-state will be C1E if all active cores have also resolved to a core C1 state or higher. 4.2.
Power Management 4.2.4 Core C-states The following are general rules for all core C-states, unless specified otherwise: • A core C-State is determined by the lowest numerical thread state (such that, Thread 0 requests C1E while thread1 requests C3, resulting in a core C1E state). See Table 4-4. • A core transitions to C0 state when: — an interrupt occurs. — there is an access to the monitored address if the state was entered using an MWAIT instruction.
Power Management 4.2.4.5 C-State Auto-Demotion In general, deeper C-states, such as C6, have long latencies and have higher energy entry/exit costs. The resulting performance and energy penalties become significant when the entry/exit frequency of a deeper C-state is high. Therefore, incorrect or inefficient usage of deeper C-states may have a negative impact on power consumption. To increase residency and improve power consumption in deeper C-states, the processor supports C-state auto-demotion.
Power Management Table 4-6 shows an example package C-state resolution for a dual-core processor. Figure 4-3 summarizes package C-state transitions. Table 4-6. Coordination of Core Power States at the Package Level Core 1 Package C-State C0 Core 0 C0 C11 C3 C6 C0 C0 C0 C0 C11 C0 C11 C11 C11 C3 C0 C11 C3 C3 C6 C0 C11 C3 C6 Note: 1. If enabled, the package C-state will be C1E if all actives cores have resolved a core C1 state or higher. Figure 4-3.
Power Management 4.2.5.2 Package C1/C1E No additional power reduction actions are taken in the package C1 state. However, if the C1E sub-state is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage. The package enters the C1 low power state when: • At least one core is in the C1 state. • The other cores are in a C1 or lower power state.
Power Management 4.3 Integrated Memory Controller (IMC) Power Management The main memory is power managed during normal operation and in low power ACPI Cx states. 4.3.1 Disabling Unused System Memory Outputs Any system memory (SM) interface signal that goes to a memory module connector in which it is not connected to any actual memory devices (such as, DIMM connector is unpopulated, or is single-sided) is tristated. The benefits of disabling unused SM signals are: • Reduced power consumption.
Power Management Table 4-7. Targeted Memory State Conditions Mode 4.3.2.3 Memory State with Internal Graphics Memory State with External Graphics C0, C1, C1E Dynamic memory rank power down based on idle conditions. Dynamic memory rank power down based on idle conditions. C3, C6 Dynamic memory rank power down based on idle conditions If the graphics engine is idle, no display requests, and permitted display configuration, then enter self-refresh.
Power Management 4.5 Integrated Graphics Power Management 4.5.1 Graphics Render C-State Render C-State (RC6) is a technique designed to optimize the average power to the graphics render engine during times of idleness of the render engine. Render C-state is entered when the graphics render engine, blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions.
Thermal Management 5 Thermal Management For thermal specifications and design guidelines, refer to the appropriate Thermal and Mechanical Specifications and Design Guidelines (see Section 1.7).
Thermal Management 52 Datasheet, Volume 1
Signal Description 6 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type. Notations Signal Type I Input Pin O Output Pin I/O Bi-directional Input/Output Pin The signal description also includes the type of buffer used for the particular signal. Table 6-1.
Signal Description 6.1 System Memory Interface Table 6-2. Memory Channel A Signal Name 54 Description Direction Type SA_BS[2:0] Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SA_CAS# CAS Control Signal: This signal is used with SA_RAS# and SA_WE# (along with SA_CS#) to define the SDRAM Commands. O DDR3 SA_CK#[1:0] SDRAM Inverted Differential Clock: Channel A SDRAM Differential clock signal-pair complement.
Signal Description Table 6-3. Memory Channel B Signal Name Description Direction Type SB_BS[2:0] Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SB_CAS# CAS Control Signal: This signal is used with SB_RAS# and SB_WE# (along with SB_CS#) to define the SDRAM Commands. O DDR3 SB_CK#[1:0] SDRAM Inverted Differential Clock: Channel B SDRAM Differential clock signal-pair complement.
Signal Description 6.2 Memory Reference and Compensation Table 6-4. Memory Reference and Compensation Signal Name Description SA_DIMM_VREFDQ SB_DIMM_VREFDQ Channel A and B Output DDR3 DIMM DQ Reference Voltage. SM_RCOMP[2:0] System Memory Impedance Compensation. 6.3 Reset and Miscellaneous Signals Table 6-5. Reset and Miscellaneous Signals (Sheet 1 of 2) Signal Name CFG[17:0] Description Configuration signals: The CFG signals have a default value of 1 if not terminated on the board.
Signal Description Table 6-5. Reset and Miscellaneous Signals (Sheet 2 of 2) Signal Name Description Direction Type COMP2 Impedance compensation must be terminated on the system board using a precision resistor. Refer to Table 7-11 for the termination requirement. I Analog COMP3 Impedance compensation must be terminated on the system board using a precision resistor. Refer to Table 7-11 for the termination requirement.
Signal Description 6.4 PCI Express* Based Interface Signals Table 6-6. PCI Express* Based Interface Signals Signal Name Description Direction Type PEG_ICOMPI PCI Express Current Compensation. I Analog PEG_ICOMPO PCI Express Current Compensation. I Analog PEG_RBIAS PCI Express Resistor Bias Control. I Analog PEG_RCOMPO PCI Express Resistance Compensation. I Analog PEG_RX[15:0] PEG_RX#[15:0] PCI Express Receive Differential Pair.
Signal Description 6.7 Intel® Flexible Display Interface Signals Table 6-9. Intel® Flexible Display Interface Signal Name 6.8 Description ® Direction Type FDI_FSYNC[0] Intel Flexible Display Interface Frame Sync—Pipe A. I CMOS FDI_FSYNC[1] Intel® Flexible Display Interface Frame Sync—Pipe B. I CMOS FDI_INT Intel® Flexible Display Interface Hot Plug Interrupt. I CMOS FDI_LSYNC[0] Intel® Flexible Display Interface Line Sync—Pipe A.
Signal Description 6.9 Error and Thermal Protection Table 6-11. Error and Thermal Protection Signal Name 60 Description Direction Type CATERR# Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.
Signal Description 6.10 Power Sequencing Table 6-12. Power Sequencing Signal Name 6.11 Description Direction Type SKTOCC# SKTOCC# (Socket Occupied): This signal will be pulled to ground on the processor package. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present. O SM_DRAMPWROK SM_DRAMPWROK processor input: This signal connects to PCH DRAMPWROK. I Asynch CMOS TAPPWRGOOD Power good for ITP.
Signal Description Table 6-13. Processor Core Power Signals (Sheet 2 of 2) Signal Name Description Direction Type I/O CMOS VID[7:0] (Voltage ID) are used to support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator-Down (VRD) 11.1 Design Guidelines for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals become valid.
Signal Description 6.12 Graphics and Memory Core Power Signals Table 6-14. Graphics and Memory Power Signals Signal Name 6.13 Description Direction Type GFX_DPRSLPVR Integrated graphics output signal to a VRD11.1 compliant VR. When asserted this signal indicates that the integrated graphics is in render suspend mode. This signal is also used to control render suspend state exit slew rate. O CMOS GFX_IMON Current Sense from an VRD11.1 compliant VR to the integrated graphics.
Signal Description 6.14 Processor Internal Pull Up/Pull Down Table 6-16.
Electrical Specifications 7 Electrical Specifications 7.1 Power and Ground Lands The processor has VCC, VTT, VDDQ, VCCPLL, VAXG, and VSS (ground) inputs for onchip power distribution. All power lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop.
Electrical Specifications 7.3 Processor Clocking (BCLK[0], BCLK#[0]) The processor uses a differential clock to generate the processor core(s) operating frequency, memory controller frequency, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by 133 MHz. Clock multiplying within the processor is provided by an internal phase locked loop (PLL) that requires a constant frequency input, with exceptions for Spread Spectrum Clocking (SSC).
Electrical Specifications 7.5 Graphics Voltage Identification (GFX_VID) A dedicated voltage regulator is required to deliver voltage to the integrated graphics core. The integrated graphics will use seven voltage identification pins, GFX_VID[6:0], to set the nominal operating voltage. The GFX_VID specification for the processor is defined by the Voltage Regulator Down (VRD) 11.0 Design Guidelines. Table 7-1 specifies the voltage level corresponding to the state of the GFX_VID signals.
Electrical Specifications Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 2 of 3) VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX 0 0 0 1 0 1 1 0 1.47500 0 1 1 1 0 0 0 1 0.90625 0 0 0 1 0 1 1 1 1.46875 0 1 1 1 0 0 1 0 0.90000 0 0 0 1 1 0 0 0 1.46250 0 1 1 1 0 0 1 1 0.89375 0 0 0 1 1 0 0 1 1.45625 0 1 1 1 0 1 0 0 0.
Electrical Specifications Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 3 of 3) VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX 0 0 1 1 1 1 1 0 1.22500 1 0 0 1 1 0 0 1 0.65625 0 0 1 1 1 1 1 1 1.21875 1 0 0 1 1 0 1 0 0.65000 0 1 0 0 0 0 0 0 1.21250 1 0 0 1 1 0 1 1 0.64375 0 1 0 0 0 0 0 1 1.20625 1 0 0 1 1 1 0 0 0.
Electrical Specifications Table 7-2. Market Segment Selection Truth Table for MSID[2:0] MSID2 MSID1 Description1 MSID0 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 1 0 1 Reserved 2009A processors supported 2 1 1 0 2009B processors supported 3 1 1 1 Reserved Notes: 1. The MSID[2:0] signals are provided to indicate the maximum platform capability to the processor. 2.
Electrical Specifications Table 7-3.
Electrical Specifications Table 7-3.
Electrical Specifications 7.8 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage.
Electrical Specifications 7.10 DC Specifications The processor DC specifications in this section are defined at the processor pads, unless noted otherwise. See Chapter 8 for the processor land listings and Chapter 6 for signal definitions. Voltage and current specifications are detailed in Table 7-5, Table 7-6, and Table 7-7. For platform planning, refer to Table 7-8 that provides VCC static and transient tolerances. This same information is presented graphically in Figure 7-1.
Electrical Specifications Table 7-6. Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications (Sheet 2 of 2) Symbol VCCPLL Parameter PLL supply voltage (DC + AC specification) Min Typ Max Unit 1.71 1.8 1.
Electrical Specifications Table 7-7. Processor Graphics VID based (VAXG) Supply DC Voltage and Current Specifications Symbol VAXG GFX_VID Range Parameter GFX_VID Range for VAXG VAXG VAXG LLAXG VAXG Loadline Slope Min Typ Max Unit Note 0.5 — 1.
Electrical Specifications 3. Figure 7-1. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_SENSE lands. Refer to the Voltage Regulator Down (VRD) 11.1 Design Guidelines for socket load line guidelines and VR implementation. VCC Static and Transient Tolerance Loadlines Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 VID - 0.000 VID - 0.
Electrical Specifications Table 7-9. VAXG Static and Transient Tolerance Voltage Deviation from GFX_VID Setting Notes: 1, 2, 3 IAXG (A) VAXG_Max (V) LLAXG = 6 m VAXG_NOMINAL (V) LLAXG = 6 m VAXG_Min (V) LLAXG = 6 m 0 0.020 0 -0.020 5 -0.010 -0.030 -0.050 10 -0.040 -0.060 -0.080 15 -0.070 -0.090 -0.110 20 -0.100 -0.120 -0.140 Notes: 1. The VAXG_MIN and VAXG_MAX loadlines represent static and transient limits. 2.
Electrical Specifications Table 7-10. DDR3 Signal Group DC Specifications Symbol Parameter Alpha Group Min Typ Max Units Notes1 — 0.43*VDDQ V 2,4 V 3 VIL Input Low Voltage (e,f) — VIH Input High Voltage (e,f) 0.
Electrical Specifications Table 7-11. Control Sideband and TAP Signal Group DC Specifications Symbol Alpha Group Min Typ Max Units Notes1 Input Low Voltage — — 0.64 * VTT V 2 Parameter VIL (m),(n),(p),(s) VIH (m),(n),(p),(s) Input High Voltage 0.76 * VTT — — V 2,4 VIL (g) Input Low Voltage — — 0.25 * VTT V 2 VIH (g) Input High Voltage 0.80 * VTT — — V 2,4 VIL (ga) Input Low Voltage — — 0.4 V VIH (ga) Input High Voltage 0.
Electrical Specifications Table 7-12. PCI Express* DC Specifications Symbol Alpha Group Parameter Min Typ Max Units Notes1 (ad) Differential peak to peak Tx voltage swing 0.8 — 1.
Electrical Specifications 7.11 Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications 7.11.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 7-3 as a guide for input buffer design. Figure 7-3. Input Device Hysteresis VTTD Maximum VP PECI High Range Minimum VP Minimum Hysteresis Valid Input Signal Range Maximum VN Minimum VN PECI Low Range PECI Ground .
Electrical Specifications 84 Datasheet, Volume 1
Processor Land and Signal Information 8 Processor Land and Signal Information 8.1 Processor Land Assignments The processor land-map quadrants are shown in Figure 8-1 through Figure 8-4. Table 8-1 provides a listing of all processor lands ordered alphabetically by pin name. Figure 8-1.
Processor Land and Signal Information Figure 8-2.
Processor Land and Signal Information Figure 8-3.
Processor Land and Signal Information Figure 8-4.
Processor Land and Signal Information Table 8-1. Processor Pin List by Pin Name Pin Name Table 8-1. Pin # Buffer Type Dir. BCLK_ITP AK39 CMOS O DMI_RX[3] Pin Name BCLK_ITP# Processor Pin List by Pin Name Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-1. Pin Name GFX_VID[6] Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir. Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir. Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-1. Pin Name SA_DQ[16] Table 8-1. Pin # Buffer Type Dir. AT4 DDR3 I/O SA_DQ[56] Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir. SA_MA[14] AT11 DDR3 O SB_DM[4] Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-1. Pin Name Table 8-1. Processor Pin List by Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1.
Processor Land and Signal Information Table 8-1. Pin Name 96 Processor Pin List by Pin Name Table 8-1. Dir.
Processor Land and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1.
Processor Land and Signal Information Table 8-1. Pin Name 98 Processor Pin List by Pin Name Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir.
Processor Land and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1. Dir.
Processor Land and Signal Information Table 8-1. Pin Name 100 Processor Pin List by Pin Name Table 8-1. Dir.
Processor Land and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1.
Processor Land and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type VTT V8 PWR VTT W1 PWR VTT W6 PWR VTT Y33 PWR VTT Y34 PWR VTT Y35 PWR VTT Y36 PWR VTT Y37 PWR VTT Y38 PWR VTT_SELECT AF39 CMOS VTT_SENSE AE35 Analog VTTPWRGOOD AG37 Asynch CMOS Dir.
